Part 1: FET Selection

In the top (control) FET position, we prefer a P-channel FET so that we can avoid a bootstrap rail as discussed in Chapter 1. Of course, the controller IC selected must be commensurate with that desire.

The output power is 5 V×5 A=25 W. If we target an efficiency of over 80% over the entire operating input voltage range (not over the entire load range!), the input power is a max of 25/0.8=31.25 W. In other words, we are allowed a total loss of 6.25 W. To achieve a cost-effective design, we keep in mind that at low line, the top FET conducts for a longer time, whereas at high line, it is the bottom (synchronous) FET that conducts for a longer time. Since both FETs do not see a worst-case dissipation at the same input voltage extreme, we now set their individual dissipation targets to about 4 W (for their respective conduction loss components). The rest is for switching/crossover losses (in the top FET) and other miscellaneous losses like DCR-related losses, capacitor losses, and so on. Note that our FET selection here is based on efficiency targets, and is not directly based on current or temperature stresses. But those should be checked out too as discussed in Chapters 6 and 11. Note also that with this efficiency target, if the output voltage was not 5 V, but say, 1 V (as in many VRM applications nowadays), we would need to really choose FETs of much lower R_DS. If the output voltage is low, for the same power, the currents are much higher. Further, since heating goes as I²R, to keep to within a certain power dissipation budget, the resistance “R” (R_DS in our case) will need to be reduced significantly (~25 times in this example), and/or we will need to choose a much better package too, especially for the lower FET, since the thermal resistance of the currently selected one is rather high. Further, if we want to do 25 W with just 1 V output, that is at 25 A load current, we will actually need to use interleaved converters as discussed in Chapter 13.

For the current application, our first choices for FETs are:

We thus set R_{DS_1}=0.28 Ω and R_{DS_2}=0.08 Ω.

Note: We will see that the selected Drain-to-Source resistances of the two FETs are commensurate with the target dissipation. Observe that the load current is only 1.5 A, yet we have selected a 6 A FET for the top position, and a 21 A FET for the bottom position. However, the big increase in rating (i.e., lower R_DS) of the bottom FET in particular is not only on account of the very low duty cycle at high line (its long conduction time) but also on the significantly worse thermal resistance characteristics it possesses as per its datasheet.

Note: It seems that the voltage stress factor is not sufficient since we are using a 60 V FET in a 57 V max application. However, keep in mind that both the selected FETs have guaranteed avalanche ratings, so they can absorb narrow spikes higher than 60 V. But the application must be evaluated thoroughly to ensure that this FET selection is acceptable.

Part 2: Conduction Losses in the FETs

For the top FET, we expect the conduction loss to be worst at low line (because of the higher duty cycle). From Chapter 7 and the appendix, the switch RMS equation is

Its conduction loss at low line is therefore P_{COND_1_VINMIN}=3.7331²×0.28=3.9021 W (using R_{DS_1}=0.28 Ω).

At high line, for the same FET, we get

Its conduction loss at high line is therefore P_{COND_1_VINMAX}=1.4914²×0.28=0.6228 W (using R_{DS_1}=0.28 Ω).

We now calculate the dissipation in the bottom FET, over both line extremes. We proceed as above, but with the appropriate R_DS and with 1−D instead of D. For this FET we expect worst-case dissipation at high line because of the smaller converter duty cycle that translates into a larger on-time for this FET. At low line, the switch RMS current is

Its conduction loss is therefore P_{COND_2_VINMIN}=3.339²×0.08=0.8919 W (using R_{DS_2}=0.08 Ω). At high line, its RMS current is

Its conduction loss is therefore P_{COND_2_VINMAX}=4.8098²×0.08=1.8507 W (using R_{DS_2}=0.08 Ω).

Finally, we get the total FET dissipation due to conduction losses only, at low and high line as (using the numbers highlighted below)

Note that even at low line, the RMS current in the bottom FET is comparable to that of the top FET, but because we have picked such a low R_DS for the bottom FET, its dissipation is relatively lower at both line extremes. Remember that especially at high line, we still need to account for crossover losses in the top FET, as calculated further below.

Part 3: FET Switching Losses

We are following the steps in Chapter 8 (Figure 8.16 in particular). We are also trying to maintain most of that chapter’s terminology here.

We are assuming that crossover losses occur in the top FET only, as explained in Chapter 8.

As per datasheet of the top FET, we set Qgs=2.3 nC, Vt=2 V, g=8 S (Siemens, i.e., mhos).

Reading from the curves provided in the FET datasheet, we get a much lower value of Ciss=0.45 nF. Therefore, as explained in Chapter 8, we need to apply the following scaling (correction) factor (to account for the voltage coefficient of capacitance)

From the datasheet curves, we get Coss=0.06 nF and Crss=0.04 nF. We need to apply the same scaling factor to these numbers too. We have also expressed all these capacitances in pF rather than nF for the equations further below. So the final values used are

Finally, the capacitances we need, to calculate the intervals are

We also set a Gate drive voltage of 9 V. Assume this is very close to the minimum of the input voltage range. Keep in mind that, typically, we need a Gate drive voltage of about 10 V to drive the selected FETs properly (turn them ON fully), but 9 V will also suffice. We also assume the pull-up drive resistor is 2 Ω.

We set: Vdrive=9 V, Rdrive=2 Ω.

From Figures 8.7 to 8.10, we get the required durations/time constant as

Therefore, the crossover time during turn-on is (at either voltage extreme):

So, the crossover losses associated with turn-on, at both input extremes are

As expected, the crossover losses are higher at high line because of the higher voltage during crossover (combined with the fact that since this is a Buck, the center-of-ramp is fixed, irrespective of input voltage).

Next we calculate the losses associated with turn-off. We set the pull-down as Rdrive=1 Ω.

From Figures 8.11 to 8.14, we get the required time constant and durations as

Therefore, the crossover time during turn-off (at either voltage extreme) is

So, the crossover losses associated with turn-off are

The total crossover loss, therefore, is

However, to complete the switching loss term, we also have to add one more term to the crossover loss above. This is related to the regular dumping of the energy of Cds into the FET at every turn-on. We get, using Cds=38.94 pF (as calculated earlier)

So finally, the total switching loss terms at either input voltage extreme (occurring only in the top FET) are

Note that we have neglected the Gate driver losses calculated in Chapter 8, since they are relatively small, especially when doing dissipation calculations at max load. Driver losses do become significant at light loads, but we have not concerned ourselves with light-load efficiency in this example.

Adding the switching loss to the conduction loss of the top FET, we get the total loss in the top FET

The typical assumption is that the bottom FET has negligible switching losses. So,

Therefore, we get the combined dissipation in both FETs at both input extremes

Both these are well within the 6.25 W planned budget. But we still need to calculate and add a few more, relatively minor, loss terms.

Part 4: Inductor Loss

Our choice of inductance was 2.2 μH. We also know that its rating must be greater than 5 A. A suitable off-the-shelf inductor is therefore the 2.2 μH inductor “UP2C-2R2-R” from Coiltronics, rated 7.5 A. Its DCR is 6.6 mΩ and its maximum volt μ seconds is 9.6 at 300 kHz, corresponding to core losses that are 10% of the total losses for a 40°C rise in temperature.

We need to understand that the inductor has a I_SAT rating of 8.67 A (which is sufficient in our application), and that the stated 7.5 A rating corresponds to the amount of DC current (no ripple and therefore no core loss) that can be passed through the inductor such that it produces a temperature rise of 40°C. In Chapter 2, we discussed ways of validating an off-the-shelf inductor in a particular application, and also estimating its core loss term. This particular vendor, however, provides an easy look-up chart for the purpose, as presented in Figure 19.3. The procedure to use it will become clear soon.

Figure 19.3: Estimating core losses in selected Coiltronics inductor.

First quantify the total permissible dissipation in the inductor. That is

To evaluate the core loss and I_RMS derating in our application, we need to find out the applied voltμseconds (which we are hereby calling “Et” as we did in Chapter 2).

From the datasheet of the inductor, the rated voltμseconds is given by

So, the ratio of the applied voltμseconds to the rated value (at both lines extremes) is

Now looking at Figure 19.3, we see that with 47.15% of the rated voltμseconds and at 1 MHz switching frequency, the percentage of loss from the RMS heating is to be kept to about 91% of the total loss when both are combined to produce a 40°C rise. So basically, this means the total maximum (allowed) copper loss is now only 0.91×0.371 W=0.338 W. This corresponds to a certain reduction in the rated RMS to a value below 7.5 A, one that we can work out easily as presented further below. But right here, we don’t need that value. Because with the given information we can find out the core loss in our application. The logic is as follows: the reason for the required RMS derating is that the core loss makes up for the difference. So, it is easy to realize that the estimated core loss in our application (at high line) is 0.371 W−0.338 W=0.033 W. That makes it 9% of the total rated allowed dissipation (0.371 W) as expected. Similarly, at V_INMIN, the applied voltμseconds is 23.15% of the rated voltμseconds. From Figure 19.3, we see that it intersects the y-axis at 98.2%. So, with the same logic, the core loss at low input voltage is 1.8% the total rated wattage, that is, 0.018×0.371=0.00668 W. We consolidate the results on core loss at both line extremes

Next, we calculate the actual copper loss in our application. But before we do that we should confirm that we are operating within the derated RMS rating of the inductor (with the above-mentioned core losses). If it turns out that the continuous max inductor current in our application is less than the derated rating, we can logically conclude that the inductor’s temperature rise will be less than 40°C; otherwise, it will be greater than 40°C (but that may also be acceptable depending on our worst-case ambient temperature). The derated RMS ratings at both line extremes (in our application) are obtained by the following steps.

The applied RMS is around 5 A as we see below, so it is well within the max derated rating.

The amount of RMS current in the inductor, as per the equations in Chapter 7 and the Appendix is

Note that as expected in a typical CCM inductor design, the RMS current is very close to the DC value (center-of-ramp), so it is not really necessary to use the RMS equation above. We could just use the DC value. The copper loss is

The total inductor loss is finally

Part 5: Input Capacitor Selection and Loss

We start by selecting the capacitor based on a target input voltage ripple of ±0.5% (typical of DC–DC integrated switchers and controller ICs). So, at an input of 57 V, that allows for a peak-to-peak input ripple of 1%×57=0.57 V. We are assuming that the maximum input ripple occurs at maximum input voltage (that statement is true for all topologies). From Chapter 13 we have seen that the actual ripple is a mixture of an ESR-based ripple component (ignoring ESL here) and a capacitance-based ripple component. Let us assume we want to pick a ceramic input capacitor with a typical (low) ESR of 50 mΩ (including lead and trace resistances). From Figure 13.4, we can solve for C_IN:

We pick a standard cap of value of 2.2 μF, rated 63 V or higher. The RMS current in the input cap is (see Chapter 7 and Appendix)

Observe that this is consistent with Curve #4 in Figure 7.7, since the duty cycle closest to D=0.5 is at V_INMIN in our application. The dissipation, therefore, is

Part 6: Output Capacitor Selection and Loss

We set ourselves the task of satisfying three constraints simultaneously, as shown below. The corresponding rationale and design equations are provided in Figure 19.4.

Figure 19.4: Criteria for output capacitor of a Buck converter.

We have minimum output capacitances based on (1), (2), and (3) above, as follows:

Let us therefore pick a standard output capacitance of 33 μF (rated 6.3 V or higher).

We should also double check that the ESR of the selected cap is small enough. As per Figure 7.7, we check the ESR-based portion of the ripple at high line. Refer to Figure 13.5 for the output ripple equations. The ESR should be less than

Most ceramic capacitors will have no trouble complying with this. Suppose we pick a capacitor with ESR=20 mΩ. To calculate dissipation, we need to find out the RMS current in the output cap.

Part 7: Total Losses and Efficiency Estimate

We can now sum over the losses in the FETs, inductor, and input/output capacitors.

Estimated efficiency is

We see that we have achieved our target of greater than 80% efficiency over the entire input range.

Note that so far we have done the calculations based on the ideal duty cycle equation. Actually, we are now in a position to calculate duty cycle more accurately — based on efficiency as explained in Chapter 5. We can then use the new values of duty cycle to run through the above equations once again if we want. Repeated iterations will yield progressively more accurate predictions of efficiency. The improved equations for duty cycle are

Compare the values so obtained to the ideal values of 0.088 and 0.556, respectively. We realize based on the preceding examples, that this increase in duty cycle corresponds with the total loss occurring in the converter.

Part 8: Junction Temperature Estimates

Let us assume that the FETs are mounted reasonably far away from each other, so there are no hot-spots (thermal constriction effects). We also assume that the copper area is large enough (say, a two-sided board, with thermal vias passing through to the copper side below the FETs, and so on).

As per the datasheet of the top FET, we can assume a typical junction to ambient thermal resistance of 25°C/W, and for the bottom FET we assume 40°C/W. We also assume that the local ambient (in the vicinity of the FETs) is 15°C higher than the max room ambient of 40°C. So for the FETs, the effective max ambient is 55°C. We also know that the worst-case for the top FET is at low line, and for the bottom FET at high line. We thus estimate the following worst-case junction temperatures for the top and bottom FETs, respectively.

Both the FETs are rated for a max junction temperature of 175°C, so the above temperatures are considered quite acceptable, though the top FET is running a little too hot (80% temperature derating is a max junction temperature of 0.8×175=140°C).

Part 9: Control Loop Design

We need to refer to Chapter 12 here, in particular Figures 12.25 and 12.26. We assume that the controller is a current mode IC and that it uses a “gm” error amplifier (OTA). Since the switching frequency is 1 MHz, we target a crossover frequency of f_sw/3=333 kHz in keeping with the generic guidelines of current mode control. The max current is 5 A and the time period (of switching) is 1 μs.

We have assumed the reference voltage is 1 V. So, for example, in the voltage divider we could be using 4k as the upper resistor and 1k as the lower one (or 10k and 2.5k, and so on).

We also have an important math relationship in Figure 19.5. Using that, at both voltage extremes, we get

Figure 19.5: A math relationship for current mode control compensation.

Using the relationships in Figure 12.26 we get two recommendations for each voltage extreme, based on a selected gm=0.2 (but note that typically, OTAs have much smaller gm values!)

We see good line rejection at wok as expected. We just pick a close standard value to both.

Set C1=82 nF.

In Figure 12.26, we see than the location of the zero “fz1” is 1/(2πR1C1). As per Figure 19.5, we set it at the location of the load pole. So we are setting fp=1/(2πR1C1). Since we know C1 from above, we can solve for R1 as follows

Once again, we just pick a close standard value.

Set R1=333Ω.

The pole fp1 in Figure 12.26 is set to cancel the ESR zero of the output cap (ESR=20 mΩ).

The ESR zero frequency is f_ESR=1/(2π×ESR×C_O)=241.14 kHz. We thus get

We pick a standard value.

Set C2=2 nF.

We can plot the final results out, based on Figure 12.22 and the selected compensation components. We thus arrive at Figure 12.6, validating our selection and procedure (Figure 19.6).

Figure 19.6: Plotting out the final results of the loop compensation.