Custom ASIC Chips
For companies with the financial and technical wherewithal, an ASIC is the product of choice. These are “real” custom chips, manufactured using the best process technology to deliver the best performance and lowest power consumption. ASICs aren't generic like field-programmable chips, although they are mass-produced, but only for one customer. An ASIC is the best opportunity for a moderately funded company to design, own, and sell its own chips.
In this chapter, we use ASIC as a catch-all term for a group of subtly different products and processes that all solve the same problem. ASIC stands for application-specific integrated circuit, which is meant to suggest that the chip is designed for one specific application or product. That's usually the case, although it's not a requirement. This group also includes products like ASSP (application-specific standard product) and SoC (system on a chip) devices. The differences among these terms are minor, and are covered shortly, but for now we call them all ASICs.
To ASIC or Not To ASIC
The decision whether or not to make an ASIC comes down to cost: Will you realize a good return on your investment? ASIC development is very expensive, so it's a project that's never undertaken lightly, but the benefits can be great: You get exactly the chip you want, in high volume, and all to yourself. You never have to share your ASIC chip with your competitors. Some of today's most popular products, such as cell phones and laptop computers, wouldn't be possible without custom ASICs.
However, the cost of developing an ASIC can make strong managers tremble. As a rough estimate, plan on spending $1 million before the first chip is ready. That's a big investment before you even know for sure if the chip will work. If not, you have to decide whether to pour more time and money into fixing it and making a revised chip. If it does work, you get to decide how much additional money to pour into mass-producing them.
The cost equation for ASICs is a bit schizophrenic. Almost all the cost is up front, tied up in development. After that initial investment, the unit cost of production is relatively cheap. The more chips you make, the more you can amortize the up-front costs across multiple units. Thus, the key to rationalizing an ASIC project is guaranteeing volume production. As a rough rule of thumb, most companies would not consider an ASIC unless volumes were forecast to exceed 50,000 units. At around 250,000 units an ASIC is probably a safe bet, and if you can sell 1 million units, it's a sure thing.
The costs for an ASIC are exactly the opposite as for an FPGA or other field-programmable chip. FPGAs have no up-front development costs at all, but their unit price is comparatively high. ASICs have very high up-front costs but low unit prices (disregarding amortization). A good business manager would then look at the volume cross-over point to see whether an ASIC or an FPGA makes financial sense. That cross-over changes, of course, for every customer, market, and chip type. Plenty of companies have made the wrong decision, buying FPGAs long after they could have amortized an ASIC, or developing an ASIC when the volumes can't support it. ASIC development is a prestige job among engineers and a mark of respect among electronics companies, so there's often some subtle pressure from within the ranks to create an ASIC even if the numbers can't strictly justify it.
Designing an ASIC
ASICs are designed like any other type of complex chip, using the tools and techniques described in Chapter 3, “How Chips Are Designed.” A team of engineers will work for several months plotting out how the chip will work, then moving on to the detailed design. A number of these engineers will be tasked with double-checking and verifying that everything their colleagues do is correct. The team can't afford to design a bad chip, and waiting until the first one is built to test it is too risky. ASIC teams need to assure themselves that every transistor, resistor, and capacitor in their chip is exactly where it should be before they commit their creation to silicon.
Once the ASIC design is finished, the engineers will tape out their chip. Today, this is largely a ceremonial event, but it used to be a big deal. The tape of a new chip design is the final design plan, like the blueprints for a new skyscraper. It's not really a tape any more, and creating the final plans involves pushing a button, but it's still an emotional milestone for the entire design team. Many of the engineers might receive bonus pay if they tape out ahead of schedule.
Between the time they tape out and the time the first chip arrives from the foundry—a period of several weeks—the engineers bite their nails. There's nothing more they can do on their million-dollar project except wait and wonder if it will work.
Full-Custom Designs
A full-custom ASIC design is just what it sounds like: a completely custom chip designed by, and built for, one company. This is easily the most expensive way to make a custom chip, but it's also the most flexible and the only way to achieve the very highest levels of performance. Full-custom ASICs used to be rare but the tools, talents, and technology have all improved to the point where medium-sized electronics companies can create an ASIC every few years. Full-custom ASICs are still not the most common method of making custom chips but they're the path for top-notch performance.
Standard Cell Designs
Ideally, the ASIC design engineers would have free rein to design anything they want. Realistically, however, there might be cost and time limits on what they can do. It's also likely that some chip, somewhere, is at least a little bit similar to what the design team envisions. To save time and money, and to take advantage of existing technology, they can create a “standard cell” design. A standard-cell ASIC sacrifices a little flexibility in return for easier development and lower costs.
Standard-cell chips are a bit like FPGAs in that the custom chip is implemented using an array of already existing functions, like a mosaic made of silicon tiles, called standard cells. It's a modular approach, although a fine-grained one. Standard-cell chips are cheaper than full-custom ASICs because they can be manufactured using semistandard silicon wafers that are partially completed. These require only a little customization during manufacturing, so they're cheaper to produce. They're also far easier and less risky to design because the engineers are not creating everything from scratch. Standard-cell ASICs offer a compromise between ultimate flexibility and moderate cost, and most ASICs are now designed using this method.
Gate Array Designs
Gate array ASICs are another alternative to full-custom or standard-cell ASIC design. Like standard cells, gate array chips trade flexibility for simpler manufacturing and lower cost. Gate arrays are not as finely grained as standard cells, which makes them less flexible. Designing a gate array ASIC is like designing with Lego blocks: They can be connected in innumerable different ways, but the result is always a bit blocky.
Like standard cells, gate array ASICs are built using partially completed silicon wafers that are customized late in the manufacturing process. Chips designed using gate array techniques are a bit bigger in silicon area than standard-cell ASICs (and a lot bigger than full-custom chips), which makes them more expensive to manufacture.
Building an ASIC
Third-party semiconductor factories called foundries manufacture the ASIC chips. Foundries are in the business of providing their manufacturing services to any and all comers. Any customer designing an ASIC can pay for the services of a foundry. The foundry business is competitive, and foundries compete on price, availability, delivery time, performance, and all the other things that make a spirited and healthy market. Some foundries specialize in low-cost manufacturing (although your chips might not be the fastest), whereas others have a reputation for leading-edge technology (although you might have to wait in line and pay premium prices).
ASIC design teams generally have to choose their foundry partner midway through the design process. Some of the chip's design details will depend on who manufactures the chip, and where. These details have to be pinned down before the design is finished.
After the design team tapes out, they send the “tape” (really a big e-mail or a CD-ROM) to the foundry. The foundry might start manufacturing the chip right away, or it might wait until another customer's chips are finished. You might have to wait for weeks, or even months if business is good, before your chip gets to the front of the production queue. After that, it's a matter of a few weeks before the finished chips come out the other end of the production line.
Foundries produce large-volume orders all at once to minimize the down time of their expensive equipment. Smaller orders sometimes have to wait behind larger (and presumably, more lucrative) ones. Very small orders of a few hundred chips will be produced on a shuttle run, which is a collection of different customers' chips processed together on one batch of silicon wafers. Shuttle runs are a compromise for both the customer and the foundry. All the various chips must obviously be compatible with exactly the same production process, because they'll all be processed at once. This means no mixing fast chips with slow chips. Foundries don't like shuttle runs because they're labor intensive and don't produce much revenue, but they're the only way to service small customers, and small customers might one day become big customers.
Each ASIC chip will be marked with your own company's logo, not the foundry's. Foundries are silent partners in ASIC development, and they like to preserve their customers' anonymity as well as their own. There's no easy way to tell what foundry manufactured a particular chip or, in fact, whether it was made at a foundry at all.
Once the chips are ready, they're shipped back to the customer who designed them. This is an exciting day for the ASIC design team and a nervous one for their managers. In Silicon Valley, this event frequently falls around early springtime, because ASIC teams often cram to finish their design before end-of-year deadlines.
Testing the very first chip is sometimes called the smoke test, to see if the chip smokes. Black smoke or white smoke, it's all bad. The wry humor among engineers would have us believe that all silicon chips really run on smoke, not electricity. If you let the smoke out of a chip, it stops working, so obviously, it must be smoke-powered.