Index

A

Ability of a single CPU, 394–395
Abundance of NOPs, 161
operations, 189
Acceleration – local oscillators, 334
Access pattern of a FIR filter, 481
Accessing RAM, 479
Accumulators of DSPs, 100–101
Acquisition of performance data, 348–349
Active power dissipation, 236
Actual FFT computations, 114–115
Actuators, 28–32
sensors, 28, 30
Adaptive filtering, 87, 220
FIR filter, 87
ADC processing, 81
ADCs, 70–71, 151
ADD operation, 438
Adder, 100–102, 124–125, 147–148
Addison-Wesley, 358, 538
Additional phases of optimization, 381–383
Additional tests, 328
Address Modes, 147–148
ADSL, 340–341
Advanced,
emulation technology, 330
event triggering, 326
high-performance DSPs, 44
ILP compilers, 238
Advantage of,
a VLIW DSP architecture, 97
multiple access DSP architectures, 89–90
DSP, 78
RTOS, 297
DSP, 2–3
Alexander Wolf, 158
Algorithm,
bugs DSP systems, 345–346
level optimization Algorithms, 424
modules, 552, 566
Specific Optimizations, 440–441
Technically, 566
performance, 419
structure of DSP algorithms, 163
Amplitude response, 102
Analog I/O – D/A, 28
Analog signal processing, 3–4, 16
Analysis data, 340–342, 365, 398–399
ANSI,
C code, 433
C standard library, 371
standard C code, 360–361
Anti-aliasing filters, 67–68
API,
acronym, 566
calls, 290
definitions, 275
identifiers, 561
Apollo space missions, 299
Application,
level cache optimizations, 500–503
level optimizations, 492
libraries, 360
processing, xi-xiii, 100–101, 270, 390, 419, 489
Programming Interface, 566
space diversity – DSP applications, 324
specific processors, 38
specific – embedded systems, 30
specific gates – hardware acceleration, 28
Architect software, 250–251
Arithmetic DSPs, 123
ARM downloading, 397–398
ARM/DSP interface, 400–401
gains read/write access, 395–396
loads, 398, 400–401
Array of mesh-connected DSPs, 419
ASIC implementations, 89–90
ASP, 4
Assembler, 105, 365–366, 457, 566
Assembly statement, 444
Asynchronous,
events, 22
system calls, 566
Atomic execution, 139–140
Audio,
applications, 66, 94–95, 248
channel processing, 400–401
DSP algorithms, 446
sample processing, 303
Automatic turn-on/off mechanism, 154
Automotive,
DSP applications, 324
signal Processing, 4
system Design, 538
Auxiliary registers, 151–152
Available CPU bandwith, 54
Average performance of a DSP processor, 132

B

Background of CPU operations, 560
Bad loop structure, 444
Bandpass filters, 78, 111–112
Bank,
organization, 128–129
switching, 129
Basic,
debug, 326
FIR optimizations, 89–90
I/O capability, 264
operation of a Fourier, 110–111
tuning capabilities, 326
Battery life of a CD player, 15
Ben Kovitz, 538
Benchmarking, 39–40, 328–329, 335, 358, 421–423, 431–432
benchmarks, 499–500
benchmarks of discrete algorithms, 431
Berkeley Design Technology, 36, 224, 538
Big advantages of DSP, 39–41
Bilinear Transform method, 100
Bit-Reversed Addressing, 2, 103, 116–117, 151–153, 158
Blinking of a LED, 321
Block,
filtering Typically, 106
FIR application, 52–53
of memory PIP_get, 274
Blocking,
problems, 536
semaphores, 286, 288–289
Board failures, 25–26
Boolean expressions, 346
Branch,
control flow, 142
optimization, 198
control, 144
Brian W. Kernighan, 227
Brief History of Digital Signal Processing, 2
Broad spectrum of DSP implementation techniques, xv
Bugs, 161, 321, 345–348, 414
Butterworth filter, 80
Butterworth filters aere, 80
Bytes/data, 423

C

C,
programmer, 54
coding style, 457
coding techniques, 435–436
compiler usage, 217
header file, 567
language implementation of a C++ class, 567
language run-time conventions, 543
optimization, vii, 433–435, 452, 479
performance, 460, 496
programming, 435, 446, 543, 561
programming language, 543, 561
run-time, 542–543, 555
run-time conventions, 543
source code, 46, 416, 433–434, 448, 468, 472–473, 477
source code line, 433–434
source-level debugger, 222
Cache-based DSP systems, 119
Cadence, 414
Calculating,
DSP Performance, 50
worst-case execution time, 301
Calculation of,
average current, 237
periodicity, 314–315
CAN,
controller area network, 49
device, 38, 243, 275
protocol, 49, 293
Capacitive loading of outputs, 234
Capacitor Filters, 78
Careful design techniques, 102
Careless implementation of feedback systems, xiv
CCS, 460, 463
CCStudio, xviii
CCStudio IDE, xviii
CD,
audio, 66, 340–341
player, 15, 65
Cell Phone Responses, 512
Chebyshev filter, 80
Choice of a,
ADC, 69–70
DSP, 35, 48–49
DSP processor, 48–49
deploying modular DSP software elements, 411–412
Circular buffer implementations, 151
CISC architectures, 479
CLK register, 245
CLKOFF, 244
CMOS, 139, 235–236, 257–258
circuit, 139
gate, 235
transistors, 235
Co-processors, 400–401, 251
Code Composer Studio™, xviii, 441–442
Code Composer Studio User’s Guide, 441
Code portability, 175
Color space conversion, 392
Combinations of,
fixed hardware, 42
GPP/uC, 41–42
signal processing algorithms, 385–386
V/F, 243
Commercial DSP RTOSs, 280
Common,
APIs, 273
case of a single CPU, 544
pipeline depths, 140–141
subexpression elimination, 198
Compiler Architecture, 159, 197, 433
Compiler Optimizations, 442, 225
Complex,
condition code, 444
DSP system, 358–360
DSP systems, 351, 413
state machines, 322
system applications, 61
Complexity of,
DSPs, 348
modern DSP CPUs, 161
Component-Based Design Approach, 410
Computation of a FIR algorithm, 94–95
Computational core of many DSP algorithms, 41–42
Computer algorithms, 59
Concepts of RTOS Real-time, 264–265
Concurrency errors, 297
Cons of writing DSP code, 55–56
Context of DSP application development, 351
Core run-time, 541–542, 564
Correct ANSI C, 433–435
Correctness of a computation, 19
COTS Journal, 158
COTS OS, 424
CPU,
calculation, 51
core area, 254
frequency opportunities, 251
functional units, 448
idle modes, 251
loading, 335
operation, 172
processing, 489
processor clock, 155
read/writes, 563
reads, 486–488, 490–492
register, 391, 557, 568
registers, 335, 373, 549
resources, 435
signals, 133
speed, 479, 482, 48–49
stalls, 482–483
throughput measurement, 423
time, 230, 301, 311, 314, 488
utilization estimation, 426
voltage, 233
Creating compliant DSP algorithms, 560
Current generation,
DSP array computer, 423
DSP processor, 421–422

D

D/A converter, 5, 64, 67, 69
DAC operation, 71
Data memory types, 552
Data models DSP C compilers, 557–558
DC,
loading, 258
output voltage, 7
DCT, 391, 400–401
algorithms, 391
Deadline Monotonic,
approach, 312–313
policy, 312
scheduling algorithm tests, 312
scheduling deadline monotonic priority, 311
scheduling Deadline monotonic scheduling, 299
Debug,
challenges, 323
monitors, 322
of code, 348
versions of algorithms, 552
Debugging,
application, 331
DSP code, 222
DSP-centric, 411
DSP systems, 358–359
DEC Alpha systems, 567
DEC VAX, 567
Decode, 394, 56, 137–138, 141–142, 144, 146, 158
Decompression, 14–15, 30, 400–401
Dedicated logical DMA channel, 565
Deeper discussion of DSP architectures, 47
Design,
algorithms, 355
automation, 537
challenges, 25–26, 358–359
DSP applications, 230
FFT routines, 119–120
patterns, 416
technologies, 410
Designing IIR filters, 98–100
Designing simple DSP, 270
Desktop PC systems, 324
Development of,
a DSP application, 220
efficient algorithms, 60
SoC technology, 394
Development Tools, xviii, 330, 351, 360–362, 384, 411–413
Device,
driver software, 358
independent I/O sub-system, 541
simulation, 533–534
DFT implementation, 165
DFTs, 112–113
Diagram of a,
DSP, 47, 368–369, 389
DSP application, 368–369
Different,
DSP devices, 136
DSP optimization techniques, 208
levels of DSP debug capability, 326
Digital counters, 322
Digital Filter Design Using C, 97
Digital output, 7, 14, 56, 67–68, 389–390, 392
Digital Signal Processing, vii, xi, xiv-xvii, 1–7, 16–17, 36, 59, 61, 74, 109, 352–355, 360–361, 419,
engineers, 61
Digital TVs, 39–41
Digital Video Systems, 392
Digital-to-analog,
conversion, 5, 7–8, 70
converters, 2–3, 72
Discrete Cosine Transform, 400–401
Discrete Fourier Transform, 60, 112–113, 120–121, 165, 224
DMA, 263, 553–554, 561
capable machine, 172
channel, 134, 560–561, 563, 565
completion status register, 179
controllers, 2–3, 132–134
data transfer, 489
devices, 132–133
hardware status register, 179
interface, 563
polling operation, 179
processing chain, 498
resource utilization, 161
scheme, 560
status register, 179
syncs, 370
transfers, 133, 176, 563, 565
usage, 560
Double buffering, 291, 489–492
Drivers, 43, 56–57, 245, 263–264, 295–296, 348, 358–359, 416–418
DSL, 16, 229
modems, 16
DSP,
algorithm analysis, 60
algorithm code, 54
algorithm developers, 539
algorithm development, 355–357, 539, 542–543, 561
algorithm development standards, 355–357
algorithm optimization, 227
algorithm standards, 355–356
algorithm technology, 539
application code, 166
application developer, 351
application optimization, 160
architectural features, 47
ARM loading, 392
array architecture, 420
auxiliary registers, 151–152
basestation applications, 324
benchmark, xviii, 426
BIOS developers conference, 320
BIOS RTOS, 269–270, 273–274
C compilers, 552–553, 557–558
caches, 130
centric kernel, 395
code/data, 398
code generation, 97
compiler efficiency, 54–55
compiler optimization, 227
compiler specific instructions, 379
complexity, 352–353, 358–359, 363–364
computer bus architectures, 132–133
controller module, 400–401
controllers, 132–133, 153
core features, 421
core voltages, 234
COTS algorithms, 416
data space, 395–396
debug technologies, 324
debugger, 222, 335–336
design, vii, 36, 42–43, 60, 98–99, 153–154, 230, 352–354, 360–361, 389, 538,
design tools, 538
development activities, 343–344
device architectures, 236
devices FIR implementations, 89–90
emulation capability, 337–339
emulators, 335
engineering, 351, 537–538
family, 150, 178, 202, 309
filter, 102
functional resources, 189–190
hardware capabilities, 411
hardware platform, xiv
hardware technology, 411
Harvard architecture, 164
IDE editor, 371
IDE’s, 365
internal data memory, 180–181
internal registers, 397–398
linker technology, 343–344
memory space, 135
microprocessor instruction, 332–333
microprocessors, 89–90
MIPS, 365, 262
modeling tools, 360
modules, 417–418, 562
on-chip memory, 370, 120, 297–298
operations, 119, 235
ptimization effort, 160
out of reset, 397–398
performance, 333, 378, 381–383, 420, 460, 554, 565, 8, 10, 15–16, 41–42, 50, 126–127, 132, 155–157, 165–166, 227, 251
platforms, 413, 415, 418
ports, 135, 276
power consumption, 160, 234
power information, 256–257
power optimization, 256–257
processor activity, 334–335
processor bus activity, 334–335
processor nodes, 428–429
program, 343–344, 398, 416, 541–542, 557–558, 153, 277–279
programmer productivity, 411
programming, 108, 216–217
real-time systems, vii, 298, 343–344, 379, 525
registers, 89–90, 128, 151–152, 203–204, 219–220, 335, 337, 397–398, 558
RTOS implements sempahore mechanisms, 298
RTOS package, 275
RTOS task, 266–267
software debug, 322–323
software development process, 223
software technology, vii, 411, 418
solution providers, 165–166
source code, 197
specific algorithms, 395
status register, 398, 180
subsystem, 391–392
system development landscape, 323
system development process, 385–386
timer functions, 277–279
toolboxes, 360–361
vendor, 340–341
Dual-access memory, 547–548, 551
DVD players, 31–33
Dynamic,
algorithms, 298–299, 313–315
nature of memory usage, 423
power management, 234
RAM, 43
Random Access Memory, 480

E

Easy C code optimization, 452
EDF scheduling algorithm, 314–315
EDMA, 368–369
channel, 275–276
DSP, 276
EEPROM, 38
Effects of temperature, 238
Efficiency of an FFT, 120–121
Electric motors, 8
Electrical signals, 335–336
ELSE option, 508
Embedded,
Alternative, 158
Microprocessor Core Design, 410
Processor Consortium, 224
Software Primer, 349
Systems Design, 322
EMIF buses, 136
Emulation Capabilities, 326, 331–332, 335–337
controller, 331–332
hardware, 330, 333, 525–526, 528
Emulator Physical, 331–332
Emulator software, 330
Enable/Disable,
byte, 403
HPI interface, 403
End-to-End analysis, 531–532, 536
Endian byte, 557–558
Enumeration, 509, 511–514, 519–521, 523
EPROM, 2
Example of a,
complete DSP Solution, 57–58
DSP applications, 48
DSP reference framework, 57–58
I/O devices, 48–49
implementation of a Delay algorithm, 462–463
DSP architecture, 238
MAC instruction, 124
simple CSL, 275–276
simple FFT butterfly structure, 114–115
application specific DSP, 35
SoC processor, 389–390
Examples of,
analog signals, 5–6
aperiodic tasks, 269
applications, 38, 303
arithmetic operations, 59
bad loop structure, 444
DSP, 153, 201, 324, 340–342, 562
dynamic best effort algorithms, 299
dynamic scheduling policies, 298–299
real world signals, 1
system resources, 262
Execution,
control, 323, 326, 346–348, 398–399
efficiency, 23, 263
environment, 358, 421
predictability, 132

F

Family of DSPs, 202, 435
Fast processors, xv, 391
Faster algorithms, 114–115
Feature of DSPs, 103–104, 147–149
Feedback mechanism of IIR filters, 95
FFT,
algorithms, 116, 119
approach, 114
bit-reversed, 2
butterfly, 114–116
calculations, 153
code, 119
implementation issues cache, 119
operation, 114–115
waterfall, 363–364
Field Test Factory, 358–359
Field testing, 381
Field-programmable gate arrays, xv-xvi
FIFO, 322
order, 268
scheduling algorithm, 270
scheduling of threads, 270
FIR,
block, 52–53, 417
code, 97, 105
counterpart, 99
diagram, 46
filter code, 105
filter processing, 123
filter routine, 374
filtering, 82, 94–95, 128
filtering techniques, 94–95
linear-phase distortion, 94–95
process, 150
routine, 374, 50–51
structure, 94–95
system, 89–90
FireWire®, 57–58, 331–332
First level cache, 480
First-in/first-out, 480
Fixed-point DSPs, 355–356, 94–95
Fixed-priority scheduling algorithms, 298
FLASH, 348, 38, 70, 136
Flashing LED, 28
Floating-point, 454, 456, 473
ADDs, 456–457, 469
control, 559
DSPs, 460, 2–3, 125
numbers, 125–126
FPGA, xv-xvii, 28, 36–45, 82, 119, 322, 355–356
designers, 39–40
devices, 44

G

General Programming Guidelines, 217, 542–543
General-purpose,
DSP software, 500–504
preserve, 558–559
scratch, 558–559
Geometries, 136–137, 235
Global,
breakpoints, 363
optimizations, 197, 220
registers, 557–558, 564
writeback-invalidate, 491–492
Good C compilers, 44
GOTO statements, 444
GPIO, 49, 241
GPP programs, 415
Graphical user interface, 254, 362–363

H

Hard Real-Time Environment, 19–20, 565
Hardware/Software emulation, 525–526, 528
HDTV, 35
Heap memory, 555, 563
Heavy duty code optimization, 114–115
Heterogeneous memory systems, 392
High Level Design Tools, 351, 358–360
Higher performance DSP, 333, 10, 41–42
Host,
CPU, 335–337
development tools, 360–362
port interfaces, 135

I

I/O bandwidth, 25, 159, 420–422, 430
calculation, 51
completion, 269
controllers, 528
drivers, 57
interface, 51
interfaces, 541
load, 256–257
peripheral independence, 541–542
port, 297
requirements, 533
signals, 327
space, 214
spaces, 157
transfer, 264
utilization, 420–422, 430
utilization performance, 421–422
IBM, 567
IC vendors, 327
ICE, 323
modules, 323
ID, 113–114, 402
IF statement, 508
IIR,
algorithm, 97
code, 97
filter design, 98–99
filter feedback mechanism, 100–101
filter IIR, 98
ILP, 43, 238
Impact of re-usable DSP software, 415
Implement FIFO, 151, 290
Improper return codes, 346
Improving DSP processing, 157
Improving throughput of FIR, 391
Independent data structures, 194
Individual CPU utilization, 300–301
Inefficient code, 379, 60, 167, 190, 210
Inexpensive evaluation boards, 385
Infinite Impulse Response Filters, xi-xiii, 94–95
Infinite Loop, 370–371, 155, 270
Information compiler, 449, 452–454, 474, 209–210, 214, 219
Infrared port, 31–32
Init Run, 553
Inlining, 199, 214
Input/Output, xv-xvii, 367, 376–377, 421–423, 425, 461–462, 547, 563, 28, 35, 48–50, 56–57, 62, 80–81, 96, 100–101, 262, 271–272, 280, 295–296
Instruction pipelines, 137
Integer fixed-point DSPs, 94–95
Integration of algorithms, 540, 560
Internal,
control logic, 126–127
CPU activity – Instruction complexity, 234
IC tests, 328–329
memory accesses, 119, 136–137, 234
RTOS, 272–273
Internet, 567, 14, 36
Interoperability of DSP algorithms, 553–554
Interpolation, 360–361, 71–72
Interpretation of cache, 499–500
Interrupt Flow, 142, 310
Interrupts, 31–34, 48, 133, 145–146, 195–196, 214–215, 257–258, 262–264, 266–268, 272–274, 277–278, 284–285, 287–289, 292–293, 295–296, 304, 309–311, 314–315, 337–339, 347–348, 370–371, 375, 398, 419–420, 428–429, 476, 529, 531, 541, 543, 546, 553–556, 559
Inverse discrete Fourier, 113
IO devices, 314–316
ISA card, 335–337

J

JPEG, 394, 400–401
encode, 394
JTAG,
bounday, 327
capability, 328–329
connection, 335–337
interface, 365
port, 326, 332–333, 335–336

K

Kalman,
Adaptive Filter, 360–362
Adaptive Filter block, 360–362
Kalman filter, 360–362

L

L-Unit, 157
Labview, 340–342
Large DSP systems, 351
Last In First Out, 555
Last N inputs, 108
Latency, xi-xii, 20, 38, 43, 48, 127, 130, 136–137, 139–140, 143, 185, 200, 202, 245, 248, 258, 263–264, 266, 280, 285, 309–310, 312, 314–315, 347, 480, 493, 500–504, 545, 555–556, 559, 563–564, 567–568
LEDs, 321, 244
Library of DSP, 50–51
Life cycle costs, 360–362
LIFO, 555
Linear-phase FIR filter, 86–87
Link failures, 25–26
Link hardware events, 370–371
LMS instruction, 88, 149–150
Load-store architecture, 283
Local buffering of loop instructions, 145
Local registers, 557–558
Local variables/pointers, 218
Logical DMA channel abstraction, 560
Logical errors, 346
Long latencies, 245
Loop,
buffers, 235, 248
distribution, 500–503
function calls, 445
optimizations, 208
Low leakage process technology, 235–236
Low level simulations, 526–527
Low power devices, 12
Low power DSPs, 12–13
Low-leakage CMOS, 257–258
Low-pass filters, 67–68, 100
LSB, 69–70, 218

M

M-Unit, 157
MAC hardware unit, 106
MAC operation, 85, 89–91, 124, 149, 437
Main CPU, 132–133, 243, 394–395
Main drawback of a digital FIR filter, 89–90
Main external memory, 203–204
Main types of DSP applications, 48
Many advanced DSP architecture styles, 2–3
Many applications of low-cost DSPs, 11
Mapping of addressable memory, 483
Marketing information, 431
MATLAB function remez, 92
MATLAB script, 92
McBSP – Multichannel, 49
Measurement Program Reference Manual, 538
Media Stream Processing Unit, 565
Medium priority task Taskmed, 316
Memory usage, 159–160, 237, 423, 433
Memory-mapped DMA, 173
Microsoft’s Windows NT, 263
Microsoft Visual C++ IDE, 363
Minimum Nyquist, 66
MIPS density, 324
Model of a DSP starter, 368–369
Modern,
architectures, 43, 286
chips, 480
CPUs, 132, 161
DSP applications, 414, 261
DSP devices, 234–235
DSP IDEs, 375
DSP system development, 357
DSP systems, 261
Most significant algorithms, 543
Motion Correlation, 400–401
Motion Estimation, 400–401
Motor modeling, 9
Motorola, 49, 131, 134, 141, 146–147, 158, 567
MPY instructions, 448
MRI, 113–114
MSI, 2
Multicore,
approaches, 389
SoCs, 410
Multiprocessor,
debug, 335, 363
systems-on-chips, 410
Multirate,
DSP systems, 299–300
processing, 360–361
sampling techniques, 71–72
Multithreaded programs, 543

N

N data, 113–115, 165, 199
N registers, 199
N-bit converter, 69
NASA, 299
National Instruments, 254–255
NEC, 2
New DSP architecture, 423
Next generation DSP-based array processor, 419
Next-generation IDE environment, 411–412
NMOS, 2
Nodes, 25–26, 235–236, 428–429, 526–527
Nonpreemptive techniques, 299–300
Nyquist,
filter, 80
sampling, 113

O

On-chip,
DARAM, 550–551
debug facilities, 331, 340–342
debugging, 332–333
DSP memory, 370, 120, 297–298
memory – internal memory, 102, 130, 176, 180–181
memory of a DSP, 549
RAM, 105
Open-loop systems, 9–10
Optimal cache usage, 433
Optimization of an algorithm stream, 430
OS,
level, 424, 242
power manager, 254
scheduler, 299–300
support, 252
Output oscillations, 95
Oversampling, 71–72

P

Parallel,
architecture – DSPs, 102
DSPs, 102, 134, 147–148
operations, 234, 236, 394
processing DSP support, 2–3
Parameter passing errors, 346
Parks-McClellan algorithm, 91
Partition, 28, 237, 257–258, 433, 443, 448, 467, 475, 549–550
PC developers, 362
PCP protocol, 531, 319
Peripheral I/O area, 254
Physical DMA channel, 560–561
Ping, 52, 291, 368–369, 371, 373–374
Pipeline of modern DSPs, 554–555
Pointer Read-only, 559
Polling, 178–179, 248, 251, 257–258, 261
Portable DSP debug environments, 324
POSIX, 528
Power,
API, 246
DSP architecture, 153–154
DSP solution, 14
DSP-based system solution, 15
of today’s DSPs, 417–418
sensitive SoC devices, 398–399
saving DSP architectures, 238
Powerful feature of RMA, 429
Practical Software Requirements, 538
Practitioner’s Handbook, 537
Pre-emphasis of a signal, 546
Preconditions, 510, 282
Preemptive,
RTOS, 283
schedulers, 268
scheduling strategy, 311
Preliminary design, 525, 533
Presence of ‘NOP’, 468
Probe Points, 363, 378
Process of symmetrical FIR implementation, 89–90
Processing multidimensional FFT, 135
Processing power of DSP, 248–249
Processor architectures, 43, 132, 136–137, 158, 238
Production DSP compilers, 161–162
Production hardware array of DSPs, 424
Program control, 323, 462, 140
Program memory algorithm code, 555
Programmable DSP, xv-xvii, 5–6, 15, 39–40, 43, 85, 358–359
cycles, 43
processor, 39–40, 85
processors, 358
solution, 15
solutions, 358
Programmable SoCs, 410
Programming DSPs, 39–40, 158
Programming real-time DSP-based systems, 161–162
Project management, 376–377
Prototyping, 41–42, 351, 358, 360–361, 385–386, 421–423, 431–432, 525–526, 531, 533–534, 536–537, 41–42

Q

Q format, 103
QoS, 385
Quick download time, 348

R

Radar signal processing sampling, 66
RAM space, 264
RAM technology, 126
Random replacement, 480
Rapid development of DSP-based systems, 360
Rapid production of robust DSP application software, 413
Rapid Response, 266
Rate Monotonic Scheduling, 298–300, 304–306, 312–314, 319–320
Rate of C, 292
Rate of P, 292
Rate of T, 6
Real-time analysis, 362–365, 398–399, 432, 529, 537, 298
data collection, 326
DSP developer, 360–362
DSP system, 345, 347
Event Characteristics, 22
nature of DSP, 347, 19
nature of DSP systems, 347
programs, 31–34
Signal Processing Systems, 410
Recursive filter feeds, 95
Refrigeration compressors, 11
Reliability, 3, 5, 8–9, 329–330, 357, 534–537
Removal of functions, 208
Removal of unused assignments, 208
Replacement of costly hardware, 9
Request DMA transfers, 565
Required elements of a DSP Algorithm Standard, 539
Resource allocation graphs, 282
Results of an FFT, 135
Return pointer Scratch, 559
RF, 58
RISC, 395, 400, 418, 479
device, 400
RM scheduling, 313–314
RMA scheduling technique, 313
ROM,
code, 397–398
monitors, 322
programmer, 322
Route McBSP, 370
RTDX, 340
RTOS, 214–215, 241–243, 245–246, 261–280, 282–283, 285, 288, 290, 292, 297–300, 310, 319–320, 340–341, 411–413, 417–418
Rules of Thumb, 538

S

Sampling errors, 6
SBP, 531
Scalability, 340–342
Scalable Software, 358
Scales, 125–126, 238, 248–249
Scheduler latency, 312
Scheduling Behavior, 300
Second-order FIR filter, 84
Semaphore, 179–180, 214–215, 274, 285–290, 295–298
Sequence enumerations, 509
Server systems, 540
Signal filtering/shaping techniques, 16–17
Signal processing A DSP framework, 56–57
Signal processing blocks, 360–361, 14
Signal source blocks, 360–361
Simulation packages, 526
Simulink Application Manager, 538
Single cycle MAC, 141, 158
Small footprint RTOSs, 281
Small loops, 171
SmartMedia cards, 136
Snoop-Invalidates, 489
SoC,
hardware design, 410
model, 329, 395, 400–401
processing elements, 400
programming model, 400–401
software development, 395
solution, 400–401
Soft real-time systems, 529, 19–20
Software code, 424–425, 439–440, 500–503
Solaris features, 430
Solaris threads, 528
Source-Level Loop Optimization, 97
Sources of latency, 140
SPARC systems, 567
Speech signals, 546, 5–6, 79, 110–111
SPI – Serial peripheral interface, 49
Sporadic I/O activities, 309
SRAM, 43, 136, 234, 264, 480, 483, 486–490, 499–500, 547–548
Stack memory, 555, 563, 214
Static power management, 234
Static RAM, 43
Static Random Access Memory, 480
Structure of many DSP algorithms, 346
Structured Programming, 547–548
Structuring C code, 435–436
Successive approximation ADCs, 70
Sun system, 528
Sun workstations running Solaris, 430
Superscalar processor architectures, 132
Symmetrical FIR, 89–91, 149
Synchronous DRAM, 423, 43
Synopsys, 414
System algorithm research, 385
System buses, 322–323, 331–332
System-on-Chip, 410
Systems Primer, 347
Systems Programming, 31–34, 158

T

Tag RAM, 484, 488
TAP controller, 328
Target array of DSPs, 424–425
Target DSP device, 340–341
Task synchronization requirements, 314–316
Tasklow’s priority, 317
Telephony, 48, 541, 565
Testing of programs, 287
Third level cache, 480
Thorax bags actuators, 29
Thrashing, 48, 119–120, 230–231, 391, 496–497, 500
Threads, 57, 246, 264–265, 270, 277–279, 283–284, 292–293, 297, 528, 543–546, 554–555, 557–558, 566–568,
Throughput of DSP algorithms, 102
TI compiler, 443–444, 566
TI DSPs, 445, 147–149
TI’s floating-point DSPs, 460
Topic of reusable DSP software, 358
Trace capabilities, 326
Traditional CPU, 391
Transfer Function IIR filters, 98
TRST input, 328
TTL, 2
Typical applications, 39–40
Typical line of audio DSP code, 446

U

UART – Universal asynchronous receiver-transmitter, 49
UNIX systems, 80–81
URL, 260, 554, 560–561
USB – Universal serial bus, 49, 331–332
Use of,
C language, 543
DSP on-chip registers, 558
floating-point, 557–558
peripherals, 553–554

V

Validate/debug – Functional correctness, 381
Valuable L unit, 456
Value || LDW, 439
Value MPYSP, 439
Value of M, 92
Variable declaration, 218
Variable length coding, 394, 400–401
Various types of DRAM, 48–49
VCRs, 31–33
VHDL simulation measurements, 426
Video Acceleration block, 391–392
Video capture, 303
Video processing applications, 400–401
VLC/VLD, 394
VLCD module, 394
VLIW,
architecture, 43, 97, 155–158, 182
device, 190–191
devices, 182
DSPs, 188
instruction, 2–3, 16, 43, 155, 238, 423
load, 156
Voltage/Frequency, 235–236, 243–244, 247–248, 251–253, 256–258
von Neumann architecture, 126–127
VOP gateway, 129–130
VPSS acceleration module, 393
VPSS processing element, 392
VRTX, 319–320

W

Watermarking, 400–401
Webster’s English Language Dictionary, 197
Wider system buses, 323
WinCE, 415
Wireless LAN, 16
World Wide Web, 15
Worst-case,
CPU requirements, 557
DMA resource requirements, 560
Write Multiplies Correctly, 227
Writeback-Invalidate command, 492
Writeback-Invalidate operation, 492
Writing audio DSP code, 445
Writing C code, 433–435
Writing DSP algorithms, 54–55
Writing OutBuffB, 489

Z

Zeidman, 410
Zigzag, 394
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