The logic implementations of a network-on-chip (NoC) directly determine its overhead, performance, and efficiency. The network latency depends on router pipeline delays; a primary design goal of router architectures is to reduce pipeline delays in a low-cost way. Buffers consume a significant portion of NoC power and area budgets. Dynamically sharing buffers among virtual channels (VCs) or ports can reduce buffer amount requirements, while maintaining or improving performance. Also, avoiding network congestion is essential to optimize the throughput and latency. Efficiently supporting multicast or broadcast communications is important for the overall performance of many-core systems. While packet switching networks are appropriate for unicast communications, bus structures are more suitable for multicast communications. Combining bus structures and packet switching networks can satisfy the requirements of both types of communications. On the basis of these observations, this part describes the NoC logic implementations in three chapters.

With an increasing number of cores, the NoC communication latency becomes a dominant factor for system performance owing to complex operations per network node. In Chapter 2 we try to reduce the communication latency by proposing single-cycle router architectures with wing channels, which forward the incoming packets to free ports immediately with the inspection of switch allocation results. Also, the incoming packets granted wing channels can fill in the time slots of the crossbar switch and reduce the contentions with subsequent packets, thereby increasing throughput effectively. The proposed router supports different routing schemes and outperforms several existing single-cycle routers in terms of latency and throughput. Owing to fewer arbitration activities, it achieves power consumption gains.

Chapter 3 studies the design of efficient NoC buffers. We first introduce a dynamically allocated VC design with congestion awareness. All the buffers are shared among VCs, whose structure varies with the traffic condition. At a low rate, this structure extends the VC depth for continual transfers to reduce packet latencies. At a high rate, it dispenses many VCs and avoids congestion situations to improve the throughput. Then, this chapter presents a novel NoC router with a shared buffer based on a hierarchical bit-line buffer. The hierarchical bit-line buffer can be configured flexibly according to the traffic, and it has a low power overhead. Moreover, we propose two schemes to optimize the router further. First, a congestion-aware output port allocator is used to assign higher priorities to packets heading in lightly loaded directions to avoid network congestion. Second, an efficient run-time VC regulation scheme is proposed to configure the shared buffer, so that VCs are allocated according to the loads of the network.

Chapter 4 presents a virtual bus on-chip network (VBON), a new NoC topology of incorporating buses into NoCs in order to take advantage of both NOCs and buses in a hierarchical way. This design is proposed on the basis of the following observations. Compared with transaction-based bus structures, conventional packet-based NoCs can provide high efficiency, high throughput, and low latency for many-core systems. However, these superior features are only applied to unicast (one-to-one) latency noncritical traffic. Their multihop feature and inefficient multicast (one-to-many) or broadcast (one-to-all) support make conventional NoCs awkward for some kinds of communications, including cache coherence protocol, global timing, and control signals, and some latency critical communications. The proposed VBON topology dynamically uses point-to-point links of conventional NoC designs as bus transaction links for bus request. This can achieve low latency while sustaining high throughput for both unicast and multicast communications at low cost. To reduce the latency of the physical layout for the bus organization, the hierarchical redundant buses are used. The VBON can provide the ideal interconnect for a broad spectrum of unicast and multicast scenarios and achieve these benefits with inexpensive extensions to current NoC routers.