Table of Contents

Cover image

Title page

Copyright

Preface

About the Editor-in-Chief and Authors

Editor-in-Chief

Authors

Part I: Prologue

Chapter 1: Introduction

Abstract

1.1 The dawn of the many-core era

1.2 Communication-centric cross-layer optimizations

1.3 A baseline design space exploration of NoCs

1.4 Review of NoC research

1.5 Trends of real processors

1.6 Overview of the book

Part II: Logic implementations

Introduction

Chapter 2: A single-cycle router with wing channels

Abstract

2.1 Introduction

2.2 The router architecture

2.3 Microarchitecture designs

2.4 Experimental results

2.5 Chapter summary

Chapter 3: Dynamic virtual channel routers with congestion awareness

Abstract

3.1 Introduction

3.2 DVC with congestion awareness

3.3 Multiple-port shared buffer with congestion awareness

3.4 DVC router microarchitecture

3.5 HiBB router microarchitecture

3.6 Evaluation

3.7 Chapter Summary

Chapter 4: Virtual bus structure-based network-on-chip topologies

Abstract

4.1 Introduction

4.2 Background

4.3 Motivation

4.4 The VBON

4.5 Evaluation

4.6 Chapter summary

Part III: Routing and flow control

Introduction

Chapter 5: Routing algorithms for workload consolidation

Abstract

5.1 Introduction

5.2 Background

5.3 Motivation

5.4 Destination-based adaptive routing

5.5 Evaluation

5.6 Analysis and discussion

5.7 Chapter summary

Chapter 6: Flow control for fully adaptive routing

Abstract

6.1 Introduction

6.2 Background

6.3 Motivation

6.4 Flow control and routing designs

6.5 Evaluation on synthetic traffic

6.6 Evaluation of parsec workloads

6.7 Detailed analysis of flow control

6.8 Further discussion

6.9 Chapter summary

Appendix: logical equivalence of Alg and Alg + WPF

Chapter 7: Deadlock-free flow control for torus networks-on-chip

Abstract

7.1 Introduction

7.2 Limitations of existing designs

7.3 Flit bubble flow control

7.4 Router microarchitecture

7.5 Methodology

7.6 Evaluation on 1D tori (rings)

7.7 Evaluation on 2D tori

7.8 Overheads: power and area

7.9 Discussion and related work

7.10 Chapter summary

Part IV: Programming paradigms

Introduction

Chapter 8: Supporting cache-coherent collective communications

Abstract

8.1 Introduction

8.2 Message combination framework

8.3 Bam routing

8.4 Router pipeline and microarchitecture

8.5 Evaluation

8.6 Power analysis

8.7 Related work

8.8 Chapter summary

Chapter 9: Network-on-chip customizations for message passing interface primitives

Abstract

9.1 Introduction

9.2 Background

9.3 Motivation

9.4 Communication customization architectures

9.5 Evaluation

9.6 Chapter summary

Chapter 10: Message passing interface communication protocol optimizations

Abstract

10.1 Introduction

10.2 Background

10.3 Motivation

10.4 Adaptive communication mechanisms

10.5 Evaluation

10.6 Chapter summary

Part V: Epilogue

Chapter 11: Conclusions and future work

Abstract

11.1 Conclusions

11.2 Future work

Index

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