Index
Note: Page numbers followed by f indicate figures.
A
Activation energy 156
ADCs See Analog/digital converters (ADCs)
Aging mechanisms 156
A-law algorithm 131
Alkaline batteries 150
analysis 67
signals 4
circuit analysis methods 67–68
circuit design 65
discrete transistors 65–66
electret microphones 88–90
input and first stage 77–80
passive components 77
specifications and topology 77
tolerances 77
noise, interference and crosstalk 86–88
op amps 83–86
power amplifiers 81–83
specifications 66–67
conversion specifications 130–132
dual-slope converter 135–136
integrated circuits 129
internal capacitor 135–136
MOSFETS 133
Nyquist rate 129–130
on-resistance and off-resistance 133
Analog simulation 16
Apple configuration 126–127
Application profiles 37
Arbitration 30
ARM Cortex-M3 CPU 3–4
Arrhenius equation 156
Arrhenius prefactor 156
Astablemultistable multivibrator 114–117
Asynchronous connectionless (ACL) links 38
Attribute protocol 38
Atwater Kent Manufacturing Company 166
B
Back electromotive force (Back EMF) 177
Basic input/output system (BIOS) 162–164
Battery 149
capacity 149
chemistry 150
constant current charging 150
constant voltage charging 150
dropout voltage 150
electrochemical cell 149
end-of-discharge voltage 149–150
end-of-life voltage 149–150
energy density 149
equivalent series resistance 150
fast charging 150–151
midpoint voltage 149–150
self-discharge 150
trickle charging 150
Baud 26
Bel 6
Bessel approximation 112
Bias voltage 67
BIOS See Basic input/output system (BIOS)
low-impedance load, bipolar transistors 206–209
AC circuit 202–203
component value formulas 204–206
DC circuit 202–203
large signal analysis 204
load line analysis 203
cascode amplifier 198–200
common base amplifier 198
common collector amplifier 198
common emitter amplifier 197–198
current sources 200–201
differential amplifier 200
base-emitter path 193
BJTs 196
characteristic curve plot 194–195
collector-emitter path 193
curve tracer circuit 194–195
cutoff region 196
Ebers-Moll model 196
forward active region 196
gain-bandwidth product 193–194
saturation region 196
Biquadraticbiquad form 103–104
Bleeder resistors 146
Bluetooth Low Energy (BLE) 38
Board-level design 2–3
Board support package (BSP) 162
Branch current method 11
Breadboards 166
Bulk transfers 34
Butterworth approximation 110
C
CAN bus 29–30
Capacitive and inductive circuits 9–11
Capacitor law 145
Chebyshev approximation 111
China headset configuration 126–127
Circuit analysis 11–14
Class A amplifier 82
Class B amplifier 82
Class C amplifier 82
Class D amplifier 82
Clear to send (CTS) 26–27
Clock jitter noise 132
auxiliary devices and circuits 57–59
fanin 44
input and output signal specifications 46
load capacitance 44–46
logic values 46
noise immunity 46
output current 45–46
static electrical discharge, sensitive to 55–56
Colpitts oscillator 120
Common base amplifier 198
Common collector amplifier 198
Common drain amplifier 73
Common emitter amplifier 197–198
Common mode rejection ratio (CMRR) 86
Complex programmable logic devices (CPLDs) 53–54
Computer-aided design (CAD) 53–54
Conductance 7
Configuration file 53–54
Constant current charging 150
Constant voltage charging 150
Controlled source 68
Control transfers 34
Corner frequency 6
Crosstalk 88
Crystal oscillator 119
Current gain 66
Cyclic redundancy checks (CRCs) 34
Cypress PSoC 5LP 3
D
DACs See Digital/analog converters (DACs)
Darlington pair 146
Data circuit-terminating equipment (DCE) 24
Data link layer 23
Data set ready (DSR) 26
Data terminal equipment (DTE) 24
Data terminal ready (DTR) 26
Daughter cards 17
Design methodology 16–17
Design partitioning process 174
conversion specifications 130–132
impedance 132
integrated circuits 129
maximum voltage 133
Nyquist rate 129–130
op amp circuit 133
thin-film resistors 133
Digital filters 112–113
function 41
logic signal levels 42
power consumption 42
state transition diagram/register-transfers 41
Digital signal processor (DSP) 3
Diode bridge 143–144
law 196
piecewise linear approximations 117
transistor junctions 196
analysis 67
signals 4
Distortion 66
DMA protocol 172
Drain-source voltage 70
DRAM interface 163
Dropout voltage 150
analog/digital boundary 173
circuit analysis methods 160
precision and 160
E
Earthed ground 142
Ebers-Moll model 196
Edge-triggered register 51
Electret microphones 88–90
conductance 7
electrical current 7
electrical potential/voltage 7
EMF 7
Ohm’s law 7
resistance 7
Electrolytic capacitors 146
Electromagnetic interference (EMI) 55–56
Electromotive force (EMF) 7
Elliptic approximation 111–112
board-level design 2–3
bottom-up design methods 3
capacitive and inductive circuits 9–11
circuit theory 3
computer system applications 1
electrical and computer engineering, conceptual interface between 1
hardware/software codesign 1
microprocessors, varieties of 3–4
mixed-signal design 1
signals 4–6
systems-on-chip 2
top-down design techniques 3
End-of-discharge voltage 149–150
End-of-life voltage 149–150
Endpoints 33–34
Energy density 149
Envelope detector 123
Equivalent series resistance 150
Even parity 25–26
F
Fanin 44
Fanout tree 44
Fast charging 150–151
Fast Fourier transform (FFT) 4–5
Federal Communications Commission (FCC) 87
Field-programmable gate array (FPGA) 53–54
advanced filter types 110–112
digital filters 112–113
op amp filters 105–106
LM555 timer 113
one shot 114
signal generators 114–120
circuit oscillation 97
passive circuit 95
resonant circuit 97
signal detectors 121–124
specifications 103–105
filter specification diagram 94
high-fidelity audio 94
loss 94
passband 93
ripple 95
stopband 93
transition band 94
voice-quality audio 94
current-to-current 99
numerator and denominator polynomials 100
resonant bandwidth frequency 103
transadmittance transfer function 100
transimpedance transfer function 100
voltage-to-voltage 99
Flow control 26–27
1/f noise 87
Fourier transform 4–5
FPGA See Field-programmable gate array (FPGA)
Fundamental frequency 66
G
Gain 66
Gain-bandwidth product 193–194
Gate voltage 70
Gaussian distribution 87
Gauss’s Law 142
Generic access profile 38
Generic attribute profile 38
Glue logic 53
Ground plane 88
Ground strap 55–56
Ground voltage 142
H
Half-wave rectification 143
Hardware abstraction layer (HAL) 162
Harmonic distortion 66
Host Controller 32
Hubs 32
Hypertext Transfer Protocol (HTTP) 39–40
I
Impulse response 12
Infinite impulse response (IIR) 112–113
Integrated circuits 2
Integrated development environment (IDE) 163
analog/digital boundary 173–174
architecture 161–162
arithmetic precision 163
bus performance 163
clap detector 176–177
computing platform 162
protoboards 166
solder bump connections 166
surface mount connections 166
command 167–168
control law 167
controller gains 168
hybrid control 169
overshoot 167
physical plants 167
PID control law 168–169
plant transfer function 169
rise time 167
settling time 167
CPU performance 162
driver design, simple character string output interface 171–172
embedded system use cases 159–160
hardware platform 162
hardware/software boundary 169–171
hyperperiod 164–165
IDE 163
interrupt latency 163
I/O devices and interfaces 163
layer diagram 164
methodologies 174–176
brushed DC motor 177
commutator 180
control law task 182–183
dead zone 181
Microchip Technology PIC16F 185
motor speed accuracy 179
response time 179
sensor-controlled brushless motor 184
sensorless brushless motor 184
servo motor 177
stepper motor 177
zero crossings 185
real-time operating system 164
RTOS 165
SDE 163
software platform 162
data rate/sample rate 160
design time 160–161
latency 160
manufacturing cost 160–161
precision and dynamic range 160
tasks 164
time quantum 165
Interference 87
Intermodulation distortion (IM) 66
Internet-enabled devices 39–40
Internet Protocol (IP) 39
Internetworking communications 39
Interrupt handler 170
Interrupt service routine (ISR) 170
Interrupt transfers 34
I2S bus 31
Isochronous transfers 34
J
Johnson-Nyquist noise 87
K
Key-value pairs (KVPs) 37
L
Laplace transform 12
Level-sensitive register 51–52
Linear conversion function 131
Linear region 69
Linear regulator 146
Linear time-invariant (LTI) 11
Linux 164
Lithium ion (LiIon) 150
LM380 83
LM386 83
LM555 timer 113
auxiliary devices and circuits 57–59
CMOS See CMOS logic circuits
bus master 54
GPIO 54
protocol 54
function 41
logic signal levels 42
power consumption 42
state transition diagram/register-transfers 41
gates, types of 42
open-drain bus circuit 49–50f
I2C 49
pulldown transistors 48–49
pullup resistors 48–49
programmable logic 53–54
protection and noise 55–56
edge-triggered register 51
level-sensitive register 51–52
transparent 51
shaft encoder 59–62
Logical link control and adaptation protocol (L2CAP) 38
Logical link control (LLC) layer 23
Logic analyzer 17
LTC 3780 147
M
Mark 26
Maximum output current 141
Media access control (MAC) layer 23
Message pipes 33
cascode amplifier 74
common drain amplifier 73
common gate amplifier 73
common source amplifier 70–73
differential amplifier 74
in CMOS logic 187
large-signal models 69–70
small-signal models 68
Microcontrollers 3
Microprocessor 3–4
Midpoint voltage 149–150
MQTT publish/subscribe model 40
N
Negative gain 66
Network layer 23
Nickel-cadmium (NiCD) 150
Nickel-metal hydride (NiMH) 150
Nodal analysis method 11
Noise immunity 46
Nonharmonic distortions See Intermodulation distortion (IM)
Nonlinear conversion laws 131
Nonlinear devices 14–16
Nonreturn to zero inverted (NRZI) encoding 32
Null modem 25
NXP S32V234 3–4
Nyquist rate 129–130
O
Odd parity 25–26
Ohm’s law 7
One-shot 58
Open-drain/open collector bus 49–50f
I2C 49
pulldown transistors 48–49
pullup resistors 48–49
Operating point 67
filters 105–106
Optical shaft encoder 59
Oscilloscopes 17
Output voltage ripple 141
P
Packet identifier (PID) 34
Pairing 38
Parallel equivalence theorem 8–9
Parity 25–26
Parks–McClellan algorithm 112
Physical layer (PHY) 23
Piconets 38
Piezoelectric effect 119
Pink noise 87
Pipes 33
Poisson distribution 87
AC-to-DC power supplies 142–147
batteries 149–151
converters 147–149
gain 66
linear regulated power supply 151–154
management 157
specifications 141–142
supply 151–154
thermal characteristics and heat dissipation 154–157
Power supply ripple 56
Power supply voltage 141
Primary winding 142–143
Priority-driven scheduling policy 165
Programmable interconnect 53
Programmable logic 53–54
Proportional-integral-derivative (PID) control law 168
Protoboards 166
Pullup resistor 29
Pullup resistors 190
LM555 timer 113
one shot 114
signal generators 114–120
Q
Quantization noise 130–131
R
Radio frequency interference (RFI) 87–88
Radius 36–37
Reactance 10–11
Ready to receive (RTR) signal 26–27
Real-time operating system (RTOS) 165
Rechargeable batteries 150
Reflective optical switch 60
Registers, logic circuits 50
edge-triggered register 51
level-sensitive register 51–52
transparent 51
Request to send (RTS) 26–27
Resistive circuits 7–9
Ripple waveform 145
circuit oscillation 97
passive circuit 95
resonant circuit 97
RMS intermodulation voltage 66–67
Root hub 32
RS-232 serial interface 24
command register bits 28
DTE and DCE 24
mark and space 26
mode instruction 28
null modem 25
parity 25–26
RTS and CTS 26–27
status bits 28–29
voltages 25
S
Safety 142
Schematic capture tool 16
Secondary winding 142–143
Self-discharge 150
Serial clock (SCL) 29
Serial data (SDA) 29–30
Serial data input (RxD) 25
74-series low-power Schottky gate 189
Shaft encoder 59–62
Short circuit 9
Shot noise 87
Signals 4–6
AC signals 4
DC signals 4
detectors 121–124
interference/crosstalk 4
noise 4
Small-scale integrated (SSI) circuits 53
Smartphone processors 3–4
Software development environment (SDE) 163
Space 26
Standard interfaces 23
RS-232 serial interface 24–29
Start-of-Frame (SOF) token 34
Static electricity 55–56
Static RAM (SRAM) 53
Stream pipes 33
Switching regulators 147
Synchronous connection-oriented (SCO) links 37
T
Thermal noise 87
Three-state logic outputs 50
Threshold voltage 69–70
Time constant 13
Time step 16
forms 41
Total harmonic distortion (THD) 66
TPA6138A2 83
TPA6166A2 127
TPA6404-Q1 83
Transconductance 68
Transistors 2
amplification 15
base-emitter path 193
BJTs 196
characteristic curve plot 194–195
collector-emitter path 193
curve tracer circuit 194–195
Ebers-Moll model 196
gain-bandwidth product 193–194
fanout problem 187–189
inverter 187
74-series low-power Schottky gate 189
terminals 187
totem pole 187
high-impedance and open outputs 189–190
open-collector and high-impedance busses 190–191
Transmission Control Protocol (TCP) 39
Trickle charging 150
U
Unity gain point 85–86
User Datagram Protocol (UDP) 39
V
Voltage controlled oscillator (VCO) 116
W
White noise 87
WM9801 83
World Wide Web 39
Z
Zigbee Device Object (ZDO) 37
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