Here's an implementation of a driver with identical functionality to the one in the A buffer-based driver section. The difference is the DMA version of the driver doesn't interrupt the application every time a byte is received. The only interrupt generated is when the entire transfer is complete. To realize this driver, we only need to add the following ISR:

void DMA1_Stream5_IRQHandler(void)
{
  portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
  SEGGER_SYSVIEW_RecordEnterISR();

  if(rxInProgress && (DMA1->HISR & DMA_HISR_TCIF5))
  {
    rxInProgress = false;
    DMA1->HIFCR |= DMA_HIFCR_CTCIF5;
    xSemaphoreGiveFromISR(rxDone, &xHigherPriorityTaskWoken);
  }
  SEGGER_SYSVIEW_RecordExitISR();
  portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
}

The significant portions of the driver are in bold. If a reception is in progress (based on the value of rxInProgress and the transmit complete flag, DMA_HISR_TCIF5, the following takes place:

• The DMA interrupt flag is cleared.
• The rxDone semaphore is given.

This is all that is required when using DMA-based transfers since the DMA controller does all of the bookkeeping associated with the buffer. At this point, the rest of the code functions in an identical way to the interrupt version (the only difference is that less CPU time is spent servicing interrupts).