Heterogeneous multi-core systems

A heterogeneous multi-core system has at least two processing cores in the same device and includes differences in either the processor architecture of the core or the way the cores access shared resources, such as system memory, peripherals, or I/O. For example, at the lower end of the spectrum, we can have multiple MCU cores on the same chip. The LPC54100 series from NXP incorporates a Cortex-M0+ and a Cortex-M4, both running at 150 Mhz, in the same package.

In this device, the MCU cores are different, but their connection to system peripherals is identical—except for instruction and data buses, which are only available on the Cortex-M4:

We can use systems like these in different ways:

  • Segmenting hard real-time operations from more general-purpose computing: The M0+ could handle low-level peripheral or hardware access/control, while the M4 handles the higher-level functionality required, such as GUIs and connectivity.
  • Power conscious design: Low-level control and interfacing is performed on the lower-power M0+, only activating the M4 when computationally expensive operations are required.

Since the LPC54100 has two MCU cores, we'll focus on bare-metal programming (no operating system) and operating systems that don't require a full-blown memory management unit (MMU), such as FreeRTOS. Running different (or multiple copies of the same) operating systems on the two cores is called asymmetric multi-processing

The name asymmetric comes from the fact that the two cores are treated differently from one another—there is asymmetry between them. This is quite a bit different from the symmetric multi-core approached used on desktop-based operating systems, where the various cores are all treated equally. Symmetric multi-core systems will be covered in the Homogeneous multi-core systems section.

For example, we could run multiple copies of FreeRTOS on each of the two cores:

In a configuration like this, the two cores run completely independently from one another. Even though FreeRTOS is being run on both cores, there is no flash program space shared between the cores—each core has a firmware image that is independent from the other. RAM behaves in the same way—the full RAM memory space is available to both cores, but by default, each core will receive its own area for stack, heap, global variables, and so on.

So, each core is running its own program—how do the two programs coordinate activities between each other? We need some way of passing information back and forth—but how?

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