Chapter 8. Parallel Physical Layer Protocol

This chapter describes the physical layer protocol for the RapidIO parallel physical layer. The RapidIO parallel physical layer differs from the serial physical layer in the following ways. The packet and control symbol information is striped across an 8- or 16-bit-wide interface, instead of a single- or four-lane interface (Figure 8.1). The clock information is sent on a separate differential pair and is not encoded in the data stream. The clock signal operates at half the frequency of the data; in other words, the data lines operate at double the rate of the clock signal. There is a separate framing signal that is used to distinguish packets from control symbols. The framing signal serves a purpose very similar to the K-codes in the serial physical layer. Control symbols each have a single function on the parallel interface, on the serial interface control symbols can have up to two separate functions. The parallel interface uses differential electrical signals based on the IEEE LVDS standard, the serial interface uses differential electrical signals based on the IEEE XAUI standard.

Figure 8.1. RapidIO interface differences

The parallel physical layer is simpler to implement than the serial physical layer. The operating frequencies are significantly lower, with specified clock frequencies ranging from 250 MHz to 1 GHz. The parallel physical layer also does not include the 8B/10B encode/decode layer or the need to generate balanced K- and D-codes. For these reasons, the parallel interface may also offer lower transaction latency than the serial interface layer, making it more attractive as a direct system interface for high-performance microprocessors. Because of its higher pin count, 40 pins for the 8-bit wide interface and 76 pins for the 16-bit wide interface, the parallel physical layer is relatively less attractive for use across backplanes, although this is not prohibited and has been demonstrated to work.

The parallel physical layer functionality includes packet transmission, flow control, error management, and other system functions. In the RapidIO documentation you will often see the parallel end point referred to as 8/16 LP-LVDS. This refers to the width of the interface (8-or 16-bit data lane widths) and the LVDS signaling used. The LP is included to indicate that the Link Protocol is also included as part of the specification. In this book we will use the more common term Parallel RapidIO.