9.5. OPERATION ORDERING AND TRANSACTION DELIVERY
This section discusses what the RapidIO to PCI bridge must do to address the requirements of the ordering rules of the PCI specifications.
9.5.1. Operation Ordering
The RapidIO transaction ordering rules were presented in Chapter 3. The rules guarantee ordered delivery of write data and that results of read operations will contain any data that was previously written to the same location. For bridge devices, the PCI 2.2 specification has the additional requirement that the results of a read command force the completion of posted writes in both directions.
In order for the RapidIO to PCI bridge to be consistent with the PCI 2.2 ordering rules it is necessary to follow the RapidIO transaction ordering rules. In addition, the RapidIO to PCI bridge is required to adhere to the following additional rule:
Read responses must push ahead all write requests and write responses.
9.5.2. Transaction Delivery Ordering
The RapidIO parallel physical layer specification and RapidIO serial physical layer specific-ation describe the mechanisms by which transaction ordering and delivery occur through the system. When considering the requirements for the RapidIO to PCI bridge it is first necessary to follow the transaction delivery ordering rules in these specifications. Further, it is necessary to add additional constraints to maintain programming model compatibility with PCI.
As described above, PCI has an additional transaction ordering requirement over RapidIO. In order to guarantee interoperability, transaction ordering, and deadlock free operation, it is recommended that devices be restricted to utilizing transaction request flow level 0. In addition, it is recommended that response transactions follow a more strict priority assignment. Table 9.3 illustrates the priority assignment requirements for transactions in the PCI to RapidIO environment.
The PCI transaction ordering model requires that a RapidIO device not issue a read request into the system unless it has sufficient resources available to receive and process a higher-priority write or response packet in order to prevent deadlock. PCI 2.2 states that read responses cannot pass write transactions. The RapidIO specification provides PCI ordering by issuing priority 0 to read requests, and priority 1 to read responses and PCI writes. Since read responses and writes are issued at the same priority, the read responses will not pass writes.
| RapidIO packet type | Priority | Comment |
|---|---|---|
| Read request | 0 | This will push write requests and responses ahead |
| Write request | 1 | Forces writes to complete in order, but allows write requests to bypass read requests |
| Read response | 1 | Will force completion of preceding write requests and allows bypass of read requests |
| Write response | 2 | Will prevent NWRITE_R request-based deadlocks |
9.5.3. PCI-X Relaxed Ordering Considerations
The PCI-X specification defines an additional ordering feature called relaxed ordering. If the PCI-X relaxed ordering attribute is set for a read transaction, the results for the read transaction are allowed to pass posted write transactions. PCI-X read transactions with this bit set allow the PCI-X to RapidIO bridge to ignore the rule described in Section 9.5.1. Table 9.4 shows the results of this additional function.
| RapidIO packet type | Priority | Comment |
|---|---|---|
| Read request | 0 | This will push write requests and responses ahead |
| Write request | 1 | Forces writes to complete in order, but allows write requests to bypass of read requests |
| Read response | 1 | When PCI-X relaxed ordering attribute is set to 0. Will force completion of preceding write requests and allows bypass of read requests |
| Read response | 2, 3 | When PCI-X relaxed ordering attribute is set to 1. The end point may promote the read response to higher priority to allow it to move ahead of posted writes |
| Write response | 2 |