A.3. COMMAND AND STATUS REGISTERS (CSRs)
All RapidIO end points or switches contain a set of command and status registers (CSRs) that allow an external device to control and determine the status of a target device's internal hardware. All registers are 32 bits wide and are organized and accessed in the same way as the CARs.
A.3.1. Mailbox CSR (Offset 0×40 Word 0)
The mailbox command and status register is accessed if an external processing element wishes to determine the status of this processing elements's mailbox hardware, if any is present; see Table A.12. It is not necessary to examine this register before sending a message since the RapidIO protocol shall accept, retry, or send an error response message, depending upon the status of the addressed mailbox. This register is read-only.
A.3.2. Write-port or Doorbell CSR (Offset 0×40 Word 1)
The write-port CSR is accessed if an external processing element wishes to determine the status of this processing element's write-port hardware; see Table A.13. It is not necessary to examine this register before sending a port-write transaction since the protocol will behave appropriately, depending upon the status of the hardware. This register is read-only.
| Bit | Field name | Description |
|---|---|---|
| 0 | Mailbox 0 available | Mailbox 0 is initialized and ready to accept messages. If not available, all incoming message transactions return error responses |
| 1 | Mailbox 0 full | Mailbox 0 is full. All incoming message transactions return retry responses |
| 2 | Mailbox 0 empty | Mailbox 0 has no outstanding messages |
| 3 | Mailbox 0 busy | Mailbox 0 is busy receiving a message operation. New message operations return retry responses |
| 4 | Mailbox 0 failed | Mailbox 0 had an internal fault or error condition and is waiting for assistance. All incoming message transactions return error responses |
| 5 | Mailbox 0 error | Mailbox 0 encountered a message operation or transaction of an unacceptable size. All incoming message transactions return error responses |
| 6–7 | Reserved | |
| 8 | Mailbox 1 available | Mailbox 1 is initialized and ready to accept messages. If not available, all incoming message transactions return error responses |
| 9 | Mailbox 1 full | Mailbox 1 is full. All incoming message transactions return retry responses |
| 10 | Mailbox 1 empty | Mailbox 1 has no outstanding messages |
| 11 | Mailbox 1 busy | Mailbox 1 is busy receiving a message operation. New message operations return retry responses |
| 12 | Mailbox 1 failed | Mailbox 1 had an internal fault or error condition and is waiting for assistance. All incoming message transactions return error responses |
| 13 | Mailbox 1 error | Mailbox 1 encountered a message operation or transaction of an unacceptable size. All incoming message transactions return error responses |
| 14–15 | Reserved | |
| 16 | Mailbox 2 available | Mailbox 2 is initialized and ready to accept messages. If not available, all incoming message transactions return error responses |
| 17 | Mailbox 2 full | Mailbox 2 is full. All incoming message transactions return retry responses |
| 18 | Mailbox 2 empty | Mailbox 2 has no outstanding messages |
| 19 | Mailbox 2 busy | Mailbox 2 is busy receiving a message operation. New message operations return retry responses |
| 20 | Mailbox 2 failed | Mailbox 2 had an internal fault or error condition and is waiting for assistance. All incoming message transactions return error responses |
| 21 | Mailbox 2 error | Mailbox 2 encountered a message operation or transaction of an unacceptable size. All incoming message transactions return error responses |
| 22–23 | Reserved | |
| 24 | Mailbox 3 available | Mailbox 3 is initialized and ready to accept messages. If not available, all incoming message transactions return error responses |
| 25 | Mailbox 3 full | Mailbox 3 is full. All incoming message transactions return retry responses |
| 26 | Mailbox 3 empty | Mailbox 3 has no outstanding messages |
| 27 | Mailbox 3 busy | Mailbox 3 is busy receiving a message operation. New message operations return retry responses |
| 28 | Mailbox 3 failed | Mailbox 3 had an internal fault or error condition and is waiting for assistance. All incoming message transactions return error responses |
| 29 | Mailbox 3 error | Mailbox 3 encountered a message operation or transaction of an unacceptable size. All incoming message transactions return error responses |
| 30–31 | Reserved |
| Bit | Field name | Description |
|---|---|---|
| 0 | Doorbell available | Doorbell hardware is initialized and ready to accept doorbell messages. If not available, all incoming doorbell transactions return error responses |
| 1 | Doorbell full | Doorbell hardware is full. All incoming doorbell transactions return retry responses |
| 2 | Doorbell empty | Doorbell hardware has no outstanding doorbell messages |
| 3 | Doorbell busy | Doorbell hardware is busy queueing a doorbell message. Incoming doorbell transactions may or may not return a retry response depending upon the implementation of the doorbell hardware in the PE |
| 4 | Doorbell failed | Doorbell hardware has had an internal fault or error condition and is waiting for assistance. All incoming doorbell transactions return error responses |
| 5 | Doorbell error | Doorbell hardware has encountered an Doorbell transaction that is found to be illegal for some reason. All incoming doorbell transactions return error responses |
| 6–23 | Reserved | |
| 24 | Write port available | Write port hardware is initialized and ready to accept a port-write transaction. If not available, all incoming port-write transactions will be discarded |
| 25 | Write port full | Write port hardware is full. All incoming port-write transactions will be discarded |
| 26 | Write port empty | Write port hardware has no outstanding port-write transactions |
| 27 | Write port busy | Write port hardware is busy queueing a port-write transaction. Incoming port-write transactions may or may not be discarded, depending upon the implementation of the write port hardware in the PE |
| 28 | Write port failed | Write port hardware has had an internal fault or error condition and is waiting for assistance. All incoming port-write transactions will be discarded |
| 29 | Write port error | Write port hardware has encountered a port-write transaction that is found to be illegal for some reason. All incoming port-write transactions will be discarded |
| 30–31 | Reserved |
The doorbell CSR is accessed if an external processing element wishes to determine the status of this processing element's doorbell hardware if the target processing element supports these operations. It is not necessary to examine this register before sending a doorbell message since the protocol shall behave appropriately, depending upon the status of the hardware.
A.3.3. Data Streaming Logical Layer Control CSR (Offset 0×48 Word 0)
The data streaming logical layer control CSR is used for general command and status information for the logical interface; see Table A.14.
| Bit | Field name | Description |
|---|---|---|
| 0–25 | Reserved | |
| 26–31 | MTU | Maximum transmission unit. Controls the data payload size for segments of an encapsulated PDU. Only single-segment PDUs and end segments are permitted to have a data payload that is less this value. The MTU can be specified in increments of 4 bytes. Support for the entire range is required
0b000000 32 byte block size 0b000001 36 byte block size 0b000010 40 byte block size ... 0b111000 256 byte block size 0b111001 Reserved ... 0b111111 Reserved All other encodings reserved |
| Bit | Field name | Description |
|---|---|---|
| 0–28 | Reserved | |
| 29–31 | Extended addressing control | Controls the number of address bits generated by the PE as a source and processed by the PE as the target of an operation
0b100 PE supports 66-bit addresses 0b010 PE supports 50-bit addresses 0b001 PE supports 34-bit addresses (default) All other encodings reserved |
A.3.4. Processing Element Logical Layer Control CSR (Offset 0×48 Word 1)
The processing element logical layer control CSR is used for general command and status information for the logical interface; see Table A.15.
A.3.5. Local Configuration Space Base Address 0 CSR (Offset 0×58 Word 0)
The local configuration space base address 0 register specifies the most significant bits of the local physical address double-word offset for the processing element's configuration register space; see Table A.16.
A.3.6. Local Configuration Space Base Address 1 CSR (Offset 0×58 Word 1)
The local configuration space base address 1 register specifies the least significant bits of the local physical address double-word offset for the processing element's configuration register space, allowing the configuration register space to be physically mapped in the processing element; see Table A.17. This register allows configuration and maintenance of a processing element through regular read and write operations rather than maintenance operations. The double-word offset is right-justified in the register.
| Bit | Field name | Description |
|---|---|---|
| 0 | Reserved | |
| 1–16 | LCSBA | Reserved for a 34-bit local physical address
Reserved for a 50-bit local physical address Bits 0–15 of a 66-bit local physical address |
| 17–31 | LCSBA | Reserved for a 34-bit local physical address
Bits 0–14 of a 50-bit local physical address Bits 16–30 of a 66-bit local physical address |
A.3.7. Base Device ID CSR (Offset 0×60 Word 0)
The base device ID CSR contains the base device ID values for the processing element; see Table A.18. A device may have multiple device ID values, but these are not defined in a standard CSR.
| Bits | Name | Reset value | Description |
|---|---|---|---|
| 0–7 | Reserved | ||
| 8–15 | Base_deviceID | See footnote[] | This is the base ID of the device in a small common transport system (end point devices only) |
| 16–31 | Large_base_deviceID | See footnote[] | This is the base ID of the device in a large common transport system (only valid for end point device and if bit 27 of the processing element features CAR is set) |
| [] | |||
| [] | |||
[] The Base_deviceID reset value is implementation dependent
[] The Large_base_deviceID reset value is implementation dependent
A.3.8. Host Base Device ID Lock CSR (Offset 0×68 Word 0)
The host base device ID lock CSR contains the base device ID value for the processing element in the system that is responsible for initializing this processing element; see Table A.19. The Host_base_deviceID field is a write-once/resetable field which provides a lock function. Once the Host_base_deviceID field is written, all subsequent writes to the field are ignored, except in the case that the value written matches the value contained in the field. In this case, the register is re-initialized to 0xFFFF. After writing the Host_base_deviceID field a processing element must then read the host base device ID lock CSR to verify that it owns the lock before attempting to initialize this processing element.
| Bits | Name | Reset value | Description |
|---|---|---|---|
| 0–15 | Reserved | ||
| 16–31 | Host_base_deviceID | 0xFFFF | This is the base device ID for the PE that is initializing this PE |
A.3.9. Component Tag CSR (Offset 0×68 Word 1)
The component tag CSR contains a component tag value for the processing element and can be assigned by software when the device is initialized; see Table A.20. It is especially useful for labeling and identifying devices that are not end points and do not have device ID registers.
| Bits | Name | Reset value | Description |
|---|---|---|---|
| 0–31 | component_tag | All 0s | This is a component tag for the PE |