8.13. SYSTEM CLOCKING CONSIDERATIONS
The RapidIO parallel physical interface can be deployed in a variety of system configurations. A fundamental aspect to the successful deployment of RapidIO is clock distribution. This section is provided to point out the issues of distributing clocks in a system.
8.13.1. Example Clock Distribution
Clock distribution in a small system is straightforward (Figure 8.19). In small systems, clocking is typically provided from a single clock source. In this case the timing budget must account for any skew and jitter component between each point. Skew and jitter are introduced by the end point clock regeneration circuitry (PLL or DLL) and by transmission line effects.
Distributing a clock from a central source may not be practical in larger or more robust systems. In these cases it may be more desirable to have multiple clock sources or to distribute the clock through the interconnect. Figure 8.20 displays the distribution of multiple clocks in a larger system.
Figure 8.19. Clock distribution in a small system
Figure 8.20. Clock distribution in a larger system
Figure 8.21. Clock distribution through the interconnect
In such a system the clock sources may be of the same relative frequency; however, they are not guaranteed to be always at exact frequency. Clock sources will drift in phase relationship with each other over time. This adds an additional component because it is possible that one device may be slightly faster than its companion device. This requires a packet elasticity mechanism.
If the clock is transported through the interconnect, as shown in Figure 8.21, then additive clock jitter must be taken into account. Assuming that each device gets a clock that was regenerated by its predecessor, and each device adds a certain jitter component to the clock, the resulting clock at the end point may be greatly unstable. This factor must be added to the timing budget.
8.13.2. Elasticity Mechanism
In systems with multiple clock sources, clocks may be of the same relative frequency, but not exact. Their phase will drift over time. An elasticity mechanism is therefore required to keep devices from missing data beats. For example, if the received clock is faster than the internal clock, then it may be necessary to delete an inbound symbol. If the received clock is slower than the internal clock, then it may be necessary to insert an inbound symbol.
The parallel RapidIO interface is source synchronous; meaning that a data element will have an associated clock strobe with which to synchronize. A clock boundary is crossed in the receive logic of the end point as the inbound data is synchronized to the internal clock. The end point should guarantee that the drift between the two clock sources does not cause a setup hold violation resulting in metastability in capturing the data.
To ensure that data is not missed, an end point implements an elasticity buffer. RapidIO uses idle control symbols as the elasticity mechanism. If a receiver needs to skip a symbol during receipt of a large packet, it can issue a throttle control symbol to cause the sender to insert a pacing idle control symbol in to the byte stream.
A data beat is clocked into the elasticity buffer with the external clock. The data beat is pulled out of the elasticity buffer using the internal clock delayed by a number of clocks behind the external clock event. This allows the data to become stable before it is synchronized to the internal clock. If the two clock events drift too close together then it is necessary for the synchronization logic to reset the tap and essentially skip a symbol. By guaranteeing a periodic idle control symbol, it is possible for the receive logic to skip an idle symbol, but not miss a critical packet data bytes.