4.2. REQUEST CLASS TRANSACTIONS
We will start by examining the Request class operation. We will look at the NREAD transaction first. An NREAD is a request by one RapidIO device to another to deliver the contents of a region of memory to the requester. The memory request can be between 1 and 256 bytes in length. There are some alignment restrictions on the data that is returned. For data over 8 bytes, it must be double-word aligned and a multiple of 8 bytes in length. For data below 8 bytes, the data must still be properly aligned in memory and the rdsize and wdptr fields are used to generate byte masks to indicate which bytes of data are valid. The minimum payload size is 8 bytes. This helps to ensure that RapidIO packets remain a multiple of 8 bytes in length. More detail on data alignment restrictions in RapidIO is found in Section 4.8.
| Operation | Transactions used | Description |
|---|---|---|
| Read | NREAD, RESPONSE | Non-coherent read from system memory |
| Write | NWRITE | Non-coherent write to system memory |
| Write-with-response | NWRITE_R, RESPONSE | Non-coherent write to system memory that waits for a response before signaling operation completion |
| Streaming-write | SWRITE | Non-coherent write optimized for large DMA transfers |
| Atomic (read–modify–write) | ATOMIC, RESPONSE | Read-modify-write operation useful for multiprocessor semaphoring |
| Maintenance | MAINTENANCE | Transactions targeting RapidIO specific registers |
4.2.1. Field Definitions for Request Class Transactions
Figure 4.1 shows the Type 2 packet with all of its fields. More detail on these fields is provided in the example below. The FTYPE field refers to the format type of the transaction. The FTYPE for Request class transactions is 2. Type 2 transactions include NREAD and several ATOMIC operations. The actual transaction type is specified in the TTYPE (transaction type) field. The combination of FTYPE and TTYPE uniquely identify the transaction format. Table 4.2 lists the defined Type 2 transactions.
RDSIZE is used in conjunction with the Address field and the W and XADD fields to specify the location, size and alignment of the data to be read. We will look at the generation of the RDSIZE, and W fields in more detail in the following example. The Address and XADD fields provide a double-word aligned address for the requested data. The address field is 29 bits long, however, because these 29 bits specify double-words rather than bytes, they support addressability to a 4 Gbyte address space. XADD (also referred to as extended address most significant bits or XADSMS) provides two more bits of address space. These two bits would be used as the most significant address bits and would increase the address space support size to 16 Gbyte per device.
Figure 4.1. RapidIO FTYPE 2 (Request class) field descriptions
| Encoding | Transaction Field |
|---|---|
| 0b0000–0011 | Reserved |
| 0b0100 | NREAD transaction |
| 0b0101–1011 | Reserved |
| 0b1100 | ATOMIC inc: post-increment the data |
| 0b1101 | ATOMIC dec: post-decrement the data |
| 0b1110 | ATOMIC set: set the data (write 0b11111 ...') |
| 0b1111 | ATOMIC clr: clear the data (write 0b00000 ...') |
This discussion has assumed the small address model. RapidIO also supports a medium and large address model. The medium address model adds 16 bits to the address field. The large model adds 32 bits to the address field. There is no information in the packet to indicate which model is employed for any given packet. The choice of address model is negotiated at system bringup between the sender and the receiver. If a target device advertises that it has a 64 bit address space then the large address model must be used for all packets destined for that device. The extra address space information is added to the packet in a contiguous big-endian fashion after the Source Transaction ID field and before the end of the packet.
In RapidIO it is assumed that senders and receivers know what they are doing and that senders are prepared to send properly configured transactions that match the characteristics of the receiver. Appendix A of this book describes RapidIO capability attribute registers which provide information to the system describing the specific capabilities of a RapidIO device.