Overview

In Chapter 6, we reviewed basic reliability and stress derating principles with emphasis on understanding datasheets and power component ratings. Our focus was on the strength aspect of the “matchmaking” process as we called it. In this chapter we turn our attention to the stresses aspect of that process. We thus hope to create viable and reliable component choices.

When designing and evaluating wide-input converters, we need to clearly identify the specific input voltage point at which a given stress reaches its maximum. Thereby we can deduce the worst-case operating stresses in the converter over its entire range of operation. That analysis will lead us to what we call the “Stress Spider” later in this chapter.

We can ask: is component selection only about matching strength (of a part) to (the applied) stress? No. That may in fact turn out to be only a pre-requisite. In Chapter 13, we will see how, for example, the input and output ripple requirements can eventually dictate the choice of the power components. In Chapter 9, we will discuss hysteretic Buck regulators for example, which depend on sufficient output voltage ripple to operate satisfactorily. In other words, various factors can affect final component choices. This chapter will help us at least shortlist eligible candidates.

The Key Stresses in Power Converters

Voltage stress is not only the most important, but also relatively the simplest to calculate and tackle. We know that if the voltage on a power semiconductor even momentarily exceeds its published Absolute Maximum (Abs Max) rating, it will very likely be destroyed almost immediately. In comparison, the current rating is usually not of such immediate concern, since it is typically (not always) thermal in nature, and is therefore comparatively slower-acting. In general, we can often inadvertently, or even sometimes with judicious deliberation, exceed the current ratings of a semiconductor somewhat, then “back off” quickly, without much impact. But note that this “forgiveness factor” should not be taken for granted. For example, if core saturation starts to occur, destruction can be almost immediate as shown in Figure 2.7.

We will now summarize our key concerns.

Waveforms and Peak Voltage Stresses for Different Topologies

We first look at voltage stresses. In Figures 7.1 and 7.2, we have started by plotting the waveforms at the switching nodes of the main conventional topologies (marked “A” or “B”). The switching node is crucial since it is a node that is a point common to both the switch and diode. Thereafter, we take the difference of the voltages on either side of the component under consideration (switch or diode), and thereby calculate the voltage across it. That difference voltage can be generally expressed by an equation of the form “V_x–V_y.” Note that looking at any specific plot in the two figures, as we move along the x-axis (time increasing), in effect, a new phase of operation starts if either of the two voltages on either side of the component (V_x or V_y, or both) change. So, for each distinct phase of operation we then need to re-evaluate the difference voltage “V_x–V_y’.” In this manner, we generate the full voltage waveform across the component over the entire switching cycle.

Figure 7.1: Voltage waveforms for the Buck, Boost, Buck-Boost, and Flyback.

Figure 7.2: Voltage waveforms for the Single-Ended Forward Converter.

We can thus clearly identify the worst-case voltage stress across the component (diode or switch). Note that we have repeated the above-mentioned process for both “continuous conduction mode” (CCM) and “discontinuous conduction mode’ (DCM) (heavy and light loads), to ensure we are really discovering the worst-case voltage stress over the entire application conditions.

Note that we have not bothered to report any capacitor voltage stresses in the figures, because that is quite self-evident in all topologies. The simple rule is that the input capacitor must be rated for at least V_INMAX, whereas the output capacitor should be rated for at least V_O. There is nothing complicated there, though we may need to apply appropriate stress derating as discussed in Chapter 6.

We have consolidated our findings for the diode and switch in an easy lookup chart: Table 7.1. Note that in this chart, there are several “new” topologies tabulated just for completeness sake. Many of these, but not all, are discussed in more detail in Chapter 9.

Table 7.1. Peak Voltage Stresses for Several Key Topologies.

In the next section, we start to look at the current stresses of the power components.

The Importance of RMS and Average Currents

Work (or energy) is done when charged particles (electrons) are transported across a potential barrier (voltage). We have the basic equation for energy as ε=V×Q, where Q is the amount of charge and V is the potential difference. Power (or dissipation) is, by definition, energy per second. So, we get ε/t≡P=V×Q/t=V×I. The last step follows because charge per second is, by definition, current. Therefore, we also get the definition of instantaneous dissipation as P(t) =V(t) ×I(t). This is a function of time, and can change from moment to moment. However, for a repetitive waveform, we can find its average value over one cycle. In steady state, that average value remains constant. By definition it is

where T=1/f_SW and f_SW is the switching frequency.

This can be further simplified based on one of the following:

so

where I_{SW_RMS} is the RMS switch (in this case MOSFET) current.

That is why it is customary to calculate and use the average current to find the dissipation for a diode and the RMS current for the dissipation in a MOSFET.

Note that there is also a V×I (crossover loss) term occurring during every switching transition that we have neglected above in computing the dissipation. In effect, what we have calculated above is just conduction loss. Note that for a switch we always need to add a switching loss term to find the total dissipation (see Chapter 8). But in a diode (or synchronous FET), we usually consider its switching loss term as negligible. Note, however, that the catch diode’s characteristics (slow reverse recovery) might cause significantly higher crossover losses in the switch if not in the diode itself. On the other hand, Schottky diodes, though near-ideal diodes in that sense, can have significant reverse leakage dissipation term that we need to add to the total dissipation in the diode, as discussed in Chapter 6.

Similarly, for a capacitor, especially an electrolytic type, we need to ensure we do not exceed its published RMS (ripple) current rating, otherwise it will have a very short life indeed as also discussed in Chapter 6. We need to know its I_RMS accurately.

At this juncture we need to gain some mastery over actually calculating RMS and average values for different topologies. We will also derive some of the key equations that appear in the Appendix of this book.

Note that several numerical examples based on this chapter, are provided in Chapter 19.

Calculation of RMS and Average Currents for Diode, FET, and Inductor

In Figure 7.3, we have provided the procedure for calculating the average/RMS currents of the switch, diode, and inductor, via “brute-force” integration techniques first. In general, we get

Figure 7.3: Integration method to derive RMS currents for MOSFET (Switch), diode, and inductor (any topology).

In Figure 7.4, we have provided an easy lookup formula that basically bypasses the above brute-force integration technique going forward. It provides the same results as above. The only restriction on using the simple method is that the waveform, however arbitrary, must be a combination of piecewise linear segments. The general rule to use is as per Figure 7.4

and

Figure 7.4: General equation to derive RMS/AVG for piecewise linear waveforms.

Applying the above techniques to the typical current waveforms of a power supply, we can also express the RMS in terms of the current ripple ratio r. This is shown in the embedded derivation in Figure 7.3. We thus get

where I_L is the average inductor current (center of ramp). Keep in mind that as shown in Chapter 1, the center of ramp (I_L above) varies for different topologies.

We thus get the equations for RMS currents (diode, switch, and inductor) as provided in the design table of the Appendix of this book.

Similarly, for average currents, the calculation is almost self-evident, but we can consult Figure 7.4 if in doubt. We get in general (calling D′ = 1–D)

This combined with the equations for I_L for different topologies, as provided above, leads to the equations for average currents (diode, switch, and inductor) provided in the design table of the Appendix.

Calculation of RMS and Average Currents for Capacitors

Now we discuss a key rule that helps us calculate capacitor currents. First, it should be intuitively obvious that if we take a waveform, and, without changing its basic shape, translate it horizontally (sideways), its RMS and average values will be unchanged. That is equivalent to changing the “0” of the x-axis (time), and we did just that in Figure 7.3 while evaluating the RMS of the diode waveform. We realized that for repetitive events, nature (expressed as observed heat and heat-related effects in our case) cannot possibly depend on where we, as mere observers, choose to start counting time, that is, where we decide to put a stake in the ground labeled “t=0.” So, horizontal translation (“x-translation”) of a waveform cannot affect any results provided so far.

But what happens if we move the waveform vertically? Certainly, the RMS and average values will be affected. But we ask: is there any simplifying relationship, or rule, that we can identify under this “y-translation,” and perhaps exploit in future? There is one such rule. In Figure 7.5, we numerically validate a fundamental property of vertically translated waveforms (using the general RMS calculation method of Figure 7.4). It is

Figure 7.5: AC RMS of a waveform is invariant under translation.

This is the “AC RMS” of a waveform: it is the RMS of only the AC part of any given waveform. The waveform is devoid of any DC value. In other words AC RMS is the RMS of the waveform with its DC value set to zero. But why are we so interested in this AC RMS term anyway? Because a capacitor does exactly that to any current waveform. If we put a current probe in series with any cap in steady state, we will see that the DC value of that waveform is zero. But there is an AC portion to it, whose RMS value is the AC RMS mentioned above. But what happens to the DC value that didn’t pass through the cap? It just passes it by. In effect, what the cap does to any current waveform is it subtracts the DC current from the applied waveform, retaining only the AC current part of it, and letting the rest (DC) pass. This is the current analog of the more familiar voltage expression we use when talking about caps in general: as it is commonly said that a series cap bypasses the applied AC voltage (i.e., lets that pass through), but blocks the DC voltage component across itself.

Alternatively stated, the average value of the current waveform through a capacitor in steady state is zero over a complete switching cycle. Otherwise it would continue to charge/discharge a little every cycle, and that would therefore not be considered a steady state. This is a completely equivalent statement to the fact that the average voltage, rather the voltseconds, impressed across an inductor over a complete cycle is zero in steady state. Now we see that the average charge (I×t or Ampere-seconds) is similarly zero for a cap over a full cycle (in steady state).

With this background in mind, in Figure 7.6 we show how we take the “associated current waveform,” remove its DC value and come up with the AC RMS (i.e., the capacitor current RMS value). Refer also to Figures 7.7–7.9 that graphically show all the current stresses in the three major topologies. We discuss that in the next section.

Figure 7.6: Calculating input and output capacitor current RMS values, based on tabulated current stresses.

Figure 7.7: Current waveforms of a buck and its related stress spider.

Figure 7.8: Current waveforms of a Boost and its related stress spider.

Figure 7.9: Current waveforms of a Buck-Boost and its related stress spider.

Some easy rules-of-thumb for selecting capacitors for a Buck converter are as follows.

We have for the input cap (of a Buck)

The function D×(1–D) has a maximum at D=0.5. Though the presence of the term in r affects this somewhat, we can simplify for low values of r

For example, a 3 A Buck will need an input capacitor sized to handle at least 1.5 A, irrespective of switching frequency, output voltage and so on.

In determining the worst-case RMS, we can ask: if D=0.5 is not included in the input range, what input voltage should we choose to check the suitability of the input cap of a Buck? The answer is: at the point closest to D=0.5. For example, if D varies from 0.2 to 0.4 over the given input range, we will pick the input voltage end at which D=0.4 (lowest input). If D varies from 0.6 to 0.8, we should pick the input voltage point at which D=0.6 (highest input). Of course, if D varies from 0.3 to 0.6, we will pick the input voltage where D=0.5 (i.e., V_IN=2×V_O).

We also realize that since RMS stresses do not depend on switching frequency, increasing the frequency will have no effect on the size of the input cap of a Buck! We can have a 2 MHz Buck as opposed to a 100 kHz Buck, but if we were using electrolytic input capacitors, both these converters will require the same input capacitor. But things can certainly change if we use ceramic input capacitors for example — these have such high ripple ratings that the acceptable input ripple, not the RMS rating, becomes the dominant criterion for selecting the input capacitor. Ripple, current or voltage, is a result of switching, and therefore does depend on frequency. So for example, in modern “all-ceramic solutions,” the input cap of a 2 MHz Buck can be roughly half the capacitance and size of a similar 1 MHz Buck. But we have to be careful too, since the use of ceramic caps on the input can cause overshoots and instability as discussed in Chapter 17. We also have to be careful in drawing too much meaning from the values of input caps shown in many semiconductor vendors’ typical schematics. The input cap of a Buck is rarely optimized as the output cap may be, and usually based on the “gut feel” of a typical engineer heading to the component cabinet. He tries it, it works, end of story.

Why is the RMS rating not significant in selecting the output cap of a Buck? Because we know that the output RMS is very small in a Buck topology. Here is the rule-of-thumb for the RMS stress on the output cap of a Buck.

So, output ripple, not RMS, becomes the dominant concern, whether or not we are using electrolytic or ceramic capacitors. Now, the actual capacitance, not just the capacitor’s physical size as related to its RMS capability, becomes important, as also the parasitics of the cap (its ESR and ESL), which as we can see greatly affect the output ripple. Full derivations for capacitor ripple and its impact are provided in Chapter 13.

The Stress Spiders

One of our key learnings from previous chapters is that for a given output voltage, the duty cycle D, in effect tells us what the input voltage is. We also learned that in all topologies, a low D corresponds to a high V_IN, and a high D to a low V_IN. In the previous sections we have derived the RMS and average values of currents for all three fundamental topologies. We now want to know how the stresses vary with D, and thereby indirectly, with respect to the input voltage. Knowledge of that variation comes in handy in deciding at what voltage within the input range “worst-case” stress occurs and what that stress is, so we can apply the derating principles learned in Chapter 6 and correctly select the power components.

When we look at the RMS/AVG equations derived so far, we see they include both r and D. That makes the total analysis a little complicated since r depends on D (input voltage) too. To arrive at the “Stress Spiders,” in the following analysis, we have often used the “small r” (or “large L,” also called the “flat-top”) approximation. But only to a certain extent — in fact only where the term in r is insignificant — we then simply ignore it. But where r happens to be the dominant term, we do not ignore it, but use the following variations (as seen from the design table provided in the Appendix of the book).

Note that now we are also interested in the “peak-to-peak” currents. The peak-to-peak current in the inductor is simply ΔI. We want to know it because, for one, core losses depend primarily on peak-to-peak (and on the switching frequency of course, but not on I_DC). Note also that in all topologies, the peak switch/diode/inductor currents are the same. That is important to know since we need to confirm that the inductor is rated for the peak current through it in terms of its rated I_SAT or B_SAT, so we can be sure to avoid core saturation, as discussed in Chapter 5. On the other hand, the RMS of the inductor current is important because it determines if the inductor is rated for that continuous RMS current value in terms of heat and its temperature rise. Note that in Figure 7.6, we have also provided the RMS of the “diode” current. The reason for that is, we may be using a synchronous topology, so we may actually have a MOSFET in place of the catch diode. To know the heating in a MOSFET we need to know its its I_RMS, not its I_AVG. Therefore, both I_AVG and I_RMS are provided for the diode (freewheeling) position.

We present some examples to show how we can approximate the dependency of the stresses with respect to D as displayed via the tables and graphs of Figures 7.7–7.9.

Example: Describe the dependency with respect to D of the peak-to-peak inductor current in a Boost topology.

The equation for peak-to-peak inductor current is

We know that the average inductor current (center of ramp) of a Boost is

Therefore, since r varies as D×(1–D)² for a Boost, we get

This is the value displayed in the table inside Figure 7.8 and plotted out in the adjoining graph.

Example: Describe the dependency with respect to D of the output cap RMS current in a Boost topology.

From Figure 7.6, we have

Therefore, assuming large inductances, the term in r is very small compared to D. Check: 0.4²/12=0.013. If minimum D is about 10%, that is, D=0.1, the term in r is 10 times smaller. We can thus approximate (for a Boost)

This is the value displayed in the table inside Figure 7.8 and plotted out in the adjoining graph.

In this manner we get the three Stress Spiders shown in Figures 7.7–7.9. The salient points of these spiders are summarized below.

Stress Reduction in AC–DC Converters

The AC–DC flyback is one of the trickiest converters to design reliably in a cost-effective manner. Let us first try to understand how to apply the RMS/AVG stress equations of previous sections to it.

To understand this better, see Figure 3.2 too. With all this in mind, we realize that all the current stress equations derived so far for the Buck-Boost can be easily applied to an AC–DC flyback.

Coming to the Forward converter, we consider its output section. Here we can assume the “Buck cell” (consisting of the two common-anode diodes, choke, and output capacitor) behaves as a DC–DC Buck converter whose input is the reflected rectified AC input (~V_AC×√2/n≡V_IN/n≡V_INR), and whose output is V_O (Volts), with load current equal to I_O (Amperes). So, all the equations for current stresses that we have derived for the DC–DC Buck converter, apply to the Buck cell of the Forward converter too. On the input side of the Forward converter, the switch current (Primary side) was sketched in Figure 3.6. Note that it is very similar to the switch waveform of a DC–DC Buck converter with duty cycle D=V_O/V_INR (or equivalently V_OR/V_IN), with a load current equal to I_OR=I_O/n. The actual switch current is actually slightly more than the equivalent DC–DC Buck converter, due to the magnetization current component in the switch waveform, but since that contribution is very small compared to the overall waveform, it can be usually ignored.

Summarizing: similar to the mapping procedure described to go from an AC–DC flyback to a Buck-Boost, all the equations derived so far for RMS/AVG stresses for a Buck can also be quickly applied to the AC–DC Forward converter. So, the switch and input capacitor of the Forward converter, in effect, think that they are part of a DC–DC Buck converter stage, whose input is the rectified AC input (~V_AC×√2≡V_IN), and whose output voltage is V_OR=V_O×n (Volts), with load current equal to I_OR=I_O/n (Amperes), where n=N_P/N_S. On the Secondary-side, the free-wheeling diode and output capacitor of the Forward converter, in effect, think that they are part of a DC–DC Buck converter stage, whose input is the reflected rectified AC input (~V_AC×√2/n≡V_IN/n≡V_INR), and whose output is V_O (Volts), with load current equal to I_O (Amperes).

One last component of the Forward converter that is not accounted for in the above mapping procedure is its output diode (the diode connected to the Secondary winding of the transformer). That diode conducts (only) during the on-time of the converter (with duty cycle D) and during that time it passes a current of average value I_O (since we know that I_O is the center of ramp of the Buck cell that follows). So, the average current through the output diode of the Forward converter, evaluated over the entire cycle, is I_O×D. Multiplying that by the forward diode drop, gives the required diode dissipation.

If we have a two-switch (“2-switch”) Forward converter, the same current passes through each of its MOSFETs. So, we have to use the same I_RMS value indicated above for each of the two MOSFETs, and then sum the two dissipations to calculate the total dual switch dissipation. So, in a 2-switch Forward-converter where each MOSFET has an R_DS of say 100 mΩ, the total switch dissipation is twice that of a single-ended Forward converter with a single MOSFET of R_DS 100 mΩ. The main advantage of using a 2-switch Forward is reflected in the fact that the voltage stress on each MOSFET is halved compared to a single-ended Forward, not the current stresses. It is also usually cheaper to find two 400 V MOSFETs with say, an R_DS of x/2 ohms each, as compared to a single 800–1000 V MOSFET with an R_DS of x ohms (same conduction loss).

See also Table 7.1 and Figure 7.2 to understand this better.

In Chapter 3, we discussed the zener clamp of a flyback as a means of reducing the leakage inductance spike of a flyback and thereby saving its switch from voltage overstress. Now, we look at another option of achieving the same basic result: the RCD clamp. Note that in a single-ended Forward converter, we may also have a leakage inductance spike due to the small leakage present between the Primary winding and the tertiary (energy-recovery) winding. However, these two windings are often wound bifilar (see Figure 9.22) and that helps the two windings couple well, reducing the leakage to near negligible. If not, some type of clamp or snubber may be required even for a Forward converter. For more tertiary winding aspects in the Forward converter, see Chapter 9.

RCD Clamps versus RCD Snubbers

Early power supplies used to invariably have an “RCD snubber” (also called a “dV/dt snubber”). RCD stands for resistor-capacitor-diode, and this little network would always be seen present across the switch. The purpose of an RCD snubber was two-fold.

Today RCD snubbers are almost obsolete for several reasons: (1) BJTs are very slow and therefore rarely used, (2) modern MOSFETs are almost immune to dV/dt failures, and (3) switching transitions today are so fast, that though there is significant V–I overlap during the transition, the transition itself lasts for only about 50–100 ns every cycle compared to a couple of μs in early days (for overlap, see Chapter 8). In effect, the RCD snubber is history. In its place, the RCD clamp has surfaced.

RCD clamps are commonly used, especially in AC–DC flybacks. One reason is they can offer higher efficiency (and lower cost) than zener clamps (as discussed in Chapter 3). But that is conditional on the RCD clamp being very carefully designed. Note that on a schematic, an RCD snubber looks almost exactly like an RCD clamp to the untrained eye — the difference is a clamp uses a much higher capacitance (typically 10–47 nF) and a much larger R, whereas a snubber has a much smaller capacitance, rarely exceeding 1–2 nF, and a much smaller R too. Therefore, functionally speaking, the difference between an RCD snubber and an RCD clamp is as follows: whereas the capacitor of an RCD snubber fully discharges every cycle, the capacitor of an RCD clamp does not discharge fully between cycles, and remains always “pre-charged” — to just a little below its “clamping voltage level.” The RCD clamp capacitor therefore comes into play (i.e., the RCD clamp diode conducts) only above a certain Drain-to-Source voltage. Below that voltage level, the RCD clamp is virtually non-existent. When the RCD clamp diode conducts, because the capacitance of the RCD clamp is so large, it acts to literally “clip” the leakage inductance voltage spike of the flyback to a safe value. As mentioned, in contrast, the capacitor of an RCD snubber discharges fully every cycle, and when the switch turns OFF, the RCD snubber capacitor is immediately ready to accept part of the freewheeling current, thus lowering the dV/dt appearing across the switch (though also transferring the switch crossover dissipation into itself). The RCD snubber was therefore often called a “switching-aid network” — it literally aids the switching action. Whereas, an RCD clamp does just that: it clamps.

In Figures 7.10 and 7.11 we cover clamps in detail, in particular the RCD clamp. We derive the equations for calculating the R and C, and estimating the clamp dissipation. We also provide a numerical example. The important things to keep in mind are:

Figure 7.10: The RCD clamp explained, and derivations for R and C.

Figure 7.11: Connecting high Line conditions with low line, and thereby calculating R, C, and dissipation for universal input flybacks.

What are the key advantages of an RCD clamp over a zener clamp? Cost is one. Efficiency is another. The reason for the efficiency improvement of an RCD is explained as follows.

For example, when using a 700 V MOSFET, a 200 V zener clamp is often used, and the V_OR is set to a maximum of 130 V. However, with a more cost-effective 600 V MOSFET, a 150 V zener is preferred, and the V_OR is set to ~100 V. We saw in Chapter 3 that, provided the voltage rating of the MOSFET is not exceeded, if V_CLAMP is made much bigger than V_OR, the dissipation in the clamp falls. This is also obvious from the equation

For a zener clamp, the clamping voltage remains almost fixed (at 200 V and 150 V, respectively) with variations in line and load. However, using an RCD clamp, as we lower the input voltage (keeping load fixed at its max value), the clamping (capacitor) voltage rises on account of the higher switch currents — to ~220 V and ~170 V, respectively, at low line. And that lowers the clamp dissipation by about 20% as compared to a zener clamp under the exact same conditions. But we note that this efficiency improvement of an RCD clamp occurs only at low line and at max load. At lighter loads for example, the clamping voltage of an RCD clamp falls much lower than that of a fixed zener clamp, on account of the lower switch currents. Therefore, the efficiency at light loads using an RCD clamp is worse than a zener clamp. Intuitively, we can view the RCD clamp as a “bad” zener clamp whose clamping (zener) voltage depends rather steeply on how much current we push into it. That helps in reducing clamp dissipation, but it can lead to excess voltages too. Therefore the RCD clamp design is rather critical. As mentioned, some nervous engineers end up combining both the RCD and zener clamps in parallel as indicated in Figure 7.10.

In designing RCD clamps there are two key optimization details to keep in mind as also discussed in Figure 7.10.