6.1.1 Inductive Links

The most versatile of the wireless on-chip communication schemes are inductively driven interfaces. Inductive links modulate the magnetic flux formed between concentrically placed inductors in different tiers within a 3-D system. Current mode signaling is used; therefore, greater communication distances can be achieved than with capacitive coupling, which is comparable to the length of a TSV (i.e., several tens of micrometers) [257]. Moreover, with inductive coupling, 3-D systems are no longer limited to face-to-face integration. Face-up, face-down, and back-to-back bonding is also supported due to low eddy current losses within the silicon substrate [258].

A transmitter and receiver circuit along with the on-chip inductors form a communication link, as depicted in Fig. 6.1. The transmitter, usually an H-bridge circuit, drives the inductor supplying a transmission current $I_T$, while the receiver senses, amplifies, and rectifies the induced voltage $V_R$ into a digital pulse. A first order model of an inductive link is depicted in Fig. 6.2, illustrating the coupled on-chip inductors $L_T$ and $L_R$. The parasitic resistance and capacitance of the on-chip spiral inductors are also depicted in this figure [259].

The inductively coupled link ideally behaves as a first order differentiator [260] $j\omega M$, where $M$ is the mutual inductance coupling between the transmitter and receiver inductors. However, due to the parasitic resistance and capacitance of the inductors, the link behaves as a band pass filter, with a peak at the resonance frequency $f_{\mathrm{SR}}$, as determined by the self-inductance and parasitic capacitance of the inductors [261],

$f_{\mathrm{SR}}=\frac{1}{2\pi \sqrt{\mathit{LC}}}.$ (6.1)

(6.1)

The operation of the inductive link can be further explained by considering the link transfer function,

$V_R=\frac{1}{\left(1-{\omega }^2{L}_R{C}_R\right)+j\omega C_R{R}_R}·j\omega M·\frac{1}{\left(1-{\omega }^2{L}_T{C}_T\right)+j\omega C_T{R}_T}·I_{T,}$ (6.2)

(6.2)

where the term 1/$(\left(1-{\omega }^2{L}_i{C}_i\right)+j\omega C_i{R}_i)$ (for $i=R,\mathit{T}$) behaves as a second order low pass filter and constrains the bandwidth due to the losses of each inductor.

Due to the short communication distance between the two inductors, pulse modulation is chosen as the communication scheme over carrier modulation. Pulse modulation is a simpler, low power communication scheme as opposed to carrier modulation, where complex analog and RF circuits are required. In the case of inductive links, the current $I_T$ of the transmitter produced by the digital pulse ${\mathit{Tx}}_{\mathrm{data}}$ is modeled as a Gaussian pulse [261], as illustrated in Fig. 6.3A,

$I_T=I_P\exp \left(-\frac{4t^2}{{\tau }^2}\right),$ (6.3)

(6.3)

where $I_P$ and $\tau$ are, respectively, the magnitude and width of the pulse. Assuming an ideal inductive link, the voltage induced on the receiver $V_R$, is the derivative of the transmitted pulse,

$V_R=-M{I}_P\frac{8t}{{\tau }^2}\exp \left(-\frac{4t^2}{{\tau }^2}\right),$ (6.4)

(6.4)

as depicted in Fig. 6.3B. This voltage is described by a Gaussian double pulse given by [262a]

$w\left(t\right)=\frac{2\sqrt{e}At}{\tau }exp\left(-\frac{2t^2}{{\tau }^2}\right),$ (6.5)

(6.5)

with an amplitude,

$A=V_P=2\sqrt{\frac{2}{e}}\frac{M{I}_P}{\tau }.$ (6.5a)

(6.5a)

The width $\tau$ of the current pulse is one of the primary parameters characterizing an inductive link. The sensitivity margin of the receiver is directly related to the width of the pulse, which is equal to $\tau /2$. Consequently, the pulse width also determines the operational bandwidth of the link. From the function describing the dependence on frequency of the induced voltage $V_R$, a peak frequency $f_p$ is observed. To avoid aliasing (or intersymbol interference), the operating frequency of the link should be greater than ${2f}_p$. Therefore,

$f_{\mathrm{SR}}>2f_p=\frac{2\sqrt{2}}{\pi \tau }\approx \frac{0.9}{\tau },$ (6.6)

(6.6)

provides a lower bound on the operating frequency of the communication scheme [261,262].

6.2.1 Intertier Coupling Efficiency

Intertier coupling efficiency is intrinsically associated with the speed, power, and area of the inductive link. The overall quality of the link therefore greatly depends upon the coupling efficiency. A first order analysis of the coupling efficiency of inductive links is presented in this subsection.

Assuming an inductor with an outer diameter $d_{\mathrm{out}}$ and a separation distance $X$, the coupling efficiency between the inductors is inversely proportional to X/$d_{\mathrm{out}}$ [261]. Since the communication distance is usually limited by technology, the outer diameter of the coil is the primary parameter for adjusting the coupling efficiency. For a specific communication distance $X,$ the coupling efficiency for decreasing the outer diameter of the coil is illustrated in Fig. 6.4.

According to Fig. 6.4 the coupling efficiency can be divided into four discrete regions, the cubic, square, linear, and saturation regions. The difference among the regions depends upon the ratio X/$d_{\mathrm{out}}$. For $X>d_{\mathrm{out}}$, $k$ is less than 0.1 and the coupling efficiency lies within the cubic region, which implies that the coupling efficiency is a cubic function of $X$. In this region, the magnetic flux between the two inductors is severely attenuated. Communication can be achieved by utilizing multiple amplification stages at the receiver tier. Roughly the minimum $k$ for supporting low power intertier communication is $0.1$ and is achieved at $d_{\mathrm{out}}=X$, where the square region is approached.

The square region lies between $d_{\mathrm{out}}=X$ to $d_{\mathrm{out}}=3X$, or $k\approx 0.65$. Synchronous receivers, in general, are used for communication when operating within the square region [261]. Synchronous circuits are preferred as these circuits exhibit lower bit error rates for low coupling as compared to asynchronous transceivers. Increasing the outer diameter allows the inductive link to enter the linear region, where asynchronous sensing schemes can be utilized. For diameter $d_{\mathrm{out}}$ greater than $5X,$ the coupling efficiency saturates. The greater intertier coupling in the saturation region is usually exploited in wireless power transfer schemes, where increased efficiency is crucial. For data transmission schemes, the suggested coupling efficiency is $k\approx 0.3$, or $d_{\mathrm{out}}=2X$. In Section 6.3, both synchronous and asynchronous inductive link receivers are considered where communication occurs within the different coupling regions.

6.2.2 Geometry and Electrical Characteristics of Inductor

The bandwidth of the link can be enhanced by proper design of the inductive link to achieve a specific coupling coefficient $k$. Optimization of the coil is achieved by altering the geometry of the inductor. The electrical characteristics of the inductive link are also determined by the geometry of the inductor.

The geometry of the on-chip spiral inductor depends upon four parameters, the outer diameter $d_{\mathrm{out}}$, the number of turns $n$, the line width $w$, and the line spacing $s$, as illustrated in Fig. 6.5. As mentioned in the previous subsection, the minimum outer diameter is limited by the communication distance to achieve a target coupling efficiency $k$. Consequently, the number of turns is chosen to manipulate the characteristics of the inductive link [259–262]. The line width and spacing are constrained by the fabrication process. Minimum line dimensions are usually employed, although a rule of thumb for the line width is 1% to 2% of $d_{\mathrm{out}}$ to reduce the parasitic resistance of the thin wires [261].

To quantify the effects of the inductor windings on the link characteristics, the complex relationship between the inductor geometry and the corresponding electrical parameters is explored here. The self-inductance of the spiral inductor structure is quadratically related to the number of turns,

$L\propto d_{\mathrm{out}}{n}^2.$ (6.7)

(6.7)

Alternatively, the parasitic capacitance is linearly proportional to the number of turns

$C\propto d_{\mathrm{out}}n.$ (6.8)

(6.8)

As a result, the self-resonance frequency is a function of $1/\sqrt{n^3}$,

$f_{\mathrm{SR}}\propto \frac{1}{2\pi d_{\mathrm{out}}\sqrt{n^3}}.$ (6.9)

(6.9)

Consequently, changing the number of turns $n$ can adjust the link performance to satisfy the specifications of the communication scheme [261]. Based on the discussion in Section 6.2.1 and this subsection, the different aspects of the design process of the inductor are combined into a design flow that produces inductive links that satisfy specific performance, area, and power constraints.

6.2.3 Design Flow for Inductive Link Coils

The design process of an inductive link scheme can require numerous iterations and be a time consuming process. A flow for designing the coils for an inductive link is illustrated in Fig. 6.6 and includes possible design iterations to satisfy power, performance, and/or area constraints.

To communicate across a distance $X$ the outer diameter $d_{\mathrm{out}}$ is chosen to satisfy a minimum coupling coefficient $k_{\min }$. The outer diameter of the inductor is increased until the coupling coefficient $k$ satisfies the minimum coupling constraint $k_{\min }$. If this constraint is satisfied, the link bandwidth is improved by adjusting the inductor geometry; specifically, the number of spiral turns and trace width.

The bandwidth of the inductive link is dependent on the communication scheme. Consequently, the bandwidth should satisfy the performance constraint of the link. Based on the coupling coefficient $k$, minimum performance requirements, and area requirements, a synchronous or asynchronous scheme is chosen for the intertier signaling.

The transceiver circuit requires a specific output data rate, which is associated with the power consumption of the link. The link bandwidth can be refined to improve the link characteristics. The power consumption is the final design criterion to be assessed. Refinements to the design of the transceiver and the outer diameter of the inductor improve the power utilization of the link.

6.3.1 Design of Synchronous Inductive Link Transceivers

For low to moderate coupling efficiencies ($0.1<k<0.6$), synchronous transceiver schemes are preferable. Synchronous receivers exhibit the advantage of noise immunity when sampling is off. As a result, noise is only induced when the received data are sampled. Consequently, the signal-to-noise ratio is improved and reliable communication is ensured.

A synchronous transceiver is schematically illustrated in Fig. 6.7 [261,262]. The transmitter is composed of an H-bridge circuit driving an inductor, augmented by a digital circuit for timing and signal shaping control. Alternatively, the receiver circuit comprises a sense amplifier for signal sensing and an SR latch to capture the received signal.

For the transmitter of the synchronous inductive link, a delay generator is used along with a clock signal to shape the pulse width, denoted by $\tau$. The pulse width is the primary factor affecting the sensitivity of the receiver. For a pulse with width $\tau$, a positive edge in the transmitted data is sensed by transistors $\mathrm{P}1$ and $\mathrm{N}2$ (see Fig. 6.7), driven, respectively, by the inverter of block $\mathrm{G}1$ and the $\mathrm{OR}$ gate of block $\mathrm{G}2$, producing a positive pulse. The amplitude of the generated pulse depends upon the size of the NMOS transistor $\mathrm{N}2$. Likewise, a negative pulse is generated for a falling edge through transistors $\mathrm{P}2$ and $\mathrm{N}1$.

Magnetic flux carries the generated pulses from the transmitter to the inductor at the receiver. The current generated at the receiver inductor is biased and amplified through the biasing resistance $R_b$, with a resistance in the $k\mathrm{\Omega }$ range. The differential output of the resistance is passed to the sense amplifier through a differential amplifier stage. Two distinct operating stages of the sense amplifier exist, the precharge and evaluation stages. The amplifier alternates between those two stages depending upon the clock signal ${\mathit{Rx}}_{\mathrm{clk}}$.

If the clock signal ${\mathit{Rx}}_{\mathrm{clk}}$ is low, the receiver circuit operates in the precharge phase, where transistors $\mathrm{P}4$ and $\mathrm{P}5$ are switched on. The SR latch stores the data. Alternatively, if ${\mathit{Rx}}_{\mathrm{clk}}$ is high, the PMOS transistors are off. Depending upon the polarity of $\mathrm{N}4$ and $\mathrm{N}5$, respectively, the voltage at either node $V_{\mathrm{LP}}$ or node $V_{\mathrm{LN}}$ is pulled to logic high, driving the other input to a logic low. Thus, the polarity of the transmitted data ${Tx}_{\mathrm{data}}$ is replicated. In the following precharge phase, the SR latch maintains the polarity of the pulse and generates the digital signal ${\mathit{Rx}}_{\mathrm{data}}$.

6.3.2 Asynchronous Data Transmission and Recovery

When operating in the linear region, asynchronous data transceivers for communication are typically used. The size of the transceiver circuit is much smaller since the timing control blocks are less complex. The effect is increased communication speed of the inductive link since the data rate of the channel is not limited by the timing circuit. Alternatively, the interface bottleneck is either the switching frequency of the transistors or the bandwidth supported by the pair of inductors (whichever is lower).

The asynchronous transceiver, shown in Fig. 6.8 [264], features an H-bridge circuit driving the inductor, similar to the equivalent synchronous circuit. Nevertheless, the timing circuit is removed, reducing overall area and yielding higher performance in terms of both communication speed and power. The timing circuit is also removed from the receiver circuit, where a hysteresis comparator is used rather than a sense amplifier.

In the receiving tier, a hysteresis comparator senses the induced data. The hysteresis comparator includes a gain stage (devices $\mathrm{P}3\mathrm{–}\mathrm{N}4$ and $\mathrm{P}6\mathrm{–}\mathrm{N}5$) and a latch circuit (see Fig. 6.8). The induced voltage $V_R$ is biased at voltage $V_b=V_{\mathrm{DD}}/2$ and is inputted differentially to the hysteresis comparator. Depending upon the polarity of the induced signal, the hysteresis comparator is driven to either an on or off state, reproducing the transmitted data signal without requiring a clock signal. The sensitivity of the receiver circuit depends upon the change in hysteresis voltage $\mathrm{\Delta }V$ of the comparator. The change in the hysteresis voltage has the opposite polarity as compared to the output signal ${\mathit{Rx}}_{\mathrm{data}}$, and is modulated by a latch circuit. For a positively induced pulse, the signal ${\mathit{Rx}}_{\mathrm{data}}$ transitions high and the latch circuit reduces the voltage threshold of the comparator by the change in the hysteresis voltage, $V_{\mathrm{TH},\mathrm{comp}}=V_{\mathrm{TH},\mathrm{inv}}-\left|\mathrm{\Delta }V\right|$, where $V_{\mathrm{TH},\mathrm{comp}}$ is the threshold voltage of the comparator and $V_{\mathrm{TH},\mathrm{inv}}=V_{\mathrm{dd}}/2$, the threshold voltage of the gain devices. The threshold voltage of the comparator facilitates the transition for the following negative pulse. The output signal is therefore held high until a negative edge is received. Similarly, an equivalent procedure is followed for a negative pulse.

As mentioned previously, an asynchronous communication scheme requires increased coupling efficiency to cope with signal reliability. Increased coupling efficiency can be achieved with larger inductors, which, however, lead to increased area for the inductive link. To mitigate the greater area, multiplexing techniques are applied, such as burst data transmission [264].

6.3.3 Burst Data Transmission

Due to the size of the inductors in the inductive link, only a few links can fit within a circuit without requiring excessive area. Increasing the number of on-chip inductors can lead to area consuming or, in many cases, overly congested circuits, since the inductors are placed within the global interconnect layers. An efficient method is needed to exploit the available bandwidth of the inductive link without further increasing area. Consequently, data multiplexing schemes, such as the approach illustrated in Fig. 6.9, are utilized to reduce the number of inductive links.

Data multiplexing provides several advantages when applied to inductive links. The number of individual inductive links decreases, reducing proportionally the area requirements. Moreover, fewer transmitter circuits dissipate less power. Depending upon the circuit, an inductive link transmitter can demand high power. An array of transmitters can consume significant power as compared to a single inductive link transmitter combined with a multiplexing scheme. Thus, less power is consumed if burst transmission is employed.

The performance of the burst transmission scheme depends upon the clock frequency of the multiplexer and demultiplexer as the clock signal is the primary bandwidth bottleneck of the circuit. To achieve a high frequency, a low power clock generator, such as a ring oscillator circuit with a counter, is often preferred to control the length of the transmission. An inductive link with burst transmission for mobile devices is described in [264], where a 400 MHz clock is assumed for the processor. As a result, a $3.2\mathrm{GHz}$ clock is generated by a local ring oscillator for multiplexing and demultiplexing eight signals. To avoid the use of a second ring oscillator on the receiving tier, the clock signal is transmitted over an inductive link.

6.4.1 Performance and Area Analysis

Recent works on TSV signaling and bandwidth optimization indicate that TSVs can achieve high data rates [265,266]. Inductive links are also capable of achieving performance levels comparable to TSVs [257]. The area requirements between the two communication schemes, nevertheless, are considerably different. TSVs occupy both silicon and wiring area, while inductive links primarily require interconnect resources. To model this situation, a performance-to-area metric is introduced to provide a fair comparison [257],

$\mathrm{eff}=\frac{\mathrm{BW}}{A},$ (6.10)

(6.10)

where $\mathrm{BW}$ is the communication bandwidth achieved by each interface and $A$ is the area.

To evaluate performance, an $RC$ model of the TSV is utilized which includes parasitic capacitive coupling with the substrate and other neighboring TSVs. Different state-of-the-art TSV pitches are considered to model the effect of coupling on TSV performance. Moreover, the redistribution layer of the TSV is also considered in the model, since this layer adds parasitic resistance and capacitance and dominates the delay of the intertier interfaces. These models are frequency dependent, since communication in a high performance system is assumed. The behavior of the model changes significantly at high frequencies.

An asynchronous inductive link transceiver is evaluated based on a state-of-the-art on-chip inductor [264]. The performance of the inductive link is evaluated with SPICE, achieving a maximum data rate of 20 Gbps. The inductors considered in this analysis are chosen to ensure that the communication distance supported by the inductive link is comparable to the length of the TSVs. Both inductive links and TSVs are placed in an $N\times M$ array to form a high performance communication interface.

The bandwidth-area efficiency for each interface is listed in Table 6.1. To determine the interconnect efficiency, a six metal layer interconnect technology is assumed. The silicon area efficiency ${\mathrm{eff}}_{s,x}$, interconnect area efficiency ${\mathrm{eff}}_{i,x}$, and total efficiency ${\mathrm{eff}}_x$ are reported for each type of interface $x$ (i.e., TSV or IL). As the TSV pitch increases, the overall efficiency drops by $80\%$. The TSV link efficiency, however, remains almost five times greater than the efficiency of an inductive link. The efficiency of the interconnect layers follows the overall efficiency, with the TSV interface presenting a significantly higher performance-to-area ratio.

Table 6.1

Performance-to-Area Efficiency for Single Interface Links

Type of Interface	${\mathbf{eff}}_{\mathit{s},\mathit{x}}(\mathbf{Mbps}\mathbf{/}\mathbf{\mu }{\mathbf{m}}^{\mathbf{2}})$	${\mathbf{eff}}_{\mathit{i},\mathit{x}}(\mathbf{Mbps}\mathbf{/}\mathbf{\mu }{\mathbf{m}}^{\mathbf{2}})$	${\mathbf{eff}}_{\mathit{x}}(\mathbf{Mbps}\mathbf{/}\mathbf{\mu }{\mathbf{m}}^{\mathbf{2}})$
TSV, 20 μm	71.2	11.8	71.2
TSV, 30 μm	21.7	3.6	21.7
TSV, 40 μm	13.8	2.3	13.8
IL, 84 μm	2.7×103	1.4	2.8

The silicon area efficiency, however, leads to a different result. Since the transceiver used by the inductive link is a small circuit, the silicon area efficiency of the inductive link is an order of magnitude greater than the efficiency of a TSV. The silicon area underneath the on-chip inductor can be used to either reduce the area overhead of the interface, or improve the performance-to-area efficiency of the inductive interface.

A multiplexing scheme can improve the performance of the inductive interface by reducing the number of on-chip inductors. The same multiplexing scheme is compared with the TSV interface. For simplicity, a 1 Gbps data rate is assumed for a communication channel. Multiplexing decreases the area of a TSV link, although multiplexing limits the data rate due to the latency imposed by the multiplexing–demultiplexing circuitry. Depending upon the diameter of the TSV and the size of the multiplexer, the area efficiency of the TSV interface departs from the aforementioned bounds. For an inductive link, however, considerable silicon area is available. This area can be reserved for multiplexing without incurring any additional area as compared to a TSV link. A tradeoff between the multiplexing ratio and the performance-to-area efficiency of the interfaces exists to determine the highest area efficiency to achieve a specific performance.

A multiplexing ratio of up to 12:1 is used by the multiplexer described in [267]. The interface efficiency is depicted in Fig. 6.10 for each scheme. For the TSV interface, two trends can be observed. For a TSV pitch smaller than $20\mathrm{\mu }\mathrm{m}$, the interface performs better without multiplexing. As the multiplexing ratio increases, the efficiency drops. However, for a TSV with a pitch greater than $30\mathrm{\mu }\mathrm{m}$, multiplexing increases system efficiency. As shown in Fig. 6.10, ${\mathrm{eff}}_{\mathrm{TSV}}$ asymptotically approaches 1.5 Mbps/μm².

This behavior occurs since the multiplexing circuits require greater area as compared to the TSVs. For a data rate of 1 Gbps and no multiplexing, the size of the interface circuit is similar to the area occupied by the TSVs. A decreasing TSV diameter leads to a quadratic increase in the area efficiency of the interface. However, if signal multiplexing is included, this behavior changes. As the multiplexing ratio increases, the efficiency of the interface saturates to a level depending upon the ratio of the pitch of the TSV to the area of the multiplexer.

The performance-to-area density for each communication scheme exhibits comparable performance, while the area significantly differs. Combined with a high density multiplexing scheme, an inductive link can exhibit comparable or even improved performance density as compared to a state-of-the-art TSV interface. Nevertheless, TSVs with a sub-20 μm pitch provide the best efficiency without signal multiplexing.

6.4.2 Crosstalk Between Inductive Links

Inductive links control magnetic flux and employ pulse modulation for near communication between different tiers within a 3-D system. Unavoidably, crosstalk noise exists between different inductive links when placed in high density arrays in high performance interconnect interfaces. A method based on time division multiplexing can be used to mitigate crosstalk between inductive links, as discussed in this subsection.

Electromagnetic coupling between inductive links occurs due to the high density required for increased performance and area efficiency. A straightforward method to reduce interlink noise is to increase the distance between neighboring inductors. For a space of $s_{\mathrm{IL}}={2d}_{\mathrm{out}}$, where $d_{\mathrm{out}}$ is the outer diameter of the inductor, the induced noise is negligible and the nearby channels do not affect the inductive link [268]. However, doubling the distance between links effectively quadruples the area required by the communication interface. An area efficient solution is, therefore, needed to improve the performance of a link while reducing crosstalk noise.

An effective way to reduce crosstalk between inductive links is to avoid simultaneous operation of adjacent links. An example of this approach is time division interleaving, as described in [268] for an 1 Tbps inductive coupling transceiver. A four-phase clock is generated by a phase interpolator, dividing the operation of a block of transceivers into several time slots. To achieve a data rate of 1 Gbps/link, a 1 GHz clock is applied and each inductive link occupies an operating time slot of 250 ps per clock cycle. 1,024 transceivers operate in parallel to achieve the 1 Tbps performance objective.

These results indicate that without the time interleaving technique, the crosstalk noise induced in adjacent links is similar to the voltage amplitude of the received signal (50 mV). The bit error rate of the channel in this case is significantly higher. However, for a two-phase interleaving scheme, the induced crosstalk noise is reduced to half (25 mV), improving the performance of the communication channel. A four-phase time division solution further improves performance, where an amplitude of 10 mV is observed for the crosstalk noise.

6.4.3 Crosstalk Noise on Adjacent On-Chip Components

A byproduct of contactless on-chip communication is interference with other components within a system due to the wireless nature of the scheme. For example, adjacent interconnect layers, analog circuits, or sensitive digital circuits may be affected by electromagnetic waves emitted from an inductive link. Alternatively, interconnects could also affect the behavior of the inductor. Interactions between the inductor and interconnect layers, as well as noise induced by the inductive link and mitigation techniques to dampen this noise, are described in this subsection. The crosstalk produced by a single inductor link is discussed in Section 6.4.3.1. The more complex case of crosstalk due to an array of inductive links is described in Section 6.4.3.3. The resulting noise due to the crosstalk on diverse power distribution topologies is evaluated in Section 6.4.3.4.

6.4.3.2 Case study

A structure consisting of an inductive link and a return path through a power delivery network has been evaluated with Ansys high frequency structural simulator (HFSS) to quantify the noise induced by an inductive link [272]. The simulated structure is illustrated in Fig. 6.11. A flip chip face-to-back integration approach is assumed. The length of the interconnect is denoted as $l_{\mathrm{PDN}}$. Distance ${\delta }_c$ denotes the spatial separation between the geometric center of the inductor $C_1$ and the geometric center of the return path through the interconnect loop. A power loop is assumed; however, the same investigation also applies to the ground loop.

The noise amplitude varies considerably with the relative location of the interconnect with respect to the center of the inductors due to the different level of magnetic flux flowing through the power loop. To model this behavior, parameter ${\delta }_c$ is used to notate the relative location between the power loop and the inductors, where ${\delta }_c$ is swept within the range $[-d_{\mathrm{out}},d_{\mathrm{out}}]$. Three positions with respect to the inductor, $C_1$, $C_2$, and $C_2^{\prime }$, are shown in Fig. 6.11, where, respectively, ${\delta }_{c,C_1}=0\mathrm{\mu }\mathrm{m}$, ${\delta }_{c,C_2}=-d_{\mathrm{out}}/2$, and ${\delta }_{c,C_2^{\prime }}=d_{\mathrm{out}}/2$. For ${\delta }_c\ge \left|d_{\mathrm{out}}\right|$, the amplitude of the noise is negligible, as shown in Fig. 6.12 by the crosshatched area. A maximum induced noise $V_{\mathrm{noise},\max }$ of 39.5 mV is observed, where the power loop is close to the windings of the inductor. Alternatively, a considerable dip in the induced noise is observed for ${\delta }_c\pm d_{\mathrm{out}}/2$, decreasing to $V_{\mathrm{noise},\min }$ of 4.6 mV.

This outcome is due to the opposite direction of the magnetic flux between the two wires of the power loop, where the power loop is placed at either $C_2$ or $C_2^{\prime }$, as shown in Fig. 6.11. This behavior indicates that there is no need to place the power loop far from the inductive link to avoid crosstalk. Instead, due to the opposite direction of coupling between the wires of the loop and the turns of the inductor, the crosstalk is low without greatly altering the power delivery network.

6.4.3.3 Crosstalk noise effects caused by inductive link arrays

Inductive links are typically placed in a high density array to increase the communication performance of the interface. To estimate the noise in this case, an array of $4\times 4$ inductive links is assumed with a spacing of 30 μm between each link to reduce crosstalk during simultaneous transmission. Each inductive link consists of transceiver and multiplexing circuits, consuming a current of I=7.1 mA, modeled as uniformly distributed current sources across each inductor. The array is supplied by a power grid that utilizes the global and intermediate metal layers of a 65 nm process node. The grid produces an $\mathit{IR}$ drop of 13.8 mV, which satisfies typical power supply noise constraints (<5% to 10% of V_dd). The power loops on the topmost global layer are illustrated in Fig. 6.13 as solid lines. The power loops span the entire array connecting to C4 bumps placed symmetrically at the periphery of the array. A spacing of $s_{C4}=150\mathrm{\mu }\mathrm{m}$ and a diameter of $d_{C4}=75\mathrm{\mu }\mathrm{m}$ are assumed for the bumps, satisfying the minimum area requirements for C4 pads [273]. The surrounding C4 bumps are assumed to supply the total current drawn by the array of inductors at a nominal $V_{\mathit{dd}}=1.1\mathrm{V}$ of 1.1 V. The bumps are connected to the power and ground lines through, respectively, the resistances $R_{\mathrm{dist},\mathit{P}}$ and $R_{\mathrm{dist},\mathit{G}}$.

The accumulated noise from a row within the inductive link array is illustrated in Fig. 6.14. The dashed line denotes the noise of an inductor at the edge of the array while the dash dotted line is the noise of an inductor at the middle of the line. The $\mathit{IR}$ drop is superimposed on both curves. The solid line is the total noise for a row within the inductor array, based on

$V_{\mathrm{noise},\mathrm{acc}}=2V_{\mathrm{noise},l}+\left(N-2\right)V_{\mathrm{noise},m},$ (6.11)

(6.11)

where $V_{\mathrm{noise},l}$ is the noise generated from the inductors placed at the edge of the loop. $V_{\mathrm{noise},m}$ is the noise produced by the remaining $N-2$ inductors coupled to the power delivery network loop, where $N=4$ for the example illustrated in Fig. 6.13. Spatial alignment of the power grid over certain positions, such as $C_2$ and $C_2^{\prime }$ depicted in Fig. 6.11, results in minimum noise caused by the inductor. The corresponding positions to produce minimum noise for the structure shown in Fig. 6.13 are also shown in Fig. 6.14 for different ${\delta }_c$.

Considering the first row of the inductive links, as shown in Fig. 6.13, the power loop is placed at position $C_2$, yielding a total noise $V_{\mathrm{noise},C_2}=35.4\mathrm{mV}$ of 35.4 mV. Moreover, the ground loop can be placed at $C_2^{\prime }$, where the accumulated noise $V_{\mathrm{noise},C_2^{\prime }}$ is 59.1 mV. The noise is slightly higher as compared to the power loop due to the increased $IR$ drop. The overall power noise is less than 8.2%. The initial placement of the power grid exhibits low $IR$ drop. The induced noise can however violate the allowed power noise constraint, reaching $V_{\mathrm{noise},\max }$ of 320 mV if the worst case position for both the power and ground loops is assumed. Proper placement of the power grid is therefore required to satisfy a low noise constraint despite interference from the inductive links.

6.4.3.4 Noise sensitivity of power network topologies

A similar analysis can be applied to determine the sensitivity to noise for other power delivery topologies, which depends upon the geometric characteristics of these networks. The sensitivity to induced noise is described in [274] for different power delivery network topologies, assuming an interdigitated power delivery network with either a paired type-I or a paired type-II topology [185,275,276]. Several power delivery network topologies are depicted in Fig. 6.15.

The center and pitch of an elemental power delivery network segment, denoted, respectively, as $c_{\mathrm{PDN}}$ and ${\mathrm{pitch}}_{\mathrm{PDN}}$, are also shown in Fig. 6.15. As the width of the loop $w_{\mathrm{loop}}$ between the power or ground wires is different for each topology, ${\mathrm{pitch}}_{\mathrm{PDN}}$ is used for all of the topologies to provide a fair comparison. The center of the power delivery network segment $c_{\mathrm{PDN}}$ describes the relative spatial position of the power delivery network with respect to an inductive link. The same inductive link structure is considered, as shown in Fig. 6.13, to evaluate the accumulated noise produced by an inductive link.

An analysis of a $4\times 4$ array of inductive links is reported in [274]. Several cases are listed in Table 6.2 for each power delivery network topology for pairs of ${(\mathrm{pitch}}_{\mathrm{PDN}},{\delta }_c)$ that satisfy a 10% noise constraint. The induced noise $V_{\mathrm{noise},\mathrm{acc}}$ described by (6–11) is also provided, which considers the induced noise on both the power and ground loops.

Table 6.2

Accumulated Noise for Different Power Delivery Network Geometries

Topology	Geometry		${\mathit{V}}_{\mathbf{noise},\mathbf{acc}}\hspace{0.5em}\left(\mathbf{mV}\right)$	$\mathit{I}\mathit{R}\text{-}\mathbf{Drop}\hspace{0.5em}\left(\mathbf{mV}\right)$		Total $\left(\mathbf{mV}\right)$	Overall Noise
	${\mathbf{pitch}}_{\mathbf{PDN}}\hspace{0.5em}\mathbf{\left(}\mathbf{\mu }\mathbf{m}\right)$	${\mathit{\delta }}_{\mathit{c}}\hspace{0.5em}\left(\mathbf{\mu }\mathbf{m}\right)$		Power Loop	Ground Loop
Interdigitated	45	−45	108	5.25	18.1	131.3	13.9% (fail)
	45	70	92	52.8	61.3	153.8	18.1% (fail)
Paired Type-I	45	−40	56.1	11.1	14.1	81.3	7.3% (pass)
	60	−40	59.2	14.2	6.1	79.5	7.2% (pass)
	105	−50	69.2	35.2	27.7	132.1	12% (fail)
	105	50	69.2	56.2	63.7	189.1	17.1% (fail)
Paired Type-II	45	−35	58.1	9.7	27.2	95	8.6% (pass)
	75	−45	65.3	16.7	26.3	108.3	9.8% (pass)
	90	0	28.5	10.8	45.5	84.8	7.7% (pass)

The interdigitated topology exhibits a higher sensitivity to induced noise as compared to the paired topologies. Even in the location where the induced noise is minimum, the added $IR$ drop for the power and ground loops increases the total noise to prohibitive levels. Overall, a minimum noise of $13.9\%$ $V_{\mathrm{dd}}$ is noted, surpassing the $10\%$ noise constraint.

Alternatively, both paired topologies include a ${(\mathrm{pitch}}_{\mathrm{PDN}},{\delta }_c)$ configuration where the overall noise is below the target limit. For the type-I topology, a noise level of $7.1\%$ is achieved, well below the target limit. The overall noise primarily occurs due to the induced noise, while the added $IR$ drop is relatively small for valid spatial positions. For the type-II topology, the ground loop $IR$ drop significantly increases the overall noise due to the greater distance from the pads. Nevertheless, positions exist where the overall noise level is tolerable, such as the positions shown in Fig. 6.13, exhibiting an overall noise of $7.7\%$ (listed in Table 6.2).