Appendix D

Proof of Condition for Via Placement of Multi-terminal Nets

In this appendix, a proof for necessary condition 1 is provided (Fig. D.1).

image
Figure D.1 Portion of an interconnect tree.

Condition 1: If rj > rj+1, only a type-1 move for vj can reduce the delay of a tree.

Proof:

Consider Fig. D.1, where the intertier via vj (the solid square) can be placed in any direction de, ds, and dn within, respectively the interval ldeimage, ldsimage, and ldnimage. For the tree shown in Fig. D.1 and removing the terms that are independent of vj, (11.1) is

Tw=viU0jspPspUij¯wspRuij(cvjlvj+Cdj)+spPspvjwsp(Ruj(cvjlvj+Cdj)+rvjlvjCdj+rvjcvjlvj22), (D.1)

image (D.1)

where

Cdj=kCdvjdk+cj+1(lde+lds+ldn). (D.2)

image (D.2)

Suppose that a type-2 move is required, shifting vj by x toward the de direction (the dashed square). Expression (11.1) becomes

Tw=[(viUijspPspUij¯wspRuij+spPspvjwspRuj)(cvjlvj+cjx+Cdj)+spPspvjwsp×[(rjrj+1)xCdj+rj+1lde(Cdj12cj+1lde)+rjx(cvjlvj+Cdj)+12(rvjcvjlvj2+rjcjx2)]]. (D.3)

image (D.3)

For a type-2 move to reduce the weighted delay of the tree, shifting vj should decrease Tw, or, equivalently, ΔT=TwTw<0image. Subtracting (D.1) from (D.3) yields

ΔT={spPspvjwsp[rjx(cvjlvj+Cdj)+Rujcjx+rj+1lde(Cdjcj+1lde2)+(rjrj+1)xCdj+rjcjxj22]+viUijspPspUij¯wspRuijcjx}. (D.4)

image (D.4)

Since rj > rj+1 and Cdj>(cj+1lde/2)image from (D.2), (D.3) is always positive and a type-2 move cannot reduce the delay of a tree.

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