Glossary of Terms

2-D Two-dimensional

3-D Three-dimensional

ADVP Alternating direction TSV planning algorithm

ALD Atomic layer deposition

a-Si Amorphous-Si

ASIC Application-specific integrated circuit

BCB Benzocyclobutene

BEOL Back-end-of-line

BOX Buried oxide

C4 Controlled collapse chip connect

CAD Computer-aided design

CBA Combined bucket and 2-D array

CMOS Complementary metal oxide semiconductor

CMP Chemical mechanical planarization

CPD Coarse pin distribution

CTE Coefficient of thermal expansion

CVD Chemical vapor deposition

D2D Die-to-die

DC Direct current

DME Deffered-merge embedding

DPD Detailed pin distribution

DRIE Deep reactive ion etching

DVFS Dynamic votlage and frequency scaling

EDP Energy delay product

eDRAM Embedded dynamic random access memory

ELO Epitaxial lateral overgrowth

ESD Electrostatic discharge

FDSOI Fully depleted silicon-on-insulator

FEM Finite element method

FEOL Front-end-of-line

FPGA Field programmable gate array

GSG Ground-signal-ground

GSGSG Ground-signal-ground-signal-ground

HPWL Half perimeter wirelength

ICP Inductively plasma enhanced

ILD Interlayer dielectric

IoT Internet of things

IP Intellectual property

IPC Instructions per cycle

ITRS International technology roadmap for semiconductors

ITVPA Interconnect tree via placement algorithm

JMOS Junction MOS

KGD Known good die

KOZ Keep out zone

LB Logic block

LDPC Low density parity check

LPCVD Low pressure chemical vapor deposition

LTO Low temperature oxide

MEMS Micro-electro-mechanical systems

MIM Metal insulator metal

MITLL MIT Lincoln Laboratory

MMM Method of means and medians

MOCVD Metalorganic chemical vapor deposition

MOM Method of moments

MOSFET Metal oxide semiconductor field effect transistor

MST Minimum spanning tree

NAPC Normalized average power consumption

NCP Non-conductive particle paste

NLP Nonlinear programming

NoC Network-on-chip

OPRSOC Open RISC platform system-on-chip

OSAT Outsourced semiconductor assembly and test

PCB Printed circuit board

PE Processing element

PEALD Plasma enhanced atomic layer deposition

PECVD Plasma enhanced chemical vapor deposition

PI Performance improvement

PL Performance loss

PLL Phase locked loop

PPA Performance, power, area

PRNG Pseudorandom number generator

PSG Phosphosilicate glass

PTM Predictive technology model

PVD Physical vapor deposition

PWB Printed wire board

RDL Redistribution layer

RF Radio frequency

RIE Reactive ion etching

RISC Reduced instruction set computer

RMST Rectilinear minimum spanning tree

SA Simulated annealing

SB Switch box

SCSVPA Single critical sink interconnect tree via placement algorithm

SEG Selective epitaxial growth

SiP System-in-package

SoC System-on-chip

SOI Silicon-on-insulator

SoP System-on-package

SOS Silicon-on-sapphire

SPICE Simulation program with integrated circuit emphasis

SST Steady-state temperature

SW/HW Software / Hardware

TAB Tape adhesive bonding

TCG Transition closure graph

TEOS Tetraethylorthosilicate

TFC TSV fault-tolerant component

TFT Thin film transistors

TGV Through glass via

TPR Three-dimensional place and route

TSV Through silicon via

TTSV Thermal through silicon via

TTVPA Two terminal via placement algorithm

VPR Versatile place and route

VRM Voltage regulation module

WDM Wavelength division multiplexing

WID Within die