Index
‘−’ don’t care value of std_ulogic
− sign operator
− subtract operator
& concatenation operator
* multiplication operator
** exponentiation operator
/ division operator
/= not-equal operator
:= variable assignment
| bar symbol
aggregates
case statements
selected signal assignment
+ add operator
+ sign operator
< less-than operator
<= less-than-or-equal operator
<= signal assignment
<> box symbol
= equal operator
=> finger
array aggregates
case statement
generic map
port map
record aggregates
> greater-than operator
>= greater-than-or-equal operator
‘0’ low value of std_ulogic
0.0 (zero) floating-point value
‘1’ high value of std_ulogic
1076, IEEE standard. See Standards
1164, IEEE standard. See Standards
2's-complement notation
32-bit integer limit
754, IEEE standard. See Standards
Absolute value (abs) operator
Access types
line type in textio
Accidental feedback
Accumulator, case study
Active signal
Add (+) operator
Add_carry procedure
Adding operators
Address generator, case study
After clause
Aggregates
array targets
array types
as record targets
constant values
look-up table
named association
of aggregates
others clause
positional association
record types
All selection
component binding
use clause
Allocation and Scheduling
Analog and Mixed-Signal Working Group
Analysis. See Compilation
Analysis and Standardization Group, VHDL
And operator
Anonymous array types
Arbitrary-precision
fixed-point types
floating-point types
numeric types
Architecture
declaration part
generic
multiple
naming conventions
statement part
test bench
Area-constrained design
Arithmetic operators
fixed-point types
floating-point types
numeric types
Array of records
Array tristate drivers
Array types
aggregates
anonymous
ascending range
assignment
attributes
bit-string literals
comparison
comparison operators
constrained
descending range
dynamic indexing
for loop bounds
generic constraints
in test benches
operators
shift operators
slice
static indexing
string literals
tristates
unconstrained
unconstrained parameters
unconstrained return
Ascending range
array types
for generate
for loops
integer types
Assert statement
test bench
Assignment. See Variables: assignment, See Signal Assignment
of array types
source
target
Association
generic map
port map, named
port map, positional
Asynchronous feedback
Asynchronous read, synchronous write RAM
Asynchronous reset
generation, test bench
simulation model
synthesis model
Attribute
event
high
last_value
left
leftof
length
low
pos
pred
range
range, test bench
reverse_range
right
rightof
succ
val
Attributes
array types
enumeration types
FSM encoding
integer types
ram type
B prefix, bit-string literal
Bar (|) symbol
aggregates
case statements
selected signal assignment
Barrel shifter
Basetype
Basic boolean operators
fixed-point types
floating-point types
numeric types
std_logic types
Basic register template
BCD decoder example
Behaviour, architecture name
Bidirectional ports
Binary bit-string literal
Bit type
Bit_vector type
Bit-preserving type conversion
Bit-string literals
in test bench
synthesis types
Boolean operators
basic
fixed-point types
floating-point types
numeric types
reducing
selecting
std_logic types
Boolean type
Box symbol <>
Branches
case statement
conditional signal assignment
if statement
selected signal assignment
Buffer mode ports
Built-in operators
Built-in type conversions
Buses, tristate
Call, function
Case statement
choices
condition
empty branch
FSM decoder
ROM
Case study
Character types
bit
character
std_ulogic
Choices
array aggregates
case statement
case statements
conditional signal assignment
selected signal assignment
Circuit contents
Circuit interface
Circuit under test
Classes, subprogram parameters
Classification function (classfp), floating-point types
Classification, operator
Clocks
clock gating
data gating
falling edge
generation, test bench
rising edge
Coefficients, filter, case study
Colon notation, floating-point types
Combinational logic
template
Combinational process
feedback
Comparing with zero
Comparison
array types
enumeration types
integer types
record types
Comparison operators
array types
discrete types
fixed-point types
floating-point types
numeric types
std_logic types
Comparison type, boolean
Compatibility synthesis packages
Compilation
incremental
Complex package example
Component
direct binding
Components
binding
declaration
default binding
entity binding
generic
generic map
indirect binding
name
packages
port map
relation to entity
Concatenation (&) operator
Concurrency, VHDL model
Concurrent domain
Concurrent statements
component
conditional signal assignment
execution order
for generate statement
function call
if generate statement
procedure call
selected signal assignment
signal assignment
simple signal assignment
Conditional signal assignment
Conditions
case statement
conditional signal assignment
if statement
redundant
selected signal assignment
Configuration declaration
Configuration specification
Constant parameter class
Constants
integer literals
lookup table
look-up table
shift distance
synthesis types
test set
Constrained array type
Context clause
synthesis types
Context declaration
std_context
Controller
case study
design
FSM
CUT. See Circuit under test
Data-flow diagram
Declaration
constant
Declaration part
architecture
process
subprograms
Declarations
array types
component
component in package
component in sub-block
configuration specification
constant
enumeration type
function
integer types
operator
port
procedure
record types
signal
subprograms
variable
Default assignments
Default binding
Default initial value
Delay, signal assignment
Delta cycle
process execution
test bench
Denormalised floating-point
Department of Defense
Dependencies, source file
Descending range
array types
fixed-point types
floating-point types
for generate
for loops
numeric types
Design iteration
Design reuse
Design stages, RTL
Design units
Digital Signal Processing (DSP)
Direct binding of components
Directory, library
Divide and conquer
Division (/) operator
Don’t cares
test bench
value ‘-’
Don’t know value ‘X’
Dot notation
fixed-point types
record types
Dot-product calculator example
Driver of a signal
DSP. See Digital Signal Processing
Dynamic indexing
arrays
RAMs
ROMs
EDA Industry Working Groups
Elaboration
clock signals
indirect binding
processes
registers
signals
variables
Elements of a record
Else
generate statement
if statement
Elsif
generate statement
if statement
Empty branch
Endfile function
Entity
generic
name
ports
relation to component
test bench
Entity binding
Enumeration type
bit
Enumeration types
attributes
boolean
comparison operators
FSM state
operators
position number
std_ulogic
Equal = operator
Error handling, textio
Error modes, floating-point types
disabling
Event
generation
process execution
simulation model
Event attribute, registered process
Examples
BCD decoder
complex package
dot-product calculator
low-pass filter
match bits
parity generator
pseudo-random binary sequence generator
systolic processor
test bench for systolic processor
Execution order of concurrent statements
Exit statement
Exponent, floating-point
Exponentiation (**) operator
Expression
Falling edge clock
Feedback, asynchronous
File system, library storage
File types
File_close procedure
File_open procedure
Filter coefficients, case study
Finger (=>)
array aggregates
case statement
generic map
port map
record aggregates
Finite function
Finite State Machine (FSM)
case study
illegal states
inference
reset
state encoding
Finite-impulse response (FIR) filter
Fixed_float_types package
Fixed_pkg package
Fixed-point typeot notation
Fixed-point types
arithmetic operators
boolean operators
case study
comparison operators
constant values
guard bits
minimum area
noise calculation in case study
notation
overflow mode
range
resize functions
result range
rules
saturation value
shift operators
type conversions
underflow mode
Fixed-point versus floating-point
Flip-flops. See Registers
Float type. See Floating-point types
type conversions
Float_pkg package
Floating-point types
arithmetic operators
boolean operators
case study
classification functions
colon notation
comparison operators
constant values
denormalised
disable error checking
error modes
interpretation
minimum area
normalised
not-a-number
notation
ordering
overflow mode
range
resize functions
result range
rounding mode
rules
type conversions
underflow mode
Floating-point unit (FPU)
Floating-point versus fixed-point
For generate statement
For loop
array indexing
attribute bounds
exit statement
loop constant
next statement
range
synthesis interpretation
test bench
FPU. See Floating-point unit
Fraction part, fixed-point
FSM. See Finite State Machine
Function
body
call
declaration
local variables
multiple returns
overloading
parameters
Functions
return statement
type conversions
unconstrained parameters
Generate constant
Generate statements
else part
elsif part
for generate statement
if generate statement
Generating test stimuli
Generation of an event
Generics
architecture
case study
component instance
entity
generic clause
generic map
parameter types
RAM
Glitch free FSM
Glitches
asynchronous reset
clock gating
data gating
Global reset
Greater-than > operator
Greater-than-or-equal >= operator
Guard bits
‘H’ weak high value of std_ulogic
Handshaking, case study
Hexadecimal
bit-string literal
printing values
read from file
Hierarchy
High attribute
array types
discrete types
for loop bounds
High-impedence value ‘Z’
Hread procedure
Ieee library
IEEE standards. See Standards
IEEE synthesis types. See Synthesis types
Ieee_proposed library
If generate statement
If statement
asynchronous reset
data gating
latch inference
priority ordering
register template
synchronous reset
synthesis
tristate driver
Illegal states, FSM
Implicit library and use clauses
In mode
function parameters
parameter normalisation
ports
procedure parameters
Incremental compilation
Independent, technology
Indexing
dynamic
RAMs
ROMs
static
Indirect binding
default binding
Inequality /= operator
Inference
FSM
latch
RAM
ROM
tristate driver
Initial values
clock signal
FSM state
registers
signals
variables
variables in functions
Inout mode
parameter normalisation
ports
procedure parameters
tristate buses
Integer part, fixed-point
Integer subtypes
Integer type
Integer types
arithmetic operators
attributes
comparison operators
declaration
limitations
mixing with synthesis types
operators
Interface, entity
Intermediate form
Internal signals
Interpreting floating-point values
Is_negative function
Isnan function
Iterative design
‘L’ weak low value of std_ulogic
Labels
components
generate statement
Language Reference Manual (LRM)
Last_value attribute
Latch inference
Left attribute
array types
discrete types
Leftof attribute
Length attribute
and resize function
array types
Less-than < operator
Less-than-or-equal <= operator
LFSR. See Linear feedback shift register
Libraries
directory
mapping
names
reuse
Library
ieee
ieee_proposed
std
work
Library clause
for package
implicit
synthesis types
Limit, resolution
Limitations of standard types
Limitations of type bit
Line type
Linear feedback shift register (LFSR)
Linkage mode
Literal values
bit-string literal
enumeration types
std_ulogic
string literal
synthesis types
Local subprogram declarations
Logb function
Logical operators
fixed-point types
floating-point types
numeric types
std_logic types
Lookup table
Loop constant
for generate
Loop termination
exit statement
next statement
Loops. See For loop, While loop, Simple loop
Low attribute
array types
discrete types
for loop bounds
Lower saturation value
Low-pass filter, case study
LRM. See Language Reference Manual
Magnitude notation
Mantissa
denormalised
normalised
Mapping, library
Masking operations
Match_bits example
Math_real package
Maximum function
Mealy machine, FSM
Memories. See Registers, Register Banks, RAMs or ROMs
Metalogical values
Minimum area
fixed-point types
floating-point types
Minimum function
Minus sign (-) operator
Miscellaneous operators
Missing else part
Mixing synthesis types with integer
Modes
and classes
function parameters
inout tristate buses
ports
procedure parameters
Modulus (mod) operator
Moore machine, FSM
Msb
fixed-point types
floating-point types
numeric types
Multi-branch conditional assignment
Multiple architectures
Multiple drivers
Multiplexer
case statement
conditional signal assignment
if statement
multi-way
priority tree
selected signal assignment
tristate
Multiplication (*) operator
Multiplier circuit
Multiply-accumulator, case study
Multiplying operators
Multivalue Logic Packages Working Group
Multi-valued logic types
std_ulogic
Multi-way multiplexer
Named association
array aggregates
generic map
generic map
port map
record aggregates
Names
architecture
component
entity
library
test bench
Naming conventions
architectures
NaN. See Not-a-number
Nand operator
Nanfp function
Neg_inffp function
Neg_zerofp function
Netlist, architecture name
Next statement
Nextafter function
Noise calculations, fixed-point
Nor operator
Normalisation
in parameters
inout parameters
out parameters
Normalised floating-point
Not operator
Not-a-number (NaN)
quiet
signalling
Notation
2's-complement
fixed-point
floating-point
magnitude
Not-equal /= operator
Null statement
Numeric types
arithmetic operators
boolean operators
comparison operators
constant values
range
resize
result range
rules
shift operators
type conversions
Numeric_std package
Numeric_std_additions package
O prefix, bit-string literal
Octal
bit-string literal
printing of values
read from file
On clause
Open port
Operator
Operator overloading
resolution
Operators
adding
arithmetic
array types
boolean, basic
boolean, reducing
boolean, selecting
built-in
classification
comparing with zero
comparison
concatenation
enumeration types
integer result sizes
integer types
logical
miscellaneous
multiplying
overloading
precedence rules
record types
relational
shifting
sign
standard set
type bit
Or operator
Order of execution
Ordered values, floating-point
Oread procedure
Organising source files
Origins of VHDL
Others clause
aggregates
case statement
constant values
ROM decoder
selected signal assignment
Out mode
parameter normalisation
ports
procedure parameters
reading port
Overflow mode
fixed-point types
floating-point types
numeric types
Overloading
functions
operators
Package
fixed_float_types
fixed_generic_pkg
fixed_pkg
float_generic_pkg
float_pkg
math_real
numeric_std
numeric_std_additions
standard
std_logic_1164
std_logic_1164_additions
std_logic_arith
textio
Package body
Packages
of components
of subprograms
Parameterised components
filter, case study
Parameters
function
procedures
unconstrained arrays
Parity generator example
Physical types
Pitfall
absolute value is negative
accidental feedback
array aggregates
avoid bureacracy
case study
component binding within generate
conversions from real
else generate
errors only found in synthesis
fixed-point bounds
fixed-point string literals
floating-point bounds
function overloading
gated register needs separate if
glitches and clock gating
glitches on asynchronous reset
incomplete sensitivity list
incrementing using attributes
initial values
loop counter does not need a declaration
multi-valued logic types
process elaboration
RAM reset
range of string literal
redundant conditions
register initial values
return constrained by value
std_ulogic type
string value “1” is negative
subprograms as hierarchy
truncation of type signed
unconstrained function parameters
unconstrained procedure parameters
unconstrained return type
wait statement in procedure
Plus sign (+) operator
Port map
configuration specification
direct binding
indirect binding
named association
open
positional association
Portability
Ports
bindings
declaration
modes
none
tristate buses
Pos attribute
Pos_inffp function
Position number
Positional association
array aggregates
generic map
port map
record aggregates
Positioning of wait statements
Power up and illegal states
PRBS. See Pseudo-random binary sequence generator
Precedence, operator
Pred attribute
Primary unit
Printing response values
Priority multiplexer
Procedure
body
call
concurrent call
declaration
parameter modes and classes
parameters
signal parameters
unconstrained parameters
Process
combinational
declaration part
event sensitivity
execution
feedback
FSM
registered
sensitivity list
simulation model
statement part
test generation
triggering
tristate driver
wait statements
Pseudo-random binary sequence (PRBS) generator
Qnanfp function
RAMs
asynchronous read, synchronous write,293
synchronous read before write
synchronous write before read
synchronous write or read
Range
aggregate
case statement
fixed-point result
fixed-point types
floating-point result
floating-point types
for generate statement
for loop
integer
numeric type result
numeric types
Range attribute
array aggregate
array types
for loop bounds
test bench
Read procedure
Reading an out mode port
Reading data files, test bench
Readline procedure
Real type
Record aggregates
named association
positional association
Record types
aggregates
element access
operators
Reducing boolean operators
fixed-point types
floating-point types
numeric types
std_logic types
Redundant conditions
Redundant registers
Register allocation
Register banks
case study
Register Transfer Level (RTL)
Registered process
synthesis model
Registers
asynchronous reset
clock gating
data gating
event attribute
redundant
synchronous reset
templates
variables
Relational operators
Remainder (rem) operator
Replicated structures
Reset
asynchronous
design
FSM
generation, test bench
RAM
synchronous
Reset to a value
asynchronous reset
synchronous reset
Resize functions
fixed-point types
floating-point types
numeric types
Resolution function
Resolution limit
Resolution, fixed-point
Resolution, operator
Resource Allocation
Response values, printing
Response, verifying, test bench
Return statement
multiple
unconstrained
Reuse policy
Reverse_range attribute
array types
for loop bounds
Right attribute
array types
discrete types
Rightof attribute
Rising edge clock
Rising_edge function
ROM Inference
Rotate-left (rol) operator
Rotate-right (ror) operator
Rounding mode
fixed-point types
floating-point types
RTL design stages
Rule
descending range
lsb is bit 0
msb on the left
natural exponent part
negative fraction part
negative mantissa part
sign is left bit
Rules
fixed-point types
floating-point types
numeric types
Saturation mode, fixed-point types
Saturation value
Scalb function
Scheduling
Secondary unit
Selected signal assignment
choices
others clause
Selecting boolean operators
fixed-point types
floating-point types
numeric types
std_logic types
Selection, record types
Self-stopping test bench
Sensitive processes
Sensitivity list
asynchronous reset register
combinational process
process
wait statement
Sensitivity list register template
Sequential domain
Sequential statements
assert statement
case statement
exit statement
for loop
function call
if statement
next statement
null statement
procedure call
return statement
signal assignment
simple loop
variable assignment
wait statement
while loop
while loop, test bench
Severity_level type
Sfixed type. See Fixed-point types
Shift operators
constant distance
fixed-point types
numeric types
std_logic types
variable distance
Shift register, case study
Shifting operators
Shift-left-arithmetic (sla) operator
Shift-left-logical (sll) operator
Shift-right-arithmetic (sra) operator
Shift-right-logical (srl) operator
Sign operators
− operator
+ operator
Signal assignment
after clause
combinational logic template
conditional
selected
sequential
simple
Signal parameter class
Signals
active
declaration
default value
driver
initial values
latch inference
multiple drivers
Signed type. See Numeric types
Sign-extension, integer types
Simple loop
Simple signal assignment
Simulation model
asynchronous reset
events
process
register initial values
registered process
signal initial values
test benches
transactions
variable initial values
variable initial values in functions
Simulation time
Simulator and Synthesiser, separate
Slice
Source files, organising
Source of assignment
Standard libraries
Standard operators
Standard package
Standardisation of VHDL
Standards
IEEE 1076
IEEE 1076.1
IEEE 1076.3
IEEE 1076.4
IEEE 1076.6
IEEE 1164, 4
IEEE 754
unification
State encoding, FSM
State machine. See Finite State Machine
Statement part
architecture
process
subprograms
Static indexing
Std library
Std_context context declaration
Std_logic type
boolean operators
comparison operators
shift operators
tristate buses
Std_logic_1164, package
Std_logic_1164_additions, package
Std_logic_arith package
Std_logic_vector only interface
Std_logic_vector type
type conversions
Std_match function, test benches
Std_ulogic type
Std_ulogic_vector type
Stimulus generation
Stopping simulation
String literals
in test bench
synthesis types
Strong typing
Subprograms
body
functions
operators
parameter modes and classes
procedures
Subtract (−) operator
Subtypes of integer
Succ attribute
Sum of products form
Synchronous design methodology
Synchronous read before write RAM
Synchronous reset
Synchronous write before read RAM
Synchronous write or read RAM
Synopsys Incorporated
Synthesis
arithmetic operators
asynchronous reset
boolean operators
comparison operators
exit statement
for loop
if statement
integer types
port modes
registered process
selected signal assignment
shift operators
synchronous reset
synthesisable types
templates
Synthesis Interoperability Working Group
Synthesis Package Working Group
Synthesis standard, VHDL
Synthesis type system
Synthesis types
case study
compatibility packages
constant values
fixed-point types
floating-point types
library and use clauses
numeric types
std_logic types
tristates
vendor provided
System, architecture name
System-level model
Systolic processor example
Table lookup
case study
test set
Target aggregates
array types
record types
Target of assignment
Technology independence
Templates
asynchronous reset register
combinational logic
combinational process
FSM
overview
RAM
registered process
ROM
synchronous reset register
tristate drivers
Test bench example
Test benches
array types
case study
clock generation
don’t cares
reading data files
reset generation
self stopping
std_match function
stimuli generation
verifying response
writing I/O procedures
Test Driven Design
Test synthesis and clock gating
Textio
error handling
file handling
line handling
package
reading delay times
reading standard types
reading string types
reading synthesis types
reading user-defined types
Third party components
Time
delays
delays, test bench
delta
Time type
Time, simulation
To_bstring or to_binary_string function. See To_string function
To_float function
To_float128 function
To_float32 function
To_float64 function
To_hstring or to_hex_string function
To_integer function
To_ostring or to_octal_string function
To_real function
To_sfixed function
To_signed function
To_slv function
To_string function
To_ufixed function
To_unsigned function
Top-down design process
Top-level interface
Transaction, simulation model
Transfer functions
Trigger, process
Tristates
buses
driver inference
multiplexer
Truncate mode, fixed-point types
Two-way multiplexer
Type
bit
bit_vector
boolean
character
file
float
integer
line
natural
positive
real
severity_level
sfixed
signed
std_logic
std_logic_vector
std_ulogic
std_ulogic_vector
string
text
time
ufixed
unsigned
Type conversions
built-in
fixed-point types
floating-point types
numeric types
user-provided
Type system
Types
access types
anonymous arrays
arbitrary precision
array types
attributes
built-in operators
character types
constrained arrays
enumeration types
file types
fixed-point types
floating-point types
integer subtypes
integer types
multi-valued logic
numeric types
of generics
physical types
record types
synthesis types
synthesisable
unconstrained arrays
universal integer
user-defined integers
‘U’ undefined value of std_ulogic
Ufixed type. See Fixed-point types
range
Unconnected port
Unconstrained arrays
function parameters
function return
procedure parameters
Underflow mode
fixed-point types
floating-point types
Unification of VHDL standards
Universal integer
Unordered function
Unsigned type. See Numeric types
Until clause
Upper saturation value
Use clause
for package
implicit
synthesis types
User-defined
integer types
operators
type conversions
Val attribute
Value-preserving type conversion
Values, printing
Variable parameter class
Variable shift distance
Variables
assignment
declaration
in a function
initial values
latch inference
purpose
registered
VASG. See VHDL: Analysis and Standardization Group
Vendor-provided synthesis packages
Verifying response, test bench
Very-High Speed Integrated Circuits programme
VHDL
1987
1993
2000
2002
2008
Analog and Mixed-Signal Working Group
Analysis and Standardization Group
as a waveform language
Initiative Towards ASIC Libraries Working Group
Multivalue Logic Packages Working Group
origins
standard 1076
standardisation process
Synthesis Interoperability Working Group
Synthesis Package Working Group
synthesis standard
unification of standards
VHSIC. See Very-High Speed Integrated Circuits Program
VHSIC Hardware Description Language. See VHDL
VITAL. See VHDL: Initiative Towards ASIC Libraries
‘W’ weak don’t know value of std_ulogic
Wait statement
combinational process
on clause
positioning
registered process
sensitivity list
time delay
unconditional
until clause
Waveform capture
When clause
case statement
selected signal assignment
While loop
test bench
Work library
Wrap mode, fixed-point types
‘X’ don’t know value of std_ulogic
X prefix, bit-string literal
Xnor operator
Xor operator
‘Z’ high-impedence value of std_ulogic
Zero extension, integer types
Zero, floating-point value
Zerofp function