Figure 1.1 The VHDL-based hardware design cycle

Figure 2.1 Cross-product calculator – data-flow diagram

Figure 2.2 Adder – balanced tree

Figure 2.3 Adder – skewed tree

Figure 2.4 Cross-product calculator – datapath

Figure 2.5 Cross-product calculator – controller

Figure 3.1 Adder tree circuit

Figure 3.2 Hardware mapping of conditional signal assignment

Figure 3.3 Multi-way conditional signal assignment

Figure 3.4 Redundant branch in conditional signal assignment

Figure 3.5 Parity generator interface

Figure 4.1 Using boolean as a comparison result

Figure 4.2 Intermediate value precisions

Figure 4.3 Multi-way selected signal assignment

Figure 5.1 Basic and operator

Figure 5.2 Selecting and operator

Figure 5.3 Reducing and operator

Figure 5.4 Four-bit equality

Figure 5.5 Four-bit less-than circuit

Figure 5.6 Array equality for arrays of equal length

Figure 5.7 Array less-than operator

Figure 5.8 Shift-left logical (sll) by 4 bits

Figure 5.9 Shift-left arithmetic (sla) by 4 bits

Figure 5.10 Rotate-left (rol) by 1 bit

Figure 5.11 Abs operator

Figure 5.12 Mapping of modulo-4 operator

Figure 5.13 Unsigned and signed modulo-4

Figure 5.14 Mapping of remainder operator

Figure 6.1 Signed resize to a larger size

Figure 6.2 Unsigned resize to a larger size

Figure 6.3 Signed resize to a smaller size

Figure 6.4 Unsigned resize to a smaller size

Figure 6.5 Fixed-point storage format

Figure 6.6 Floating-point storage format

Figure 8.1 Multiplexer interpretation of if statement

Figure 8.2 Multi-branch if statement

Figure 8.3 Incomplete if statement

Figure 8.4 Latch inference

Figure 8.5 Latched multiplexer

Figure 8.6 Interpretation of a for loop

Figure 8.7 Exit statement

Figure 8.8 Next statement

Figure 8.9 BCD to 7-segment decoder

Figure 8.10 Segment positions

Figure 8.11 Segment encodings

Figure 9.1 Simple combinational circuit

Figure 9.2 Registered circuit

Figure 9.3 Clock gating circuit

Figure 9.4 Data gating circuit

Figure 9.5 Asynchronous reset

Figure 9.6 Asynchronous reset to a value

Figure 9.7 Synchronous reset

Figure 9.8 Synchronous reset to a value

Figure 10.1 Target circuit

Figure 10.2 The two layers of indirect binding

Figure 10.3 For-generate circuit

Figure 10.4 Four-bit PRBS generator

Figure 10.5 Systole interface

Figure 10.6 Internal structure of the systole

Figure 10.7 Data flow of the systolic multiplier

Figure 10.8 Interface to the shift register

Figure 10.9 Internal structure of the systolic multiplier

Figure 12.1 Tristate driver

Figure 12.2 Tristate multiplexer using two drivers

Figure 12.3 Tristate multiplexer using one driver

Figure 12.4 Finite state machine

Figure 12.5 Signature detector state-transition diagram

Figure 12.6 Single-process finite state machine

Figure 13.1 Registered multiplexer

Figure 14.1 Project directory structure

Figure 14.2 Project subdirectory contents

Figure 15.1 Pass-band diagram for the low-pass filter

Figure 15.2 Block diagram of the FIR filter

Figure 15.3 Block diagram of the filter hardware

Figure 15.4 Actual frequency response of the low-pass filter