Book Description
This user's guide does far more than simply outline the ARM Cortex-M3 CPU features; it explains step-by-step how to program and implement the processor in real-world designs. It teaches readers how to utilize the complete and thumb instruction sets in order to obtain the best functionality, efficiency, and reuseability. The author, an ARM engineer who helped develop the core, provides many examples and diagrams that aid understanding. Quick reference appendices make locating specific details a snap!
Whole chapters are dedicated to:
Debugging using the new CoreSight technology
Migrating effectively from the ARM7
The Memory Protection Unit
Interfaces, Exceptions,Interrupts
...and much more!
*The only available guide to programming and using the groundbreaking ARM Cortex-M3 processor
*Easy-to-understand examples, diagrams, quick reference appendices, full instruction and Thumb-2 instruction sets are all included
*The author, an ARM engineer on the M3 development team, teaches end users how to start from the ground up with the M3, and how to migrate from the ARM7
Table of Contents
- Cover
- Title Page
- Copyright
- Foreword
- Preface
- Acknowledgments
- Terms and Abbreviations
- Conventions
- References
- Table of Contents
- Chapter 1: Introduction
- What Is the ARM Cortex-M3 Processor?
- Background of ARM and ARM Architecture
- Instruction Set Development
- The Thumb-2 Instruction Set Architecture (ISA)
- Cortex-M3 Processor Applications
- Organization of This Book
- Further Readings
- Chapter 2: Overview of the Cortex-M3
- Fundamentals
- Registers
- Operation Modes
- The Built-In Nested Vectored Interrupt Controller
- The Memory Map
- The Bus Interface
- The Memory Protection Unit
- The Instruction Set
- Interrupts and Exceptions
- Debugging Support
- Characteristics Summary
- Chapter 3: Cortex-M3 Basics
- Registers
- Special Registers
- Operation Mode
- Exceptions and Interrupts
- Vector Tables
- Stack Memory Operations
- Reset Sequence
- Chapter 4: Instruction Sets
- Assembly Basics
- Instruction List
- Instruction Descriptions
- Several Useful Instructions in the Cortex-M3
- Chapter 5: Memory Systems
- Memory System Features Overview
- Memory Maps
- Memory Access Attributes
- Default Memory Access Permissions
- Bit-Band Operations
- Unaligned Transfers
- Exclusive Accesses
- Endian Mode
- Chapter 6: Cortex-M3 Implementation Overview
- The Pipeline
- A Detailed Block Diagram
- Bus Interfaces on the Cortex-M3
- Other Interfaces on the Cortex-M3
- The External Private Peripheral Bus
- Typical Connections
- Reset Signals
- Chapter 7: Exceptions
- Exception Types
- Definitions of Priority
- Vector Tables
- Interrupt Inputs and Pending Behavior
- Fault Exceptions
- SVC and PendSV
- Chapter 8: The NVIC and Interrupt Control
- NVIC Overview
- The Basic Interrupt Configuration
- Interrupt Enable and Clear Enable
- Interrupt Pending and Clear Pending
- Example Procedures in Setting Up an Interrupt
- Software Interrupts
- The SYSTICK Timer
- Chapter 9: Interrupt Behavior
- Interrupt/Exception Sequences
- Exception Exits
- Nested Interrupts
- Tail-Chaining Interrupts
- Late Arrivals
- More on the Exception Return Value
- Interrupt Latency
- Faults Related to Interrupts
- Chapter 10: Cortex-M3 Programming
- Overview
- The Interface Between Assembly and C
- A Typical Development Flow
- The First Step
- Producing Outputs
- Using Data Memory
- Using Exclusive Access for Semaphores
- Using Bit-Band for Semaphores
- Working with Bit Field Extract and Table Branch
- Chapter 11: Exceptions Programming
- Using Interrupts
- Exception/Interrupt Handlers
- Software Interrupts
- Example with Exception Handlers
- Using SVC
- SVC Example: Use for Output Functions
- Using SVC with C
- Chapter 12: Advanced Programming Features and System Behavior
- Running a System with Two Separate Stacks
- Double-Word Stack Alignment
- Nonbase Thread Enable
- Performance Considerations
- Lockup Situations
- Chapter 13: The Memory Protection Unit
- Overview
- MPU Registers
- Setting Up the MPU
- Typical Setup
- Chapter 14: Other Cortex-M3 Features
- The SYSTICK Timer
- Power Management
- Multiprocessor Communication
- Self-Reset Control
- Chapter 15: Debug Architecture
- Debugging Features Overview
- CoreSight Overview
- Debug Modes
- Debugging Events
- Breakpoint in the Cortex-M3
- Accessing Register Content in Debug
- Other Core Debugging Features
- Chapter 16: Debugging Components
- Introduction
- Trace Components: Data Watchpoint and Trace
- Trace Components: Instrumentation Trace Macrocell
- Trace Components: Embedded Trace Macrocell
- Trace Components: Trace Port Interface Unit
- The Flash Patch and Breakpoint Unit
- The AHB Access Port
- ROM Table
- Chapter 17: Getting Started with Cortex-M3 Development
- Choosing a Cortex-M3 Product
- Differences Between Cortex-M3 Revision 0 and Revision 1
- Development Tools
- Chapter 18: Porting Applications from the ARM7 to the Cortex-M3
- Overview
- System Characteristics
- Assembly Language Files
- C Program Files
- Precompiled Object Files
- Optimization
- Chapter 19: Starting Cortex-M3 Development Using the GNU Tool Chain
- Background
- Getting the GNU Tool Chain
- Development Flow
- Examples
- Accessing Special Registers
- Using Unsupported Instructions
- Inline Assembler in the GNU C Compiler
- Chapter 20: Getting Started with the KEIL RealView Microcontroller Development Kit
- Overview
- Getting Started with μVision
- Outputting the “Hello World” Message Via UART
- Testing the Software
- Using the Debugger
- The Instruction Set Simulator
- Modifying the Vector Table
- Stopwatch Example with Interrupts
- APPENDIX A: Cortex-M3 Instructions Summary
- Supported 16-Bit Thumb Instructions
- Supported 32-Bit Thumb-2 Instructions
- APPENDIX B: 16-Bit Thumb Instructions and Architecture Versions
- APPENDIX C: Cortex-M3 Exceptions Quick Reference
- Exception Types and Enables
- Stack Contents After Exception Stacking
- APPENDIX D: NVIC Registers Quick Reference
- APPENDIX E: Cortex-M3 Troubleshooting Guide
- Overview
- Developing Fault Handlers
- Other Possible Problems
- Index
- Instructions for online access