Table of Contents
Instructions for online access
What Is the ARM Cortex-M3 Processor?
Background of ARM and ARM Architecture
The Thumb-2 Instruction Set Architecture (ISA)
Cortex-M3 Processor Applications
Chapter 2: Overview of the Cortex-M3
The Built-In Nested Vectored Interrupt Controller
Several Useful Instructions in the Cortex-M3
Memory System Features Overview
Default Memory Access Permissions
Chapter 6: Cortex-M3 Implementation Overview
Bus Interfaces on the Cortex-M3
Other Interfaces on the Cortex-M3
The External Private Peripheral Bus
Interrupt Inputs and Pending Behavior
Chapter 8: The NVIC and Interrupt Control
The Basic Interrupt Configuration
Interrupt Enable and Clear Enable
Interrupt Pending and Clear Pending
Example Procedures in Setting Up an Interrupt
More on the Exception Return Value
Chapter 10: Cortex-M3 Programming
The Interface Between Assembly and C
Using Exclusive Access for Semaphores
Working with Bit Field Extract and Table Branch
Chapter 11: Exceptions Programming
Example with Exception Handlers
SVC Example: Use for Output Functions
Chapter 12: Advanced Programming Features and System Behavior
Running a System with Two Separate Stacks
Chapter 13: The Memory Protection Unit
Chapter 14: Other Cortex-M3 Features
Chapter 15: Debug Architecture
Accessing Register Content in Debug
Chapter 16: Debugging Components
Trace Components: Data Watchpoint and Trace
Trace Components: Instrumentation Trace Macrocell
Trace Components: Embedded Trace Macrocell
Trace Components: Trace Port Interface Unit
The Flash Patch and Breakpoint Unit
Chapter 17: Getting Started with Cortex-M3 Development
Differences Between Cortex-M3 Revision 0 and Revision 1
Chapter 18: Porting Applications from the ARM7 to the Cortex-M3
Chapter 19: Starting Cortex-M3 Development Using the GNU Tool Chain
Using Unsupported Instructions
Inline Assembler in the GNU C Compiler
Chapter 20: Getting Started with the KEIL RealView Microcontroller Development Kit
Outputting the “Hello World” Message Via UART
Stopwatch Example with Interrupts
APPENDIX A: Cortex-M3 Instructions Summary
Supported 16-Bit Thumb Instructions
Supported 32-Bit Thumb-2 Instructions
APPENDIX B: 16-Bit Thumb Instructions and Architecture Versions
APPENDIX C: Cortex-M3 Exceptions Quick Reference
Stack Contents After Exception Stacking
APPENDIX D: NVIC Registers Quick Reference