Structure, process and integration

There are two main kinds of cell structure that use vertical channels. One is called the BiCS (Bit Cost Scalable) cell, as proposed by Toshiba in 2007.¹² The other is termed the TCAT cell (Terabit Cell Array Transistor), as proposed by Samsung in 2009.¹⁵ Both use vertical cylindrical poly-Si for the channel, but word lines (WLs) and two select gates (SGs) are horizontally stacked.

First, a review of BiCS cell structure is provided. A bird’s-eye sectional view of the BiCs cell¹⁶ is shown in Fig. 2.3. The cross-sectional view and equivalent circuit are shown in Fig. 2.4.¹⁷ A bird’s-eye scanning electron microscopy (SEM) picture of the BiCS cell is shown in Fig. 2.5(a).¹⁸ Figure 2.5(b) shows the cross-sectional SEM images for the 16-layered BiCS NAND strings fabricated by repeating the process steps for 8 layers.¹⁶ The channel is formed by a cylindrical poly-Si layer.

A junction-less undoped poly Si layer is used, because of the problems associated with atomic implant impurities. Thus, the space area of the poly NAND string must accumulate electrons by the fringing effect of the neighbouring gate during reading. The BiCS cell has a pipe-shaped channel, called the P-BiCS. Both edges of the channel are connected to a bit line (BL) and a source line (SL). Between the BL and SL, the P-BiCS cell has two selection transistors and plural memory cell transistors, with one pipe transistor at the bottom P-shaped channel. The diffusions of the selection transistors occur after the fabrication of the P-BiCS NAND strings. The gate insulator is formed by triple insulator layers, Si dioxide-Si nitride-Si dioxide (ONO). In the memory transistors, the Si nitride (SiN) layer acts as a charge storage layer to save the data, the so-called SONOS device. In conventional 2D-NAND Flash, a floating gate (FG) is used as the charge storage layer. The advantages and disadvantages of replacing FG with SiN are discussed in Section 2.4.

The basic process flow of P-BiCS is shown in Fig. 2.6.¹⁸ First, the insulator is deposited on the Si surface and a gate conductor is formed. Second, a sacrificial layer is deposited on the gate conductor (Fig. 2.6(a)). The gate conductor acts as the gate of the pipe transistor. Next, WL and select gates are stacked, with insulator layers sandwiched between them. Third, a vertical hole is made, with the subsequent removal of the sacrificial layer. Then, a P-shaped hole is made (Fig. 2.6(b,c)). Fourth, the ONO is deposited inside this P-shaped hole and undoped poly-Si is deposited there. Finally, a core filler insulator is inserted (Fig. 2.6(d)). In contrast to several of the 2D-SONOS-Flash memory devices, the Si dioxide layer must be formed by a chemical vapor deposition (CVD) process, not a thermal oxidation process. The thickness of the ONO is made up of 2.5 nm bottom tunnel oxide (TEOS), 11 nm SiN and 5 nm top oxide (TEOS).¹² The quality of such a SONOS layer made using CVD bottom oxide is as yet unknown.

The previous BICS cell¹² had a more simple structure (Fig. 2.7), with a straight poly-Si channel connecting top BL to bottom SL, and no P-shaped poly-Si channel. This was needed to be changed because of several problems relating to the straight TFT structure, such as poor reliability of memory cells, cut-off characteristics of the source side select gate and high resistance of the SL.¹⁸ For a straight poly-Si channel structure, the process flow is shown in Fig. 2.8.

First, an n⁺ layer is formed on the Si surface, and the plural insulator and WL stack are deposited. Next, holes are formed and the ONO layer is deposited. Then, the ONO layers at the bottom of the hole are etched and the poly-Si channel is deposited, to form a connection with the SL. In this process flow, the top oxide of the ONO layers is exposed to the etching conditions and quality of the bottom oxide could be degraded as a result. To avoid such degradation, pipe-shaped BiCS are proposed. The pipe gate also can reduce the resistance of the P-shaped TFT during reading. The quality improvements through using P-BiCS are summarized in Fig. 2.9.

The complete P-BICS cell array is shown in Fig. 2.10.¹⁷ At the edge of the cell array, WLs (CG0 ~ 31) are picked up by contact with the top metal layers and these are connected to the row decoder’s transistor. In order to obtain the contact with the WL, a staircase pattern is used to shape the WL. This staircase structure can be achieved (Fig. 2.11(a)),¹² and requires only one-time lithography patterning. A transmission electron microscopy (TEM) image of the contact to the stacked WL is shown in Fig. 2.11(b). Toshiba emphasizes that the number of mask steps can be kept the same, even though the number of stacks of WLs increases; this can help to minimize wafer cost.

The WL (CG_i) has a large capacitance between neighbouring WLs (CG_i + 1, CG_i − 1). During program and read, neighbouring WLs have a different bias setting and some RC delay occurs. The WL silicide process was therefore proposed to reduce the resistance (Fig. 2.12).¹⁸ A silicide process using poly-Si WL enables a sheet resistance of 11Ω/sq for a silicide thickness of approximately 42 nm (Fig. 2.13(c)). The flat band voltage (VFB) is stable, even though the layer that has undergone silicidation almost touches the gate oxide (Fig. 2.13(a,b)).

The estimated bit cost of BiCS Flash is shown in Fig. 2.14.¹⁹ There is a minimum hole size, which is limited by the thickness of ONO and radius of the body of poly-Si. Actual cell size is therefore mainly determined by the number of WL stacks. Generally, bit cost is inversely proportional to cell size and directly proportional to the process cost. For a simple stack of planar-type cells, the number of process steps is almost proportional to the number of stacks, so the process cost increases with increasing number of stacks. However, this is not the case when using the BiCS cell, which therefore implies a potential cost reduction when increasing the number of stacks. The number of WL stacks possible in a real production scenario is not yet known.

Program/erase/read operation

The program and read sequence is similar to conventional 2D-NAND Flash. During programming, a high voltage (V_prog) is applied to the selected WL with a medium voltage (V_pass) applied to the unselected WLs. In the case of 2D-NAND Flash, FN-tunnelling from channel to FG is used for programming, and from FG to channel for erasing. In the case of 3D-NAND Flash, FN-tunnelling or direct-tunnelling between the channel and SiN is used. Program disturb characteristics will be better than for conventional 2D-NAND Flash. In the case of 2D-NAND Flash, selection transistors from both sides cut off the NAND string from BL and SL at the ‘1’ programming string. Then self-boosting of the channel occurs, which can inhibit electron injection into the FG (Fig. 2.15). However, owing to the presence of the P-well, the electron flow inside the NAND string from the P-well cannot be easily cut off. By contrast, in 3D-NAND Flash, it is easier to cut off the electron flow to the program inhibit NAND string from the BL and SL, which in turn enables protection of the electron injection to SiN at the program inhibit cell (Fig. 2.16). This is one of the advantages of 3D-NAND Flash, owing to its thin film transistor structure.

In the erase operation, high voltage is applied to the channel of NAND string with the WL grounded to extract electrons from the charge stored layer. In 2D-NAND Flash, it is easy to apply high voltage to the channel by applying high voltage to the P-well under the cell array (Fig. 2.17); however, in 3D-NAND, the P-well is absent. Thus, for the erase operation, the hole current into the NAND string, generated by GIDL near the lower select gates (USG and LSG), is used to raise the body potential (Fig. 2.18).²¹ High voltage is applied to BL and SL with lower select gate voltage to create band-to-band breakdown to generate the hole current. The program/erase (P/E) characteristics are shown in Fig. 2.19.¹⁸ For the BiCS cell, the Vt shift by erasing is more than 7 V, which is higher than for 2D-SONOS-Flash. This arises from the cell shape. The shape of the ONO is cylindrical and the electric field of the top oxide can be reduced as compared with the bottom oxide field. Thus, electron reverse-injection from the gate is unlikely to occur during electron emission from the SiN to poly-Si channel. Thus, Vt can be reduced when high erase voltage is applied to the BL and SL.

By contrast, the Vt of 2D-SONOS-Flash increases by applying high erase voltage (Fig. 2.20).²⁰ This phenomenon can be explained by back-tunnelling of electrons from gate to SiN. The diameter dependence of the P/E window is shown in Fig. 2.21. The P/E window is enlarged by the smaller hole, because the electric field strength of the tunnel film is enhanced by the curvature effect.¹⁶ A comparison of program/erase characteristics between straight and pipe-shaped BiCS is shown n Fig. 2.22.¹⁶ A substantial improvement was observed at the P-BiCS, arising from the improvement in ONO quality.

In reading, I-V characteristics strongly depend on the grain boundary in the poly-Si channel. The sub-threshold characteristics of poly-silicon Field Effect Transistors (FETs) are dependent on the location of the grain boundary and the trap density at the grain boundary, which in most cases cannot be controlled. In order to achieve better control, it has been proposed to use body silicon thinner than the depletion width (Wd).²¹ By using a thinner poly-Si body, the total number of traps can be reduced and the threshold voltage can be made less sensitive to trap density fluctuation; Fig. 2.23 provides an explanatory model. The structure of the ‘macaroni’ body vertical FET is shown in Fig. 2.24. Very thin poly-Si is deposited on the ONO layer. The hollow centre of the body is filled by dielectric film to make process integration easier. Figure 2.25 shows the drain current–control gate voltage (Id-Vg) characteristics of the macaroni body vertical FET; the I-V characteristics are improved.

Figure 2.26 shows the simulated electric field across the vertical FET. The reduced body thickness enables better control of the channel potential by the gate electrode. A comparison between the Vt distribution of macaroni vertical FET and conventional, thick poly-Si FET is shown in Fig. 2.27.¹⁹ The Vt distribution width of the macaroni FET is narrower than for the conventional case. Measured Vth variations of several types of vertical FETs are plotted as a function of polysilicon body radius, or macaroni thickness (Fig. 2.28).²¹ Dispersion of the Vt variation can be reduced by making the body Si thinner. The macaroni body design offers better control to 30 nm generation; after that point, the diameter of the plug is small enough to suppress Vth variation. Details of Vt fluctuation by poly-Si grain are described in Section 2.4.

BiCS NAND Flash specification

Block size (erase cell unit) is number of WL in one string × number of cells in one WL × number of strings in one BL. The block size becomes very large as the number of WL stacks increases. Thus, the architecture of the NAND controller and file system using BiCS cell must be altered. The situation for the following TCAT cell is the same.

Structure, process and integration

The horizontal channel cell differs from the vertical channel cell in that it has a vertical control gate (VG) and vertical select gate (VG). The vertical gate cell was proposed by Samsung in 2009.²² The BL and WL are formed before the deposition of several stacks of poly-Si channels. The vertical gate is formed after horizontal poly-Si channel patterning (Fig. 2.37). A brief process flow is shown in Fig. 2.38. The BL is fabricated first, then the WL is formed on top of it. Next, multi-active layers with p-type poly-Si are formed, and patterning is carried on the multi-active layers. Third, charge trap layers (ONO) are deposited over the patterned active layers. The VG is formed consecutively and connected to the WL. Finally, vertical plugs of DC and source-Vbb are connected to the BL and SL after contact ion implants. The N⁺ doped source and p-type active layer are electrically tied to the SL. The vertical WL needs to align with the horizontal WL. It is difficult to shrink the horizontal WL pitch to avoid the misalignment and process steps are complicated.

In 2011, Macronix also proposed a vertical gate 3D-NAND cell, which can eliminate the bottom BL and WL formation (Fig. 2.39).²³ First, several stacks of insulator and undoped poly-Si are deposited. Then, patterning of the stacked insulator and poly-Si layers is carried out simultaneously. Next, the deposition of ONO dielectric and sequentially gate material fill the space between the horizontal stack of insulator and poly-Si. Patterning of the gate material is then carried out. Finally, the contact hole of the BL and SL is formed, connecting the stack of poly-Si layers and the deposits of SL and BL.

One of the difficulties with this vertical gate structure is how to select one horizontal poly-Si layer for program and read. One method is to create multiselect gates (SSL) between the BL and WL (Figs 2.37 and 2.40).²² In order to select one poly-Si layer, some selected transistors must be of the depletion type (normally ON) and others must be of the enhancement type. To distinguish between depletion and enhancement transistors, two kinds of channel doping and one heavy S/D implant are needed, which cannot be achieved by self-aligning to the SSL. Formation of plural select gates (SSL) requires some area penalty in each NAND string and the number of process steps for the channel implant increases as the number of stacks increases.

Another, more complex, method is shown in Fig.2.41.²⁴ A schematic diagram of the twisted BL layout is provided in Figs 2.42 and 2.43, which will be termed here as the ‘VG twisted-BL cell’. When 8 horizontal poly-Si layers are stacked, a chunk of memory cells inside one horizontal plane is divided into 8 × 2 × M groups (page), where M is the number of WLs in one NAND string. First, memory cells in one horizontal plane are divided into two parts (even and odd poly-Si lines). Next, even (or odd) cells connected to one WL are divided into eight pages (the same as the number of poly-Si stacks). One set of even (or odd) consecutive eight NAND strings (each poly-Si channel is assigned a page, from 0 to 7) share one BL, and eight individual SSLs (selection transistors) select only one poly-Si channel among eight strings. Even cell groups have a contact to the BL at one edge of the NAND string, and odd cell groups also have a BL contact at the other edge of the NAND string. Each BL poly-plug has one connection to one BL-pad (red circle), and other poly plugs have no connection to this BL-pad (white circle) (Fig. 2.42(b)).

There are two BL-pads at both edges of one NAND string. Eight selection transistors (SSL) are independently connected to metal 2 lines (M2), and M2 lines are connected to metal lines (M1) parallel to the WL. M1 lines run from cell array area to row decoder, in the same way as the WL. There are also two SLs in one NAND string, at both edges of one NAND string. In total, for one pair of even and odd NAND strings, there are two sets of these (BL-pad, SSL, GSL, SL), where the GSL is a source-side selection transistor. Therefore, the NAND string length becomes larger. Figures 2.44(a, b and c) shows a SEM picture of the cross-section of the 8-layer cell array. Each poly-Si channel and oxide thickness is 30 nm. The inset in Fig. 2.44(a) shows the zoomed-in view, which reveals the double-gate TFT BE-SONOS charge-trapping memory cell. Figure 2.44(b) provides a cross-sectional view of the island-gate SSL device. The SSL has double-pitch of channel BL, and is fabricated together with the WL. Figure 2.44(c) shows a cross-sectional view of the 37.5 nm half-pitch WLs. At the top of the WL, there is a 60 nm-thick WSix to reduce the WL RC delay. Figure 2.45 shows the BL poly-plug connected to the BL contact. Before filling the poly-plug to the BL contact, a sidewall lateral recess is created to form the isolation between poly plugs and BL-pad.

Program/erase/read operation

The memory cell electrical characteristics should be basically similar to BiCS or TCAT cells. One structural difference is that the VG cell is sandwiched by twin control gates, not surrounded by a gate-all-around cell. Another difference is in the gate dielectric material. In case of the cell proposed by Macronix, use is made of BE-SONGS dielectrics, not ONO.²⁵ The erasing method is the same as for a BiCS cell. By applying high voltage to the BL or SL with low select gate bias, GIDL hole current flows into the NAND string, which raises the channel body potential. The ONO shape of BiCS or TCAT is a cylinder. However, the equivalent VG-NAND shape is rectangular. Thus, the top oxide electric field is the same as the bottom oxide. BE-SONOS dielectric is necessary to suppress the reverse electron tunnelling from gate to SiN during erasing, which is different from BiCS or TCAT cells.

VG-NAND Flash specification

The spec of the ‘VG twisted-BL’ NAND Flash is described below. As explained in the previous terms of cell structure, a chunk of cells in one poly-Si plane have 2 × N pages when the number of the poly-Si stack is N. Cells in one page are programmed or read simultaneously. Thus, in the case of a 1 bit/cell, one WL has 2 × N × N pages, because Nth layer stacks have common WL. Then, the page number of a 2 bit/cell is 4 × N × N. If VG Flash has 8 layer stacks, one WL has 128 pages for 1 bit/cell. Figure 2.46 shows the programming characteristic, where BL24 is selected to program. Conventional 2D-NAND Flash has one or two pages in one WL, and a BiCS or TCAT cell will also have one or two pages, in the same way. Therefore, a very long time is needed for the programming and reading of one WL at a VG twisted-BL cell, compared with others. Accordingly, care should be taken to prohibit program disturb and read disturb, because of the longer stress time than for other cases.

Data retention

Generally the reliability of SONOS-Flash is worse than that of the FG type. One reason is the thinner bottom oxide in SONOS-Flash, which is less than about 4 nm. This is almost half the oxide thickness of 2D FG-NAND Flash. Thus, the leakage of current from the bottom oxide in 2D SONOS-Flash is larger than for FG-NAND Flash, and the data retention characteristics become worse than for FG Flash. The data retention characteristics of 3D-NAND should be the same as for 2D SONOS-Flash, which implies that data retention is worse than for 2D FG-NAND Flash.

The next problem is electron diffusion inside the SiN layer. It is well known that during a high-temperature bake, there is a larger Vt drop when the SiN layer is not cut off from neighbouring cells (Fig. 2.51).²⁸ The ΔVt depends on the neighbouring cell’s data, and a checkered pattern creates a lateral electric field inside the SiN, thereby helping electrons to diffuse into neighbouring cells. Thus, in order to obtain better retention characteristics, the SiN layer should be isolated from neighbouring cells. However, in the 3D-NAND Flash, this cannot be achieved, owing to the restriction of process/integration. In the case of VG-NAND Flash, there is another cell-to-cell interference occurring between two horizontal poly-Si layers (Fig 2.52(b)).

Among the three types of 3D-NAND Flash, the TCAT cell is superior at overcoming this issue (Fig. 2.53). Thus, to obtain better reliability, a longer WL-to-WL space and longer gate length are required. However, to obtain high cell current, the WL space needs to be smaller. Poly-Si FET is intrinsic and electron accumulation must be achieved by the fringing effect of the gate (Fig. 2.54). Thus, it is a trade-off between optimizing cell reliability and still obtaining a large cell current. These reliability issues have meant that the potential for 2 bit/cell operation has been unclear for 3D-NAND Flash, until now. However, by using FG-type NAND Flash, a 2 bit or 3 bit/cell will be possible. There are several proposals for FG-type 3D-NAND Flash.^29,30 However, from the perspective of the constraint imposed by process integration, the FG type 3D-NAND Flash is more complex than the SONOS type 3D-NAND flash.

Vt distribution widening due to SiN to SiN coupling

It is well known that neighbouring FG-FG coupling causes undesired programmed Vt widening, when the gate space is narrower. Compared to FG-type NAND, the SiN layer is thinner. Thus, SiN-SiN coupling has a smaller effect than FG-type coupling, although the effect still cannot be neglected (Fig. 2.55).³¹

Erase Vt saturation phenomena

As poly-Si channel radius becomes smaller, the erase Vt saturation phenomenon occurs through using a junction-less NAND string.³² During reading, the gate voltage of the selected cell must be 0 V or negative when the selected cell is in the erased state. Thus, owing to the gate fringing effect, electrons in the WL-to-WL space regions are reduced, which results in a reduction of cell current. Figure 2.56 shows the cell I-V characteristics with various charges in the SiN layer. Vt is not proportional to Q_SiN, as Q_SiN becomes negative. This effect is becoming more serious as the poly-Si channel become thinner (Fig. 2.57). As explained in Section 2.2, erase Vt can be lowered as the poly-Si cylindrical radius is made smaller, because of the bottom oxide electric field enhancement during erasing. An optimized radius is necessary to achieve high erase efficiency.

Vt variation due to the poly-Si grain

The poly-Si grain boundary induces a variation in I-V characteristics. There are many traps at the grain boundary, making a potential barrier ϕ_B. The potential barrier depends on grain size Lg and carrier density N (Fig. 2.58).³³ Grain boundary conductance is proportional to exp(− βϕ_B), which has strong dependence on temperature, and increases Vt while reducing Gm. The grain size dependence of Id-Vg characteristics has been studied with different poly-Si processes.³⁴ Three undoped poly-Si process options are compared according to their average grain size:

Figure 2.59 shows the Gm values for different channel materials and temperatures. High temperatures result in a larger grain size, and larger grain poly-Si also results in larger Gm. Cylindrical cell diameter dependence on Gm at RT is shown in Fig. 2.60(a). A smaller diameter results in smaller Gm. The average value of Gm can be described as proportional to cylindrical size (πR²) multiplied by gate oxide capacitance (Cox) (Fig. 2.60(b)). Thus, in order to obtain a high cell current, the cell diameter cannot be too small.

For the case of a double gate VG-NAND cell, TCAD simulation results have been obtained with and without a grain boundary at the cell channel region, where grain size is estimated to be 20~50 nm.³⁵ The simulation results in Fig. 2.61(b) indicate that the case with a grain boundary between the gate-to-gate space undergoes less degradation than in the fresh state (no Dit), whereas the case with a grain boundary under the channel has significant sub-threshold degradation and higher Vt. In Fig. 2.61(c), the many Id-Vg curves of the random grain boundary locations are compared with each other. Interestingly, the currents merge at a very low current level (< 1 fA, beyond the typical measurement resolution). Theoretically, the merged point corresponds to the mid-gap voltage, where the interface trap becomes charge neutral and unable to affect the sub-threshold current.