1. If the output is below +V_SAT and above −V_SAT, then v_D will be very near 0 volts.

2. If v_D is anything other than near 0 volts, then the amplifier will be at one of the two saturation voltages (±V_SAT).

1. Voltage gain

2. Input impedance

3. Input current requirement

4. Slew-rate limiting frequency

5. Maximum output voltage swing

6. Maximum input voltage swing

7. Output impedance

8. Output current capability

9. Minimum value of load resistance

10. Bandwidth

11. Power supply rejection ratio

Voltage Gain.

You will recall that the voltage gain for this circuit is determined by the ratio of R_F to R_I or simply

(2.6)

The minus sign is used to remind us of the phase inversion since this is an inverting amplifier. Do not interpret the minus as a loss or a reduction in signal strength. For the circuit in Figure 2.3 the voltage gain will be

We can express this as a decibel gain by applying Equation (2.2):

In this conversion, we must be particularly careful not to include the minus sign as part of the voltage gain. First, we will be unable to compute the logarithm. Second, if we tried to put the minus sign in after the calculation the resulting negative decibel answer would be misinterpreted as a loss.

It is important to note that the voltage gain computed in this section is the ideal closed-loop voltage gain of the circuit. The actual circuit gain will roll off as the input frequency is increased. This effect is discussed below as part of the discussion on bandwidth.

Input Impedance.

The input impedance of the amplifier shown in Figure 2.3 is that resistance (or impedance) as seen by the source (v_I). You will recall that the voltage between the (+) and (−) terminals of the op amp (v_D) will always be about 0 unless the amplifier is saturated. Since the (+) terminal is connected to ground (via R_B) in the inverting amplifier circuit, it is reasonable to assume that the (−) pin will always be near ground potential even though it is not and cannot be connected directly to ground. But, since the (−) input is essentially at ground potential we call this point in the circuit a virtual ground.

Considering that the (−) pin is a virtual ground, it becomes apparent that the input impedance seen by the source is simply R_I. That is, as far as current demand is concerned, resistor R_I is effectively connected across the signal source. The equation for input impedance then is given by Equation (2.7).

(2.7)

For the case of the inverting amplifier shown in Figure 2.3, the input impedance is computed as follows:

In general, as long as the (−) pin remains at a virtual ground potential, the input impedance will be equal to the impedance between this pin and the source. If the impedance is more complex (e.g., resistor capacitor combination), then you must use complex numbers to represent the impedance. The basic method, however, remains the same.

Input Current Requirement.

Ohm’s Law can be used to calculate the amount of current that must be supplied by the source. Recall that essentially no current flows into or out of the (−) terminal of the op amp. Therefore the only current supplied by the source is that drawn by R_I. Since R_I is effectively in parallel with the source due to the effect of the virtual ground, the input current can be computed as follows:

(2.8)

Since this is a sinusoidal waveform, we could easily convert this to an RMS value if desired as shown:

(2.9)

In our present case, the RMS value is found as follows:

As long as the input source can supply at least this much current without reducing its output, the op amp circuit will not load the source.

Maximum Output Voltage Swing.

The output voltage of an op amp is limited by the positive and negative saturation voltages. These can both be approximated as 2 volts less than the DC supply voltage. Since the DC supply in Figure 2.3 is ±15 volts, the saturation voltages will be +13 volts and -13 volts for the positive and negative limits, respectively. Thus, the maximum output voltage swing is computed as follows:

(2.10)

For the circuit in Figure 2.3, the maximum output voltage swing is found as shown:

Since both DC supplies are equal, the output can swing equally above and below 0. This is the normal condition.

If you desire to be more accurate in the estimation of output saturation voltage, you may refer to the manufacture’s data sheet in Appendix 1. The manufacturer lists minimum and typical output voltage swings for different values of load resistance.

Slew-Rate Limiting Frequency.

It should also be noted that the above maximum output is only obtainable for frequencies below the point where slew rate limiting occurs. This frequency can be estimated with the following equation:

(2.11)

In the case of the circuit being considered, the highest frequency that can produce a full output swing without distortion caused by slew rate limiting is computed as

If we attempt to amplify frequencies higher than 6.12 kilohertz (and full amplitude) with the circuit shown in Figure 2.3, then the output will be nonsinusoidal. Once the input frequency goes higher than a certain frequency (about 9 kilohertz in this case), then the output amplitude begins to drop in addition to the distorted shape.

Maximum Input Voltage Swing.

We have computed the voltage gain of the circuit, and we know the maximum output voltage swing. We, therefore, have enough information to compute the largest input signal that can be applied without driving the amplifier into saturation.

(2.12)

Calculations for the present case are shown below:

Since we are working with sinusoidal waveforms, we might choose to express this value as peak or RMS as shown below:

(2.13)

For our present circuit, we have

Also,

(2.14)

In the present case,

So, for the amplifier circuit presented in Figure 2.3, input signals as great as 756.5 millivolts RMS can be amplified without saturation clipping. If you attempt to amplify larger signals, then the peaks on the output waveform will be flattened at the output saturation voltage limits.

Output Impedance.

You will recall from Chapter 1 that the output impedance of an op amp is generally quite low. The data sheet in Appendix 1 lists 75 ohms as a typical output resistance for a 741 op amp. This value, however, is the open-loop output resistance. When negative feedback is added to the amplifier (as in Figure 2.3) the effective output impedance decreases sharply. The value of effective output impedance can be approximated as shown:

(2.15)

where A_OL is the open loop gain of the op amp at the specified frequency. This can be read from the manufacturer’s graphical data (see Appendix 1) showing open-loop gain as a function of frequency. Alternatively, you may estimate it as

(2.16)

where f_IN is the specific input frequency being considered.

For the circuit in Figure 2.3, the closed-loop output impedance can be estimated at 1000 hertz as follows. First we compute the open-loop gain at 1000 hertz by applying Equation (2.16):

Next compute the effective output impedance with Equation (2.15):

This low value approaches our ideal value of 0 ohms. Now, as an illustration, recompute the value of output impedance at a higher frequency of 5 kilohertz.

First compute A_OL with Equation (2.16).

Next compute the effective output impedance with Equation (2.15).

This value is significantly higher than our first estimate and clearly shows the increase in output resistance as the input frequency is increased.

How does a particular value of output impedance affect the performance of the amplifier circuit? To understand the effects, we can examine the equivalent circuit shown in Figure 2.4. Here we see a voltage source labeled v_O driving a series circuit.

The v_O source is that voltage that would be present at the output of the op amp if the output impedance were truly 0 ohms. You can see that this ideal voltage (v_O) is divided between the output impedance (r_O), which is internal to the op amp, and R_L, which is the op amp load. The voltage reaching the load can be computed with the voltage divider equation.

(2.17)

Let us compute the actual load voltage in Figure 2.3 at a frequency of 5 kilohertz. First we compute the ideal output voltage Equation (2.1):

We have found the value of r_O at 5 kilohertz to be 4.96 ohms. Using the method shown in Figure 2.4, we can now determine the actual load voltage with Equation (2.17).

At a frequency of 5 kilohertz when the output resistance has increased to nearly 5 ohms, the effect of nonideal output resistance is minimal. Problems could be anticipated when the output resistance exceeds 1 percent of the value of load resistance.

Although the preceding calculation illustrates the effects of output resistance, it is valid only if we are below the frequency that causes slew rate limiting (f_SRL). If f_SRL is exceeded, we can expect the actual output to be much lower than the value computed with Equation (2.17), and the output will be nonsinusoidal in shape. Additionally, this method is inappropriate if the output drive capability of the op amp is exceeded.

Output Current Capability.

The output of the op amp in Figure 2.3 must supply two currents: the current through the feedback resistor (i_F) and the current to the load resistor (i_L). It is the sum of these currents that flows into or out of the output of the op amp.

The output of many (but not all) op amps is short circuit protected. That is, the output may be shorted directly to ground or to either DC supply voltage without damaging the op amp. For a protected op amp (such as the 741), the output current capability is not determined by the maximum allowable current before damage, but rather depends on the amount of reduced output voltage the application can tolerate.

With no output current being supplied to the load, the output voltage stays at the expected v_O level, and the total output current is equal to i_F. As the load current is increased (load resistance decreased), the actual output voltage begins to drop as shown in the previous section. Finally, if the load resistance is reduced all the way to 0 ohms, the output current will be limited to a safe value. This value can be found in the data sheet (Appendix 1), and is 20 milliamps for the 741 device.

As the load resistance varies from infinity (open) to zero (short), the output current from the op amp varies from i_F to 20 milliamps. The limiting factor is the amount of reduction that can be tolerated on the output voltage.

The amount of current (i_F) flowing through the feedback resistor is easily computed with Ohm’s Law as

(2.18)

On an unprotected op amp, the value of load current plus the value of feedback current must be kept below the stated output current rating. If this value is not supplied in the data sheet, then it can be estimated by using the maximum power dissipation data; recall that power = voltage × current.

Minimum Value of Load Resistance.

The minimum value of load resistance is determined by the maximum value of output current (determined in the previous section). The actual computation is essentially Ohm’s Law:

(2.19)

where i_L is the maximum allowable output current of the op amp minus the current (i_f) flowing through the feedback circuit, and v_L is the minimum acceptable output voltage.

Note that in many, if not most, applications, the value of output current needed for the load is substantially below the limiting value, so no significant loading occurs.

Let us assume that the application shown in Figure 2.3 requires us to have at least 1.19 volts across the load when 100 millivolts is applied to the input terminal. Let us further assume that the frequency of interest is 5 kilohertz. From previous calculations we know that the voltage gain (A_V) is 12.2 (ignoring the effects of bandwidth described in the next section) and that the output resistance at 5 kilohertz is 4.96 ohms.

Figure 2.5 shows the equivalent circuit at this point. The value of i_O can be computed with Ohm’s Law.

(2.20)

More specifically,

The value of i_F can also be computed using Ohm’s Law, Equation (2.18).

Kirchhoff’s Current Law can now be used to determine the value of load current (i_L).

(2.21)

Calculations for the present example are shown below:

Using Ohm’s Law, Equation (2.19), we can now compute the value of R_L.

With this small value of load resistance, we would not be able to provide full-range voltage swings on the output because of excessive loading.

In the foregoing calculations (as with most calculations presented in this book), it is not important to remember all of the equations. Rather, strive to understand the concept and realize that most of what we are discussing is centered on basic electronics principles that you learned when you studied introductory AC and DC circuits.

Bandwidth.

Although the bandwidth of an ideal op amp is considered to be infinite, the bandwidth of real op amps and the associate amplifier circuit are definitely restricted. In the case of the circuit shown in Figure 2.3, the lower cutoff frequency is essentially 0. That is, since the op amp responds all the way down to DC, and since there are no reactive components to reject the lower frequencies, the amplifier circuit will operate with frequencies as low as DC.

The upper cutoff frequency is quite a different story. Figure 2.6 shows the open-loop frequency response (upper curve) for a 741 op amp. This is the same curve presented in the manufacturer’s data sheet as open-loop voltage gain as a function of frequency. Also drawn on the graph in Figure 2.6 is a line showing a voltage gain of 12.2. This is the ideal closed-loop gain that we calculated for the circuit in Figure 2.3.

Notice that the difference between the open- and closed-loop gain curves is maximum at low frequencies. As the frequency increases, the difference between the two curves becomes less. Near the right side of the graph, the two curves actually intersect. What really happens to the overall circuit gain as the frequency increases?

The derivation of the formula for amplifier voltage gain (A_V = −R_F/R_I) was based on the assumption that the op amp had an infinite (or at least a very high) voltage gain. This allowed us to make the assumption that the differential input voltage (v_D) was 0. As you can see from the graph in Figure 2.6, our assumptions are reasonable for low frequencies. That is, the open-loop voltage gain is very high. But as the frequency increases and the open-loop gain rolls off, our assumptions begin to lose their validity. The most obvious proof of this exists beyond the point of intersection of the open- and closed-loop curves. In the region to the right of the intersection point, the open-loop gain is actually lower than our calculated closed-loop gain, thus making it impossible for our circuit to deliver the desired amplification.

It is common to compute bandwidth in a circuit like that shown in Figure 2.3 by applying the following equation:

(2.22)

where f_UG is the unity gain frequency of the op amp. Substituting values and computing gives us the following:

The actual frequency response for the circuit shown in Figure 2.3 is plotted in Figure 2.7. This represents the circuit’s real behavior. Two additional lines are superimposed on the plot for reference: the open-loop frequency response curve of the 741 op amp and the ideal gain curve of the circuit in Figure 2.3.

Power Supply Rejection Ratio.

If the DC supply lines (V⁺ and V⁻) have noise, particularly high-frequency noise, these noise signals may affect the output signal. The degree to which the op amp is affected by the power supply noise is called the power supply rejection ratio (PSRR). The manufacturer’s data sheet normally expresses this parameter in microvolts per volt. To determine the magnitude of the noise signal on the output for a given amplitude of noise signal on the supply lines, we can use the following calculation:

(2.23)

where v_NO, v_N, R_F, R_I, and PSRR are the values of the output noise signal, the noise signal on the DC supply lines, the feedback resistor, the input resistor, and the power supply rejection ratio, respectively. For example, refer to Figure 2.8.

The manufacturer’s data sheet in Appendix 1 for a 741 op amp lists the power supply rejection ratio as ranging from 30 to 150 microvolts per volt. Thus, the worst-case effect on the output voltage for the circuit in Figure 2.8 is computed with Equation (2.23) as

In other words, the amplitude of the power line noise (v_N) will be reduced by a factor of 0.003525. This means, for example, that if the DC supply lines have noise signals of 100 millivolts peak-to-peak, then we can anticipate a similar signal in the output with an amplitude of about

1. Voltage gain

2. Maximum input current

3. Frequency range

4. Load resistance

5. Maximum input voltage

Determine an Initial Value for R_I.

The minimum value for R_I is determined by the maximum input voltage and the maximum input current and is computed with Ohm’s Law as follows:

(2.24)

In this case, the calculations are

As a general rule, you should avoid designing amplifiers with input resistances of less than 1000 ohms unless you have a specific need for them. In our present case, the computed minimum (2.0 kilohms) is greater than 1000 ohms, so we will use the computed value. It should also be noted that the minimum input impedance is often determined by the needs of the application.

Determine the Value of R_F.

R_F can be computed from the voltage gain equation, Equation (2.6):

Note that the inversion sign is omitted from the equation when computing a resistance value. For the present example, we compute R_F as follows:

Determine the Required Unity Gain Frequency.

The minimum unity gain frequency for the op amp can be estimated by applying Equation (2.22). For the present case, we have

Since this is well below the 1.0-megahertz unity gain frequency of the 741, we should be able to use the 741 in this application (with regard to bandwidth).

Determine the Minimum Supply Voltages.

The minimum supply voltages are computed by simply ensuring that the maximum expected output voltage swing is no greater than the ±V_SAT values. The maximum output swing can be found by using the basic equation, Equation (2.1), for voltage gain:

In our particular example, the maximum output voltage will be

Notice the multiplying factor 1.414 to convert our input voltage (given in RMS) to a peak or worst-case value. The manufacturer’s data sheet in Appendix 1 indicates that the 741 op amp will produce at least a ±12-volt output swing with a ±15-volt supply voltage as long as the load resistor is at least 10 kilohms. Thus, we can infer that we have a worst-case internal voltage drop of 15 – 12, or 3 volts. This means that the minimum power supply voltage for our circuit must be higher than the maximum output voltage by the amount of the internal voltage drop (V_INT). That is,

(2.25)

For our particular case, the minimum power supply voltages will be

Anything greater than ±11.48 volts for the DC supply will be adequate; therefore, let us choose the standard values of ±15 volts for our application.

Determine the Required Slew Rate.

The required slew rate of the op amp is affected by the highest operating frequency and the maximum output voltage swing. In our present case, the highest input frequency has been specified as 2.5 kilohertz. The maximum peak-to-peak output voltage swing (v_O(max)) was previously computed as 16.96 volts. The minimum required slew rate for the op amp is determined by rearranging Equation (2.11) to yield

Since the slew rate of the 741 exceeds this minimum value, we can continue with our initial op amp selection. If the above calculation indicates a higher requirement than our preliminary op amp selection can deliver, then another op amp must be selected that has a higher slew rate.

Calculate the Value of Compensation Resistor (R_B).

The compensation resistor (R_B) reduces the error in the output voltage caused by the voltage drops that result from the op amp’s input bias currents. To achieve maximum error reduction, we try to place equal resistances between both op amp input terminals and ground. If we were to apply Thevenin’s Theorem to the inverting input circuit, we would see that resistors R_F and R_I are effectively in parallel. This means that the optimum value for R_B is simply the combined value of R_F and R_I in parallel.

(2.26)

For the present example, we compute R_B as follows:

The final schematic is shown in Figure 2.9.

The actual behavior of the circuit is indicated in Figure 2.10 by an oscilloscope display. The measured performance is compared to the design goals in Table 2.1.

1. Voltage gain

2. Input impedance

3. Input current requirement

4. Maximum output voltage swing

5. Slew-rate limiting frequency

6. Maximum input voltage swing

7. Output impedance

8. Output current capability

9. Bandwidth

10. Power supply rejection ratio

Voltage Gain.

We know by inspection of the circuit in Figure 2.12 that the voltage on the (+) input is approximately equal to v_I. That is, there is no significant voltage drop across R_B because the only current allowed to flow through R_B is the op amp bias current (ideally 0). We also know from previous discussions that the voltage between the (+) and (−) input terminals (v_D) is very near 0 volts. Thus, we may rightly conclude that the voltage on the (−) pin is approximately equal to the value of V_I.

Ohm’s Law can be used to compute the current through R_I as follows:

(2.27)

For the circuit in Figure 2.12, we have

Since negligible current flows into or out of the input of the op amp, we will assume that all of the current flowing through R_I continues through R_F, according to Kirchhoff’s Current Law. The voltage drop across R_F can be computed by applying Ohm’s Law.

The output voltage can be determined through application of Kirchhoff’s Voltage Law. That is, we know the voltage on the (−) input is 2.0 volts peak. The output voltage will be greater than this by the amount of voltage drop across R_F. It is computed as

The voltage gain can be computed by the basic gain equation, Equation (2.1), as shown:

Recall from an earlier discussion that the voltage gain of the circuit is largely determined by the ratio of R_F to R_I. More specifically, the low-frequency or ideal voltage gain of the circuit can also be calculated with the following equation:

(2.28)

In our case, the calculations are

This latter method is the most common, but the former provides additional insight into circuit operation and the application of basic electronics principles.

The voltage can be expressed in decibels if desired, as we did with inverting amplifiers. In our present example, the equivalent voltage gain expressed in decibels is:

Note that the voltage gain computed in this section is the ideal closed-loop voltage gain of the circuit. The actual circuit gain will roll off as the input frequency is increased, just as it did with inverting amplifiers. This effect is discussed below as part of the discussion on bandwidth.

Input Impedance.

The input impedance of the noninverting amplifier circuit (refer to Figure 2.12) is essentially equal to the input impedance of the (+) input terminal of the op amp modified by the feedback effects. That is, the only current leaving the source must flow into or out of the op amp as bias current for the (+) input. The manufacturer’s data sheet for a 741 is shown in Appendix 1. It indicates that the input resistance is at least 0.3 megohms and is typically about 2.0 megohms. Recall that this is the effective resistance between the two op amp inputs. By considering the output impedance to be near 0, we can sketch the equivalent circuit shown in Figure 2.13(a).

Let us make the following substitution for the value of v_O:

This, of course, comes from Equation (2.1) and Equation (2.28). If we now apply Thevenin’s Theorem to the portion of the circuit to the right of the dotted line, we obtain the equivalent circuit shown in Figure 2.13(b). Notice that the resistance in our equivalent circuit has the same voltage (2 V_PK) on both ends, which produces a net voltage of 0. If there is no voltage, there will be no current, so the effective input impedance is infinite. This represents the ideal condition.

In a real op amp circuit, the differential input voltage (v_D) is greater than 0 and increases as the frequency increases. With reference to Figure 2.13(b), as the input frequency increases, the two voltage sources become more and more unequal. This causes a difference in potential across the resistance in the circuit, which in turn produces a current flow. The increasing current corresponds to a decreasing input impedance. Although the actual input impedance is quite high and can normally be assumed to be infinite, it can be approximated by the following equation:

(2.29)

where R_OP is the value of input resistance provided by the manufacturer and A_V is the open-loop voltage gain of the op amp. For the circuit shown in Figure 2.12, we can estimate input resistance at low frequencies as

If we had used the more typical value of 2.0 megohms for the op amp resistance (R_OP), we would have gotten a much higher value for input resistance. In either case, the actual effective input resistance is extremely high. This high input resistance is one of the primary advantages of the noninverting amplifier in many applications.

Input Current Requirement.

The input current can be estimated by applying Ohm’s Law to the input circuit as follows:

Even this is a worst-case value. If we had used the higher typical value for input resistance, we would have computed an even smaller value. For many, if not most, applications, this input current can be considered negligible. If it becomes necessary to consider this current, then additional considerations must be made because the exact value of input resistance varies considerably with temperature and frequency.

Maximum Output Voltage Swing.

As we found with the inverting amplifier, the output voltage of an op amp is limited by the ±V_SAT levels. For most applications utilizing a bipolar op amp, the saturation voltages can be estimated at about 2 volts less than the DC supply voltage. In the case of Figure 2.12, we compute the maximum output swing, Equation (2.10), as

If a more accurate value is desired, the manufacturer’s data sheet can be used to find a more precise value for the worst-case saturation voltage.

Slew-Rate Limiting Frequency.

The highest frequency that can be amplified without distorting the waveform, because of the slew rate limitation of the op amp, is given by Equation 2.11.

If it is known for certain that the actual output swing will never be required to reach its limits, then the lower actual output swing can be used in place of v_O(max) in the above calculation.

Maximum Input Voltage Swing.

The maximum input voltage swing is simply the highest input voltage that can be applied without driving the output past the saturation point. It is computed in the same manner as that for the inverting amplifier.

Since we are working with sinusoidal waveforms, we might choose to express this value as peak, as in Equation (2.13), or RMS, as in Equation (2.14), as shown:

and

If you attempt to amplify signals larger than 1.425 volts RMS, then the peaks on the output waveform will be flattened at the output saturation voltage limits.

Output Impedance.

You will recall from the analysis of the inverting amplifier that the effective output impedance decreases sharply from the open-loop value stated in the manufacturer’s data sheets. The value of effective output impedance can be approximated by applying Equation (2.15).

where A_OL is the open-loop gain of the op amp at a particular frequency. For the circuit in Figure 2.12, the open-loop gain at 2500 hertz is computed with Equation (2.16) as

The output impedance at 2500 hertz can then be estimated as

In most cases, the output impedance is so low relative to the value of load resistance that the output voltage is essentially unaffected, but you can always be sure by performing the voltage divider calculation outlined in Section 2.2.2.

Output Current Capability.

If the output of the op amp is short-circuit protected (as in the 741), then the output current capability is limited by the maximum allowable drop in output voltage for the given application. This can be estimated with Ohm’s Law as discussed in the preceding section. Recall from our discussion of inverting amplifiers that the output must supply both load resistor current and the current through the feedback resistor. The feedback current is computed using Ohm’s Law. For this particular circuit, the calculations are

With no output current being supplied to the load, the output voltage stays at the expected v_O level and the total output current is equal to i_F. As the load current is increased (load resistance is decreased), the actual output voltage begins to drop because of the voltage divider action described in the previous section. Finally, if the load resistance is reduced all the way to 0 ohms, the output current will be limited to the short circuit value. This value can be found in the data sheet (Appendix 1) and is 20 milliamperes for the 741 device.

As the load resistance varies from infinity (open) to 0 (short), the output current from the op amp varies from i_F to 20 milliamperes. The limiting factor is the amount of reduction that can be tolerated on the output voltage.

On an unprotected op amp, the value of load current plus the value of feedback current must be kept below the stated output current rating. If this value is not supplied in the data sheet, it can be estimated by using the maximum power dissipation data; recall that power = voltage × current.

Bandwidth.

The discussion of bandwidth presented for the inverting amplifier circuit is also applicable to the noninverting configuration. That is, as long as the circuit has no reactive components, the frequency response will extend all the way down to DC on the low-frequency end. We can estimate the high-frequency end of the frequency response by applying Equation (2.22):

Recall that the open-loop gain of the op amp falls off rapidly as the input frequency is increased above a few hertz. As the open-loop gain value approaches the computed closed-loop gain value, the actual circuit gain also begins to drop. Thus, we begin to experience increased errors in our gain calculations as the frequency is increased.

For these equations to be valid, it is important that the op amp output voltage swing be small enough to avoid the effects of slew rate limiting. The highest amplitude that can be amplified at a given frequency without the effects of slew rate limiting is given as

(2.30)

The slew rate is determined by the particular amplifier, f is the frequency of interest, and v_O(max) is the highest peak-to-peak amplitude in the output before slew rate limiting begins to distort the signal. In the present case, if we try to operate at the upper cutoff frequency (155 kHz), we have to keep the output voltage below the value computed:

Power Supply Rejection Ratio.

The power supply rejection ratio provides us with an indication of the degree of immunity the circuit has to noise voltages on the DC power lines. The change in output voltage (v_O) for a given change in DC power line noise voltage (v_N) is computed with Equation (2.23):

where v_O, v_N, R_F, R_I, and PSRR are the values of the output noise signal, the noise signal on the DC supply lines, the feedback resistor, the input resistor, and the power supply rejection ratio (PSRR), respectively. The manufacturer’s data sheet in Appendix 1 lists the PSRR as ranging from 30 to 150 microvolts per volt. The worst-case effect on the output voltage for the circuit in Figure 2.12 is then

In other words, the amplitude of the power line noise (v_N) will be reduced by a factor of 0.000968. This means, for example, that if the DC supply lines had noise signals of 100 millivolts peak-to-peak, we could anticipate a similar signal in the output with an amplitude of about

1. Voltage gain

2. Frequency range

3. Load resistance

4. Maximum input voltage

Determine an Initial Value for R_I.

There are endless combinations of R_F and R_I that will produce the desired circuit voltage gain. The smaller the values of R_F and R_I, the higher the value of feedback current. The feedback current subtracts from the maximum available output current. Thus, we want to avoid extremely small values.

The larger we make R_F and R_I, the more the circuit operation is affected by certain nonideal characteristics. In general, neither resistor should be less than 1.0 kilohms nor more than 680 kilohms unless there is a compelling reason for them to be so. With this rule of thumb in mind, we select R_I as 4.7 kilohms.

Determine the Value of R_F.

R_F can be computed from the voltage gain equation, Equation (2.28):

For the present design example, we compute R_F as follows:

We select the nearest standard value of 33 kilohms to use as R_F.

Determine the Required Unity Gain Frequency.

You will recall from our discussions on bandwidth that the error between the calculated or ideal gain and the actual gain increases as frequency increases. We can, however, estimate the required unity gain frequency by applying Equation (2.22).

Thus, we must select an op amp that has minimum unity gain frequency of at least 40.1 kilohertz. Since the 741 has a 1.0-megahertz unity gain frequency, it should be adequate for this application with respect to bandwidth.

Determine the Minimum Supply Voltages.

The minimum supply voltages are computed simply by ensuring that the maximum expected output voltage swing is no greater than the ±V_SAT values. The maximum output swing can be found by using the basic equation for voltage gain, Equation (2.1).

In our particular example, the maximum output voltage will be

Notice the multiplying factor 1.414 to convert our input voltage (given in RMS) to a peak or worst-case value. The manufacturer’s data sheet in Appendix 1 indicates that the 741 op amp will produce at least a ±12-volt output swing with a ±15-volt supply voltage and a load resistance of at least 10 kilohms. Thus, we can infer that we have a worst-case internal voltage drop of 15 – 12, or 3 volts. The minimum power supply voltage can be determined with Equation (2.25):

Anything greater than ±12.05 volts for the DC supply will be adequate, so we choose the standard values of ±15 volts for our application. Realize that this is a worst-case calculation; a more typical internal drop would be 2 volts rather than 3 volts.

Determine the Required Slew Rate.

The minimum slew rate for the op amp is computed by transposing Equation (2.11).

Since the slew rate of the 741 exceeds this minimum value, we can continue with our initial op amp selection. If the above calculation indicates a higher requirement than our preliminary op amp selection can deliver, then another op amp must be selected that has a higher slew rate.

Calculate the Value of Compensation Resistor (R_B).

The compensation resistor (R_B) reduces the error in the output voltage caused by the voltage drops that result from the op amp’s input bias currents. As with the inverting configuration, we achieve maximum error reduction by inserting equal resistances between both op amp input terminals and ground. The resistance between the inverting input to ground is essentially equal to the parallel combination of R_I and R_F. This is easier to appreciate if you remember that the output impedance of an op amp is very low. For purposes of this analysis, assume that the output impedance is actually 0 ohms. In this condition, one end of both R_I and R_F connect to ground and the other ends connect to the inverting input terminal. Thus, they are effectively in parallel. The value of R_B is calculated as in Equation (2.26):

We will choose a standard value of 4.3 kilohms. The final schematic is shown in Figure 2.14.

The actual performance of the circuit is indicated by the oscilloscope plots in Figure 2.15. Additionally, Table 2.2 contrasts the measured performance with the original design goals.

A slight phase shift can be seen between input and output waveforms in Figure 2.15. The effect is more pronounced as the input frequency is increased. For many applications, input/output phase relations are not important; in other applications they are critical. Chapter 10 discusses this issue in more detail.

1. Voltage gain

2. Input impedance

3. Input current requirement

4. Maximum output voltage swing

5. Slew-rate limiting frequency

6. Maximum input voltage swing

7. Output impedance

8. Output current capability

9. Bandwidth

10. Power supply rejection ratio

Voltage Gain.

The ideal voltage gain of a voltage follower circuit is always unity, or 1. This can be further demonstrated by applying the voltage gain equation, Equation (2.28), presented for the noninverting amplifier circuit. Since R_F is now 0 and R_I is infinity, our calculations become

As with other amplifier configurations, the actual gain of the circuit falls off at high frequencies. This is further discussed, along with bandwidth, in a later section.

Input Impedance.

The input impedance of the voltage follower is ideally infinite because it is essentially the input resistance of the (+) input of the op amp modified by the effects of feedback. The value may be estimated by applying Equation (2.29) with the quantity R_I/(R_F + R_I) considered to be unity. Thus, for low frequencies (i.e., near DC) the circuit in Figure 2.16 will have a minimum input impedance of

If we had used typical values for R_OP, we would have gotten an even higher value for Z_IN. In any case, the value is so high that we can consider it as infinite for most applications.

Input Current Requirement.

The input current for the circuit in Figure 2.16 is only the bias current for the (+) input terminal. This is ideally 0 and for most applications may be neglected. If more precision is desired, then the manufacturer’s data sheet in Appendix 1 can be referenced. The data sheet indicates that the input bias current will be no higher than 500 nanoamperes, with a more typical value listed as 80 nanoamperes. Even though this current is temperature dependent, the absolute values are so small that they may be neglected in many applications.

Maximum Output Voltage Swing.

The maximum output voltage swing for the follower circuit is determined in the same manner, Equation (2.10), as that used with preceding amplifiers. That is,

If a more accurate value is desired, the manufacturer’s data sheet can be used to find a more precise value for the worst-case saturation voltage.

Slew-Rate Limiting Frequency.

As with the amplifier configurations discussed previously, the highest frequency that can be amplified with a full output voltage swing and no slew-rate limited distortion is computed as in Equation (2.11):

If it is known for certain that the actual output swing will never be required to reach its limits, then the lower actual output swing can be used to compute the slew-rate limiting frequency.

Maximum Input Voltage Swing.

Since the amplifier has a voltage gain of 1, the maximum input voltage swing is equal to the maximum output voltage swing. Thus, in the case of Figure 2.16, we could have an input signal as large as ±13 volts without causing the amplifier to saturate. Again, if you plan to push the amplifier to its limits, you should refer to the manufacturer’s data sheet and select the worst-case output saturation voltage at the worst-case temperature. The computations, however, remain similar.

Output Impedance.

The output impedance of the voltage follower can be computed as follows:

(2.31)

where A_OL is the open-loop gain of the op amp at the specified frequency. You can determine the value of A_OL at the desired operating frequency as in Equation (2.16):

where f_IN is the specific input frequency being considered.

For the circuit in Figure 2.16, the open-loop gain at 5 kilohertz, for example, is

The output impedance then becomes Equation (2.31).

As with most op amp circuits, the output impedance is so low relative to any practical load resistance that its effects may be ignored.

Output Current Capability.

The total current flowing in or out of the output terminal of the op amp in Figure 2.16 may be delivered directly to the load. That is, the feedback current is extremely small and can be disregarded in nearly all cases. As the load resistance varies from infinity (open) to 0 (short), the output current from the op amp varies from 0 to the short-circuit value of 20 milliamps (given in the data sheet). The limiting factor is the amount of reduction that can be tolerated on the output voltage swing.

On an unprotected op amp, the value of load current must be kept below the stated output current rating. If this value is not supplied in the data sheet, it can be estimated by using the maximum power dissipation data; recall that power = voltage × current.

Bandwidth.

The bandwidth (i.e., the upper cutoff frequency) of a voltage follower circuit may be estimated by the following equation:

(2.32)

For the circuit shown in Figure 2.16, we can compute the upper cutoff frequency and/or bandwidth as follows:

At lower frequencies, the voltage gain will be nearly equal to the calculated value of unity. As the frequency approaches the upper cutoff, the voltage gain begins to decrease. Once the input frequency exceeds 1.0 megahertz (for a 741), the overall circuit gain will decrease dramatically.

Power Supply Rejection Ratio.

The change in output voltage (v_O) for a given change in DC power line noise voltage (v_N) is computed for the voltage follower with the following equation:

(2.33)

where v_O, v_N, and PSRR are the values of the output noise signal, the noise signal on the DC supply lines, and the power supply rejection ratio, respectively. The manufacturer’s data sheet in Appendix 1 lists the power supply rejection ratio (PSRR) as ranging from 30 to 150 microvolts per volt. The worst-case effect on the output voltage for the circuit in Figure 2.16 is then

In other words, the amplitude of the power line noise (v_N) will be reduced by a factor of 0.000150. This means, for example, that if the DC supply lines had noise signals of 100 millivolts peak-to-peak, we could anticipate a similar signal in the output with an amplitude of about

Select the Op Amp.

First, we must select an op amp that can provide unity gain up to the maximum input frequency. That means we will need an op amp with a unity gain bandwidth of at least Equation (2.32):

Second, the slew rate of the op amp must be adequate to allow the required output voltage swing at the highest input frequency. The required slew rate is given by Equation (2.11):

Since both the unity gain frequency and the slew rate requirements are within the limits of the 741 (see Appendix 1), let us choose this device for our design.

Select the Power Supply Voltages.

Now we must select a power supply voltage that is high enough to prevent saturation on the highest input voltage. The worst-case internal voltage drop on the output for a 741 is listed as 5 volts in Appendix 1 for load resistances between 2 and 10 kilohms. A more typical value is 2 volts. The minimum required power supply voltage can be determined as in Equation (2.25):

We will choose a more standard value of ±15 volts for our power supply voltages. The complete schematic of our voltage follower circuit is shown in Figure 2.17.

Now let us check to be sure the 741 can supply the required current to our load without causing an appreciable voltage loss in our output. When the output voltage reaches its maximum level, the load current can be computed with Ohm’s Law as

This should have negligible effect on the output voltage of the op amp because the 741 can supply significantly higher currents.

Figure 2.17 also illustrates the use of a compensating resistor R_B. Recall from the previous amplifier designs that bias current in the op amp can cause output offsets because of the voltage drops across any resistances in line with the bias current. We minimize this offset by providing equal resistances in both (+) and (−) inputs. The resistance in the (+) input is simply the source resistance that was given as 1.8 kilohms. To minimize output errors, we insert an equal value R_B in the feedback loop. Note that no significant signal current flows through R_B. Therefore, the voltage gain is unaffected by the addition of R_B, and it remains constant at unity.

The actual performance of our voltage follower circuit is shown in Figure 2.18 through the use of an oscilloscope plot. The measured performance is compared to the design goals in Table 2.3.

1. Voltage gain of each input signal

2. Input impedance of each input signal

3. Input current requirement for each input signal

4. Maximum output voltage swing (total)

5. Maximum input voltage swing (individual)

6. Output impedance

7. Output current capability

8. Bandwidth

9. Slew-rate limiting frequency

Voltage Gain.

The voltage gain for each input signal in Figure 2.20 must be computed separately. Each gain, however, is computed in the same manner, Equation (2.6), as a simple inverting amplifier circuit. That is,

where the minus sign is used to remind us of the phase inversion given to each signal.

The individual voltage gains for the circuit in Figure 2.20 are computed:

Observe that each of these calculations is similar to our analysis on a single-input inverting amplifier and that the gains are independent of each other.

Input Impedance.

The input impedance seen by each input is equal to the value of the input resistor on that particular input. That is, since each input resistor connects to a virtual ground point, its respective source sees it as the total input impedance. No calculations are required to determine the input impedance; we simply inspect the input resistors’ individual values.

Input Current Requirement.

Each source must supply the current for its own input. The amount of current can be determined by Ohm’s Law and is simply the input voltage divided by the input resistance, Equation (2.8). For the circuit shown in Figure 2.20, we can compute the following values:

In the case of V₁, a variable DC source, we computed the worst-case input current by using the maximum input voltage (3 volts). Similarly, for the alternating voltage sources v₂ and v₃, we used peak values of input voltage. In each of these cases, the source must be capable of supplying the required current.

Maximum Output Voltage Swing.

The output voltage of the summing amplifier is limited by the ±V_SAT values. For the purposes of this analysis, we will estimate the values of ±V_SAT to be 2 volts below the DC power supply values. The calculations, Equation (2.10), to determine the maximum output voltage swing are

As with previous circuits, we can utilize the data sheet supplied by the manufacturer if it becomes necessary to have a more accurate, or perhaps worst-case, value.

Maximum Input Voltage Swing.

The maximum input voltage swing of an amplifier is the voltage that causes the amplifier’s output to reach saturation. Input voltages that exceed this limit will produce distorted (i.e., clipped) output signals. In the case of the summing amplifier, the situation is more complex than with previous, single-input amplifiers. That is, the instantaneous level of output is determined by the instantaneous values of input voltage on all inputs. First we will consider each input separately to determine the maximum levels of an isolated input. The calculations, from Equation (2.1), are similar to those used with previous circuits.

where A_V is the voltage gain received by a particular input. The individual calculations are

Note that the negative and positive saturation limits were used as the maximum output “swing” for V₁ and V₄, respectively, since these two inputs are DC and will only be limited by one saturation barrier.

With reference to v₂ and v₃, we may want to express them in their peak and RMS forms to better compare them with the signals shown in Figure 2.20. These conversions are

Since the maximum limits on all inputs (both DC and AC) are greater than the values listed on the schematic, we will assume that no single input can cause the amplifier output to saturate. However, two or more input signals may combine at some instant to drive the output to its saturation limit. Let us determine if this situation can occur in the circuit shown in Figure 2.20. To perform this calculation, we want to determine the worst-case combination of input signals. First observe that V₁ and V₄ are of opposite polarity and thus tend to reduce each other’s effect in the output. A worst case would be when V₁ is zero or when V₁ is maximum (3 volts DC). Let us evaluate them with Equation (2.1) to determine the worst-case combination.

From these calculations we can see that if V₁ were reduced to zero, V₄ would produce +1.7 volts in the output. On the other hand, if V₁ were set for maximum (3 volts DC), the net output voltage would be the difference between the V₁-produced and V₄-produced outputs. This worst-case output voltage is simply -7.8 + 1.7, or -6.1 volts.

Now we must consider the effects of the AC signals v₂ and v₃. The worst-case output condition will occur when these two inputs hit their peak values simultaneously and have the same polarity as V₁. The output voltages produced individually by v₂ and v₃ are

The net effect of V₁, v₂, v₃, and V₄ can be found by adding the individual output values (Superposition Theorem).

Since this worst-case value is less than our maximum output voltage limit (±13 volts typically), we should not have a problem. In extreme cases, however, we may have a potential problem. Recall that the output limits of ±13 volts were obtained by using typical performance values for the 741. If worst-case values are used, we will find that the limits fall to ±10 volts under worst-case conditions. If this situation were to occur at the same time our inputs were all at their maximum values, we would drive the amplifier into saturation and produce a clipped output. If this is a serious concern for our particular application, we can reduce R_F slightly to prevent the combined signals from driving the output to saturation.

Output Impedance.

The output impedance of the summing amplifier can be estimated as follows:

(2.34)

where A_OL is the open-loop gain of the op amp at the specified frequency and Y is computed as follows:

(2.35)

Now let us compute the output impedance for the circuit in Figure 2.20. First we compute the value of the parallel combination of input resistors (R_X):

Then we use this value to compute the factor Y, Equation (2.35):

Next we determine the value of A_OL at the frequency of interest, using Equation (2.16). We will use the worst-case value that occurs at the highest input frequency (10 kilohertz):

Finally we compute the estimated value of output resistance, from Equation (2.35):

Since this value was computed at the highest input frequency (worst case), and since it is very low compared to the value of the load resistor, its effects on output voltage can be safely ignored.

Output Current Capability.

The maximum value of load current occurs when the output reaches its highest instantaneous value. The maximum voltage was previously computed as 12.2 volts. The worst-case load current can be computed with Ohm’s Law:

The output of the op amp must also supply the feedback current. In most applications, this current can be ignored because it is generally much smaller than the load current. Our present circuit is no exception. That is, we can see by inspection that the feedback path has over 10 times as much resistance as the load.

The data sheet in Appendix 1 indicates that even under worst-case conditions, the output can maintain at least 10 volts across a 2000-ohm load. By Ohm’s Law, we can conclude that this corresponds to an output current of

Of course, the typical value of current is even higher. In any case, the current capability of the output clearly exceeds our requirements and therefore poses no problem. If our load resistor were smaller, we could anticipate a reduced output voltage.

Bandwidth.

For a meaningful discussion on bandwidth, we must consider the response of each input individually. When the responses are considered separately, we can estimate the bandwidth of any given input by applying the bandwidth equation, Equation (2.22), used in previous analyses:

We know from earlier calculations that the bandwidth will decrease as the closed-loop gain is increased. Let us calculate the bandwidth for the input in Figure 2.20 that has the highest gain. We have already determined the individual gains to be 2.6, 10, 2.1, and 1.7 for inputs V₁ through V₄. We will compute the bandwidth for the v₂ input because its gain is the highest. Incidentally, there would be very little point in computing the bandwidth for inputs V₁ and V₄ because these have DC signals applied. The bandwidth for the v₂ input is

A similar analysis could be made for input v₃, which has a computed gain of 2.1 and a maximum input frequency of 10 kilohertz. For large amplitude output signals, the slew rate will tend to restrict the operation to even lower frequencies. This is discussed in the following section.

Slew-Rate Limiting Frequency.

As discussed for previous amplifier configurations, the slew rate also limits the highest operating frequency for larger output voltage excursions. The slew-rate limiting frequency is found as follows, Equation (2.11):

Thus, although the v₂ input was shown to have a 90.9-kilohertz bandwidth as established by the unity gain frequency, the full-power upper limit is only 6.12 kilohertz. In the given application, however, the applied signal is only 5000 hertz, so this should not hamper the operation of the circuit with respect to the v₂ input.

The v₃ input, on the other hand, operates at 10 kilohertz. This means that we can never get the full 26-volt swing in the output as a result of v₃ signals. The schematic indicates that the highest input voltage is 1.2 volts RMS. The gain for v₃ was previously computed as 2.1. The largest normal output swing from v₃ can be found by applying Equation (2.1):

The actual slew-rate limiting frequency for this input is then estimated with Equation (2.11) as

In the given circuit, the slew rate should not interfere with the expected operation.

Input 1. 0 to 500 millivolts peak, at a frequency of 2.7 kilohertz. The source resistance is 1.0 kilohms, and the signal is to be amplified by a factor of −3.5.

Input 2. −2 to +2 volts DC. The source resistance is 0.75 ohms, and the voltage is to pass through the circuit without amplification (i.e., inversion only).

Input 3. 0 to 3 volts RMS, at a frequency of 500 hertz. The source resistance is 50 ohms, and the signal is to be amplified by a factor of −2.

Determine the Worst-Case Input.

Our initial step is to determine which input to design first. If we choose the wrong one, we will end up recalculating some of our values. The proper input can be identified by choosing the one that has the highest product of source resistance multiplied by voltage gain (absolute value). These calculations are shown for comparison:

Since input 1 has the highest gain-source-resistance product, we will begin by selecting the input resistor for input 1.

Choose the Value for the First Input Resistor.

The source resistance and the input resistor are in series. Their sum in conjunction with R_F will determine the voltage gain of that input. In theory, there is no requirement to have a physical resistor for R_I—the source resistance alone can serve as the input resistor. In practice, however, the source resistance is usually only an estimate and rarely a constant; therefore, it is generally wise to include a separate resistor as R_I and to make this resistor large enough to minimize the effects of changes in the source resistance. The application must dictate the degree of stability needed, but in general, if the input resistor is 10 times as large as the source resistance, then the effects of changes in the source resistance are reduced by about 90%. If greater protection is needed, increase R_I accordingly.

For purposes of our sample design, let us choose R_I1 to be 10 times the value of source resistance. The value of R_I1 then is computed as

Calculate the Required Feedback Resistor (R_F).

The feedback resistor is calculated by using a transposed version of the basic voltage gain equation, Equation (2.6), for an inverting amplifier.

In our particular circuit,

We choose the nearest standard (5% tolerance) value of 36 kilohms.

Compute the Remaining Input Resistors.

Values for each of the remaining input resistors can be calculated by using yet another transposed version of the basic voltage gain equation, Equation (2.6).

Using this equation, we can now compute values for R_I2 and R_I3 as follows:

and

Compute the Value of R_B.

To minimize the effects of op amp bias currents, we want to make the value of R_B equal to the parallel combination of R_F and all of the input/source resistors.

(2.36)

In our present case, the value of R_B is computed as

We select the nearest standard value of 5.1 kilohms.

Determine the Required Power Supply Voltages.

The DC power supply voltages must be high enough to prevent saturation under the worst-case input conditions. Generally, the condition to be considered is when all inputs are at the maximum voltage at the same time. The worst-case output voltage, then, is computed by adding the output voltages caused by each of the individual inputs, as in Equation (2.1).

The worst-case output will be

Unless the internal drop on the output of the selected op amp is unusually high, we should be able to use standard ±15-volt supplies. Suppose, for example, we decide to use a 741 op amp. The manufacturer’s data sheet in Appendix 1 indicates that the op amp can deliver at least ±12 volts to a load ≥10 kilohms when ±15-volt supplies are used. We will plan to use a 741 unless we encounter problems with bandwidth or slew rate (verified in subsequent sections).

Determine the Required Unity Gain Frequency.

The minimum unity gain frequency for each input is computed with Equation (2.22):

In all cases, the required minimum unity gain bandwidth is substantially below the 1.0-megahertz limit of a 741. Therefore, we will initially plan to use a 741 in our design. If the minimum bandwidth requirement were greater than 1.0 megahertz, we would have to select a different op amp.

Determine the Required Slew Rate.

The minimum acceptable slew rate for the op amp is given by the following equation, Equation (2.11):

Let us determine the minimum slew rate for each input:

In all cases, the required slew rate is substantially below the 0.5-volts-per-microsecond rating of the 741. Therefore, we will select this device as our final choice.

The schematic of our design is shown in Figure 2.21. The actual performance of the circuit is evident from the oscilloscope displays in Figure 2.22. The measured performance is contrasted with the original design goals in Table 2.4.

Voltage Gain.

The voltage gain of the circuit in Figure 2.25 can be computed with the noninverting amplifier gain formula given in Equation (2.28).

Output Voltage.

The output voltage of the circuit in Figure 2.25 can be determined by utilizing the basic gain equation of Equation (2.1):

Therefore,

1. Voltage gain

2. Input impedance

3. Bandwidth

Voltage Gain.

We will compute the overall voltage gain of the inverting circuit, Figure 2.27(a), by considering the gain to be made up of two parts. The first part of the gain is determined by all components to the left of C_O. The second part of the overall gain is determined by C_O and R_L. This latter part is actually a loss and tends to reduce the overall gain. Once these individual gains are computed, multiply them together to determine the overall voltage gain.

The voltage gain of the circuit to the left of C_O is computed in basically the same way, Equation (2.6), as a direct-coupled inverting amplifier. That is,

(2.37)

The only modification to our original equation is that the denominator must also include the effects of C_I. Therefore, instead of dividing by R_I (as we did with the direct-coupled circuit), we simply divide by the net impedance of R_I and C_I (i.e., Z_I). You will recall from basic electronics that the net impedance of a series RC circuit is computed with the following equation:

where X_C is the capacitive reactance of C_I. We already know that the gain of an op amp varies with frequency, but now we have introduced an even more obvious frequency-sensitive factor (X_C). Thus, when we speak of voltage gain, we must refer to a specific frequency in order to have a meaningful discussion. In most cases, we are interested in the lowest input frequency because this is where the capacitors will have their greatest effect (i.e., gain will be the lowest).

For the portion of the circuit in Figure 2.27(a) left of C_O, we can compute the voltage gain as shown. First, we need to determine the capacitive reactance with our basic electronics formula for X_C.

For illustrative purposes, we will assume an input frequency of 800 hertz. The first step, then, is to calculate the reactance of C_I at the frequency of interest.

Now we can compute the impedance of R_I and C_I:

Substituting this into the voltage gain equation, Equation (2.37), we can compute the gain of the circuit to the left of C_O.

Recall that the minus sign indicates a phase inversion, but in no way implies a reduction in signal amplitude.

Our next step is to compute the effects of C_O and R_L. These two components form an RC voltage divider. You may apply your favorite circuit analysis method to determine the percentage of voltage that appears across R_L. This percentage is the effective “gain” of the RC-coupling circuit. For our purposes, we will use the following method, which is based on the resistive voltage divider formula:

(2.38)

where Z is the net impedance of C_O and R_L.

First we compute the reactance of C_O at the frequency of interest (800 hertz in this case):

Next we compute the net impedance of R_L and C_O:

Finally, substituting this value into Equation (2.38), we compute our gain as

That is to say, about 97% of the signal amplitude that appears at the output terminal of the op amp will be developed across R_L. The RC-coupling circuit appears to be working well at 800 hertz, since very little voltage is being lost across C_O.

The overall voltage gain for the circuit is found by multiplying these two gains as computed.

(2.39)

For our example, we compute overall voltage gain as

Notice that the method described for computing overall voltage gain does not include the effects of the variations in open-loop gain at different frequencies. Although this additional consideration could be included as with the direct-coupled amplifier, it is not normally necessary because our calculations are accomplished at the lowest input frequency. If you want to compute the gain at some relatively high frequency, then you should include the effects of reduced op amp internal gain.

Another point that you may wish to consider involves phase shift. In addition to the 180-degree phase shift provided by the op amp itself, the signal also receives a phase shift from the two RC networks. The preceding calculations compute only the amplitude of the signal. If the phase is also an important consideration, then the same basic equations still apply but you can express the values as complex numbers. The final answer, then, not only will include the magnitude of the gain as computed, but will also reveal the amount of phase shift given to the signal.

The voltage gain calculation for the noninverting circuit shown in Figure 2.27(b) is similar, but will be considered as three separate gains that are multiplied together to find the overall gain. The three individual gains are

The gains of the input and output RC circuits are computed in the same way that we computed the gain of the output RC circuit in Figure 2.27(a). Let us first calculate the input RC circuit gain. Our initial step is to compute the reactance of C_I at the lowest frequency (assumed to be 800 hertz).

Next we find the net impedance of R₁ and C_I.

Finally we compute the voltage gain (loss) of the RC network with Equation (2.38).

Similar calculations for the output RC network of Figure 2.27(b) can now be accomplished. First we find the reactance of C_O.

Next we compute the net impedance of R_L and C_O.

Finally, the effective voltage gain (loss) of the R_LC_O network can be computed, Equation (2.38).

The third portion of our overall gain calculation is the gain of the op amp circuit as determined by R_F and R_I. We compute this using the gain formula of Equation (2.28) presented for the direct coupled amplifier.

The effective overall gain at 800 hertz is found by multiplying the three individual gains, as in Equation (2.39).

As with the AC-coupled inverting amplifier, we have chosen to ignore the frequency-dependent effects of open-loop op amp gain. This is generally a reasonable approach because our calculations are performed at the lowest input frequencies, where the open-loop gain is the closest to its ideal value.

Input Impedance.

The input impedance for the AC-coupled inverting amplifier circuit shown in Figure 2.27(a) is equal to the net impedance of R_I and C_I. Recall that the (−) input of the op amp is a virtual ground point. The source, therefore, sees the input impedance offered by C_I and R_I. Because this is a frequency-dependent value, we must discuss input impedance at a particular frequency of interest. For purposes of our present discussion, let us compute the highest and lowest values for input impedance if the input frequency range is 800 hertz to 3 kilohertz. The following input impedance at 800 hertz is computed. First we find the reactance of C_I at 800 hertz.

Now we can compute the impedance of R_I and C_I.

The minimum value for input impedance occurs at the highest input frequency. In most cases, the input impedance approaches the value of R_I; however, the computations are similar to those as shown:

Now we can compute the impedance of R_I and C_I.

The input impedance for the AC-coupled noninverting amplifier circuit shown in Figure 2.27(b) is essentially equal to the impedance offered by R₁ and C_I. Technically, the input impedance of the (+) input terminal appears in parallel with R₁. We can generally ignore this impedance, however, since it is usually an extremely high value. For our present example, we begin by finding the reactance of C_I at the lowest input frequency.

Next we find the net impedance of R₁ and C_I.

The minimum value for input impedance occurs at the highest input frequency, as it did with the inverting circuit. In most cases, the input impedance approaches the value of R₁. The following computations, however, are shown:

Now we can compute the impedance of R₁ and C_I:

Bandwidth.

Bandwidth can be defined as that range of frequencies that pass through a circuit with a voltage amplitude of at least 70.7 percent of the maximum output voltage—in other words, the range of frequencies between the two half-power points. These two frequencies can be readily determined in at least three ways:

You may be able to employ all three of these methods. However, none of them are suitable for use in this reference book, so we will examine yet another, less direct approach. Let us begin by making some observations. First, since the op amp has a frequency response that extends all the way to DC, the lower cutoff frequency will be unaffected by the op amp. That is, the input and output RC circuits will determine the lower cutoff frequency. Second, in a practical circuit, the upper cutoff frequency will be determined by the op amp itself. The RC circuits act as high-pass filters and will not restrict the gain at the higher input frequencies.

Calculation of the upper cutoff frequency was discussed in previous sections. We estimate it with Equation (2.40).

(2.40)

In the case of Figure 2.27(a), our ideal upper cutoff frequency is computed as

Next we calculate the lower cutoff frequency, which is determined by the input and output RC networks. The cutoff frequency of each individual RC network is determined with the following equation:

(2.41)

The lower cutoff frequency for the entire circuit is determined by the ratio of the cutoff frequencies for the RC circuits.

Let us now compute the lower cutoff frequency for the circuit in Figure 2.27(a). First we compute the individual cutoff frequencies for the two RC networks. The input circuit calculations, as in Equation (2.41), are

A similar computation, Equation (2.41), for the output RC circuit is

Computing the ratio of the two cutoff frequencies (using the higher frequency as the numerator) gives us the index needed for the lookup operation in Table 2.5.

(2.42)

For our particular case, the index is computed as

Finally, we use the lookup table shown in Table 2.5 to get our multiplying factor k. In this case, the value of k is about 1.32 (estimating the value between 1.34 and 1.306). The overall lower cutoff frequency can now be found by multiplying our factor k by the higher of the two individual cutoff frequencies.

(2.43)

Thus, the lower cutoff frequency for the circuit in Figure 2.27(a) is estimated as

The approximate bandwidth of the circuit in Figure 2.27(a) can now be expressed as Equation (2.5):

The bandwidth of the noninverting circuit shown in Figure 2.27(b) is computed in the same way that it was for the inverting circuit. First we estimate the upper cutoff frequency, which is determined by the behavior of the op amp, from Equation (2.22).

Next we compute the individual cutoff frequencies for the input and output RC circuits, as in Equation (2.41).

A similar computation for the output RC circuit is Equation (2.41):

Computing the ratio of the two cutoff frequencies (using the higher frequency as the numerator) gives us the index, from Equation (2.42), needed for the lookup operation in Table 2.5:

Using this value as the index into Table 2.5 gives us an approximate value of 1.33 for k. The lower cutoff frequency for the entire circuit in Figure 2.27(b) can now be estimated with Equation (2.43):

At this point, the bandwidth of the circuit can be estimated with Equation (2.5):

Slew-Rate Limitations.

The slew rate of the op amp will limit the upper cutoff frequency for high-amplitude output signals. The slew-rate limiting frequency is calculated in the same manner as described for previous amplifier configurations.

1. Design the basic amplifier circuit according to the guidelines presented for the direct-coupled inverting or noninverting amplifier circuits.

2. Compute the values for the input and output RC coupling components.

1. Midpoint voltage gain of 12

2. Lower cutoff frequency of 500 hertz

3. Upper cutoff frequency of at least 15 kilohertz

4. Input impedance of at least 3000 ohms

Determine the Value of R_I.

We will select R_I as 6.8 kilohms. Although this selection is somewhat arbitrary, we are keeping within the guidelines of choosing resistance between 1000 ohms and 680 kilohms. Additionally, the selection of R_I will have a major effect on the final input impedance, as R₁ will be close to the same value as R_I, and it is R₁ that determines the input impedance of the amplifier. Thus, in order to meet the requirements for an input impedance of at least 3000 ohms, we must choose a value for R_I that is larger than 3000 ohms.

Determine the Value of R_F.

R_F can be computed from the voltage gain equation shown in Equation (2.28):

For the present design example, we compute R_F as follows:

We select the nearest standard value of 75 kilohms to use as R_F.

Determine the Required Unity Gain Frequency.

We can compute the minimum unity gain frequency for our op amp with Equation (2.22):

where f_UG is the minimum required unity gain frequency for the op amp and bw is the highest operating frequency. Thus, we must select an op amp that has a minimum unity gain frequency of at least 180 kilohertz. Because the 741 has a 1.0-megahertz unity gain frequency, it should be fine for our purposes. Now let us determine the slew-rate requirement.

Determine the Required Slew Rate.

The minimum acceptable slew rate for the op amp is given by the following equation, Equation (2.11):

In our case, let us assume that we want to deliver a full output swing (±13 V) at the highest frequency (15 kHz). The minimum slew rate is computed as follows:

The 741 has a slew rate of 0.5 volts per microsecond, so it will not be adequate for this application. There are many alternatives, but let us choose the MC1741SC op amp (Appendix 4). It has a unity gain frequency similar to that of the 741, but it offers a slew rate of 10 volts per microsecond.

Select R₁.

R₁ is chosen to be the same value as the parallel combination of the feedback resistor (R_F) and the input resistor (R_I). This following value is computed:

We will use a standard value of 6.2 kilohms.

Compute the Value of C_I.

To simplify subsequent calculations, we will choose a value for C_I that produces a reactance that is much less than the resistance R₁. We will design for a reactance of one-tenth R₁, or 620 ohms in this case, at the lower cutoff frequency. The value for C_I is computed from the capacitive reactance equation.

In our present case,

We will select the next higher standard value of 0.56 microfarad.

Select the Value of R_L.

In many cases, R_L is the input resistance of a subsequent stage. In these cases, R_L is not selected; it is already defined by the nature of the problem. For our example design, we will choose R_L as 27 kilohms. This is sufficiently large to eliminate any concerns of output loading on the op amp, but it is low enough to facilitate coupling to a subsequent op amp circuit if needed.

Compute the Value of C_O.

By following the guidelines given for the selection of the R₁C_I combination, we have assured ourselves that the lower cutoff frequency will be primarily determined by the R_LC_O network. We use the fundamental formula for capacitive reactance to compute a value for C_O that produces a reactance equal to the value of R_L at the lower cutoff frequency (500 Hz).

The resulting circuit for our noninverting AC-coupled amplifier is shown in Figure 2.28. The actual performance of the circuit is reflected in the oscilloscope waveforms shown in Figure 2.29. The design goals are compared to the measured performance in Table 2.6.

1. Current gain

2. Load current

3. Range of acceptable input currents

4. Maximum load resistance

5. Input resistance

6. Output resistance

Current Gain.

The current gain (A_I) can be initially described with the basic gain equation, Equation (2.1):

Current i_L is composed of the two currents, i₁ and i_I. That is,

The voltage across R₁ is equal to the voltage across R₂ and is computed by Ohm’s Law as

The value of current (i₁) can also be computed by Ohm’s Law as

Substituting this into the equation for load current produces

Factoring i_I, gives us the equation for I_L:

(2.44)

In this form, it is easy to see that we do indeed have a current amplifier. That is, the input current (i_I) is multiplied by a constant (R₂/R₁ + 1) to produce the output or load current. The constant is the current gain of the circuit, shown below.

(2.45)

In the case of the circuit in Figure 2.30, the current gain is calculated as shown:

It is especially important to note that the value of load current is independent of the value of load resistor. That is, the op amp circuit is acting as a current source.

Although many current sources are essentially DC (e.g., transducers), there may be an application requiring current amplification at higher frequencies. As the frequency of operation is increased, the actual current gain will begin to decrease from the low frequency value calculated. This effect is caused by the reduction in open-loop op amp gain as the input frequency is increased. The higher the value of current gain (A_I), the more significant the effects of op amp voltage gain variations.

Load Current.

The input current (i_I) for the circuit in Figure 2.30 is indicated to be in the range of 10–50 microamps. The output current can be found by transposing the basic current gain equation, Equation (2.1).

In our case, the minimum load current is computed as

The highest load current is found in a similar manner as

Range of Acceptable Input Currents.

In order for the circuit in Figure 2.30 to operate as a current source whose value is proportional to input current, it is essential that the output voltage (v_O) be less than the saturation voltage in either polarity. This, then, is the factor that restricts the range of acceptable input currents. The output voltage can be expressed as a sum of two voltages by using Kirchhoff’s Voltage Law.

Substituting current and resistance values (i.e., V = IR) produces

To calculate the amount of input current needed to drive the output to saturation, we transpose this equation to find i_I and substitute the value of V_SAT for v_O. For our example, let us assume that the saturation voltage is determined from the manufacturer’s data sheet to be 13 volts. The maximum input current, then, is computed as

(2.46)

More specifically, for our present circuit we have

The lower range is computed in a similar manner by using the other saturation limit. In most cases (i.e., balanced dual power supply circuits), the values of ±V_SAT will be the same. If this were true for the circuit in Figure 2.30, we could have a range of input currents that extended from -57.3 microamps to +57.3 microamps—the polarity, of course, telling us the direction of current flow.

Maximum Load Resistance.

Another way to view the preceding calculations is to consider a known range of input currents and a variable value for R_L. Again, the output voltage must be kept from reaching the saturation limits. We can transpose Equation (2.46) for i_I(maximum) to get the following result:

where i_I is the highest expected input current. In the case of Figure 2.30, we can determine the maximum value for the load resistance as

Input Resistance.

Although the input resistance of the circuit in Figure 2.30 is ideally 0, there may be applications that require us to know a more accurate value for it. The following equation can be used to estimate the input resistance of the current amplifier in Figure 2.30:

(2.47)

where R_X is the resistance of R₁ and R₂ in parallel (i.e., R₁R₂/(R₁ + R₂)) and A_V is the open-loop gain of the op amp at a particular frequency.

In the case of Figure 2.30, let us compute the input resistance for DC conditions. First, the open-loop gain at DC can be found in the data sheet (Appendix 1) to be at least 50,000. The value for R_X is calculated as

The input resistance can now be calculated, Equation (2.47), as shown:

As you might expect, the input resistance approaches the ideal value (to be driven by a current source) of 0 ohms.

If the input frequency is higher than DC, the input resistance will deviate more from the ideal value of 0. For example, if our input frequency were raised to 1 kilohertz, the input resistance would increase to about 226 ohms. Additionally, we would need to consider the effects of bandwidth and slew rate limitations.

Output Resistance.

The output resistance of the circuit in Figure 2.30 as viewed by the load resistor is ideally infinite, as the circuit acts like a current source. A more accurate value for the output resistance can be computed with the following equation:

(2.48)

where A_V is the open-loop voltage gain of the op amp at a particular frequency and R_X is the value of R₁ and R₂ in parallel. In the case of Figure 2.30, let us estimate the output resistance at DC:

As evidenced in the equation, this value becomes less ideal as the frequency of operation is increased.

1. Input current range

2. Output current range

3. Current gain

4. Load resistance

1. Output current of 10 milliamps (constant)

2. Input current of 500 microamps

3. Load resistance of < 500 ohms

4. Available power supply of ±15 volts

5. 741 op amp used if practical

Compute the Required Current Gain.

The required current gain of our circuit can be computed with the basic current gain equation, Equation (2.1):

Determine the Maximum Value for R₂.

The maximum value for R₂ can be found by applying a transposed version of the equation we used for computing the maximum value for R_L:

We will select a standard value less than this–for purposes of our design, a 12-kilohm resistor for R₂. Notice that we use the worst-case value of 12 volts as the saturation voltage for the op amp.

Compute the Value of R₁.

R₁ can be computed by applying a transposed version of the current gain equation, Equation (2.45).

We will select the nearest standard value of 620 ohms. If it is essential to have a precise value of load current, then we put a variable resistance in series with R₂.

The schematic of our completed design is shown in Figure 2.31. The load resistor has been replaced with a zener diode to illustrate a possible application. By forcing the zener current to be a known value, we can measure the zener voltage and compute the zener resistance. As long as the effective zener resistance is below our established limit for R_L, the circuit will work fine. The measured performance of the circuit is contrasted with the design goals in Table 2.7.

1. Input voltage of 1.0 volt RMS

2. Input resistance > 10 kilohms

3. Input frequency range between 10 hertz and 2.0 kilohertz

4. Load resistance of 50 ohms

5. ±15-volt supplies to be used

6. 741 op amp to be used if practical

Select the Output Transistor.

There are basically five transistor parameters that must be reviewed to select a transistor:

In some cases, the frequency characteristics of the transistor must be evaluated, but in most cases the transistor performance exceeds that of the op amp and can be ignored.

In our case, we need an emitter-collector breakdown voltage greater than 15 volts. The exact collector current will be computed later, but we need to estimate a worst-case value so that we can select the transistor. For this purpose, we can assume that the entire +15 volts of the supply are felt across the 50-ohm load. Ohm’s Law tells us the value of load current.

The actual collector current will be less than this, but this is a good value to use for initial transistor selection.

Now we need to determine the required current gain (β) of the transistor. In data sheets, this is generally labeled as h_FE. We can again make a rough estimate for purposes of transistor selection. If we divide the load current computed above by half of the short-circuit output current of the op amp, we will have a good place to start. The following computation gives us the minimum value of β that our transistor should have.

(2.53)

The short-circuit current for a 741 is listed as 20 milliamps, and so in the present case we have

The power dissipation of the transistor can be estimated with the following equation:

(2.54)

where V_CC is the positive supply voltage. For the present case, the estimated power dissipation of the transistor is

By scanning a transistor data book (selector guides in particular), a transistor that satisfies the above requirements can be found. For illustration purposes, let us select a 2N3440 transistor. The data sheet for this common device is presented as Appendix 9. Its critical parameters follow:

These values exceed our rough, worst-case requirements. Now let us extend our estimate to include the determination of a heat sink (see Appendix 10 for a more complete discussion). We will assume that 50°C will be the highest expected ambient temperature. The required thermal resistance (θ_JA) can be estimated as follows:

Since the required value of θ_JA is greater than the transistor’s θ_JC, this transistor can be used for this application. However, since the required value of thermal resistance (θ_JA) is less than the θ_JA for the transistor, a heat sink will be needed to ensure safe operation. The required thermal resistance (θ_SA) of the heat sink can be estimated as follows:

Note that the case-to-sink thermal resistance (θ_CS) was estimated as 2°C/W. Since the required thermal resistance is only slightly lower than the transistor’s own thermal rating, it should be easy to find or make a satisfactory heat sink. There are many transistor/heat sink combinations that are adequate for a given application. Final selection must include cost and availability considerations.

Determine the Maximum Output Voltage of the Op Amp.

The maximum op amp output voltage is simply V_SAT. Appendix 1 lists the data sheet for a 741. The worst-case saturation voltage is listed as 10 volts for resistive loads of 2 to 10 kilohms. If the load on the op amp is over 10 kilohms, the saturation voltage is listed as 12 volts minimum. The load as seen by our op amp is computed by applying a basic transistor equation, Equation (2.49).

Thus, the maximum available voltage at the output of the op amp will be considered to be 10 volts. In practice, it will likely be higher.

Determine the Minimum Output Voltage of the Op Amp.

The lower limit on op amp output voltage is determined by the V_BE value of the transistor. The worst-case value for the 2N3440A is given as 1.3 volts. Thus, our op amp output voltage can swing as low as 1.3 volts without fear of clipping.

Determine the Required Bias Voltage at the Output.

The output of the op amp should be biased halfway between its two limits (V_SAT and V_BE). This is computed as shown using Equation (2.52):

Determine the Maximum AC Swing at the Output.

The output of the op amp is centered at the bias level and can swing between V_SAT and V_BE. The RMS value of output voltage is computed as

(2.55)

For the present circuit, we have

Compute the Required Voltage Gain.

The required voltage gain of the amplifier circuit is determined by applying the basic voltage gain equation, Equation (2.1).

Note that the negative value simply indicates an inversion.

Determine the Value of R_I.

The value of the input resistor is chosen to establish the required input resistance of the circuit. In our case, anything greater than 10 kilohms should suffice. Let us choose a standard value of 18 kilohms.

Calculate the Value of R_F.

R_F is calculated with the inverting amplifier gain equation, Equation (2.6).

We will select a standard value of 56 kilohms.

Determine the Required Unity Gain Frequency.

The required unity gain frequency is computed in a manner similar to that in previous discussions, using Equation (2.22).

Select a Value for R_P.

The value of the potentiometer R_P is essentially arbitrary. As it is made smaller, its power rating requirement becomes higher, and the current draw from the supply becomes greater. If R_P is made excessively large, then the effects of bias currents that flow through R_P are more pronounced. As a guideline, select R_P to be approximately equal to R_F/10, but consider 1.0 kilohm to be the minimum practical value. In our case, we have

Compute the Value of R_B.

The optimum value for R_B varies as the wiper arm of R_P is moved. However, the preceding method for selecting R_P reduces this dependency. We will compute the value of R_B needed when the wiper arm of R_P is at midpoint. R_B is computed as shown.

(2.56)

In our case, we compute R_B as

We will choose a standard value of 51 kΩ.

Compute the Value of C_I.

The purpose of the input coupling capacitor is to isolate the DC levels between the signal source and the (−) pin on the op amp. It should be selected to have a reactance of less than one-tenth of R_I at the lowest input frequency (10 hertz in this case). The calculations are

We will choose a standard value of 10 microfarad.

Bandwidth and Slew Rate Considerations.

Since our application requires only modest performance, neither slew rate nor bandwidth limitations should pose problems. If the application were more demanding, these restrictions would have to be considered. The methods described for previous amplifier circuits can be utilized to evaluate the effects of bandwidth and slew rate limitations.

The schematic of our completed design is shown in Figure 2.34. Actual performance of the circuit is indicated by the oscilloscope display shown in Figure 2.35.

1. Observation

2. Signal injection/tracing

3. Voltage measurements

4. Resistance measurements

Observation.

This is probably the most important step in the process if done effectively. Observation means more than just looking at the circuit. It includes all of the following actions:

Many problems can be identified during the observation stage. How many of us have “successfully” traced a malfunction throughout a complex circuit until we located a suspected switch or variable resistor on the schematic? Then, when we physically locate the suspected component on the system, it turns out to be a front panel control! Had we applied the preceding procedure faithfully, we could have reduced our efforts dramatically.

Signal Injection/Tracing.

All electronic circuits can be diagnosed to some extent by signal injection, signal tracing, or a combination of the two methods. The underlying goal for this process is to reduce the number of possible culprits down from a set consisting of every component in the system to a smaller set consisting of only a few components.

Signal injection requires us to inject a known, good signal at some point in the circuit and observe the effects. If the circuits that utilize this signal then appear to operate normally, we can infer that the malfunction is located ahead of our injection point. We then move our injection point closer to the source of the trouble and inject another signal. Again, the behavior of the subsequent circuits will provide guidance as to our next injection point. Two common types of test equipment for signal injection are signal generators and logic pulsers.

Signal tracing is similar in concept, except we put a known good signal at the input and verify (trace) its presence throughout the circuit. If we lose the signal (or it becomes distorted) at a certain point, then we can infer that the trouble lies ahead of the monitored point. The oscilloscope and logic probe are two common types of signal tracing equipment.

Both signal tracing and signal injection can be enhanced by using the split-half method of troubleshooting. By selecting your injection or monitor point to be approximately halfway through the suspected range of components, each measurement effectively reduces the number of possible components by half.

Voltage Measurements.

Voltage measurements normally occur after you have isolated the problem down to a particular stage consisting of up to perhaps 10 components. The voltage checks contrasted with normal values should result in the narrowing of suspects down to one or two possibilities. Distinction between the signal tracing and voltage measuring phases often becomes blurred when an oscilloscope is used. The concept remains valid, however.

Resistance Measurements.

Resistance checks are performed last because accurate measurements often require desoldering of a component. Desoldering not only is time consuming but also risks damage to an expensive printed circuit board in many cases. The resistance checks are done to verify that you have in fact located the defective component. Component testers can also be used at this point if available and appropriate.

1. Verify the power supply voltage on the op amp.

2. Measure output voltage.

3. Measure differential input voltage (v_D).

4. Compare the results of steps 2 and 3. If the results violate basic theory (e.g., noninverting input is more positive than inverting input, but output is negative), then the op amp is probably bad. If no basic theory principles are violated, check the following: