Contents

Preface

Acknowledgments

1 Overview

1.1 Introduction

1.2 Fueling the Innovation: Moore’s Law

1.3 Digital Systems

1.4 Examples of Digital Systems

1.5 Components of the Digital Design Process

1.6 Competing Objectives in Digital Design

1.7 Synchronous Digital Hardware Systems

1.8 Design Strategies

References

2 Using a Hardware Description Language

2.1 Overview

2.2 About Verilog

2.3 System Design Flow

2.4 Logic Synthesis

2.5 Using the Verilog HDL

2.6 Four Levels of Abstraction

2.7 Verification in Hardware Design

2.8 Example of a Verification Setup

2.9 SystemVerilog

Exercises

References

3 System Design Flow and Fixed-point Arithmetic

3.1 Overview

3.2 System Design Flow

3.3 Representation of Numbers

3.4 Floating-point Format

3.5 Qn.m Format for Fixed-point Arithmetic

3.6 Floating-point to Fixed-point Conversion

3.7 Block Floating-point Format

3.8 Forms of Digital Filter

Exercises

References

4 Mapping on Fully Dedicated Architecture

4.1 Introduction

4.2 Discrete Real-time Systems

4.3 Synchronous Digital Hardware Systems

4.4 Kahn Process Networks

4.5 Methods of Representing DSP Systems

4.6 Performance Measures

4.7 Fully Dedicated Architecture

4.8 DFG to HW Synthesis

Exercises

References

5 Design Options for Basic Building Blocks

5.1 Introduction

5.2 Embedded Processors and Arithmetic Units in FPGAs

5.3 Instantiation of Embedded Blocks

5.4 Basic Building Blocks: Introduction

5.5 Adders

5.6 Barrel Shifter

5.7 Carry Save Adders and Compressors

5.8 Parallel Multipliers

5.9 Two’s Complement Signed Multiplier

5.10 Compression Trees for Multi-operand Addition

5.11 Algorithm Transformations for CSA

Exercises

References

6 Multiplier-less Multiplication by Constants

6.1 Introduction

6.2 Canonic Signed Digit Representation

6.3 Minimum Signed Digit Representation

6.4 Multiplication by a Constant in a Signal Processing Algorithm

6.5 Optimized DFG Transformation

6.6 Fully Dedicated Architecture for Direct-form FIR Filter

6.7 Complexity Reduction

6.8 Distributed Arithmetic

6.9 FFT Architecture using FIR Filter Structure

Exercises

References

7 Pipelining, Retiming, Look-head Transformation and Polyphase Decomposition

7.1 Introduction

7.2 Pipelining and Retiming

7.3 Digital Design of Feedback Systems

7.4 C-slow Retiming

7.5 Look-ahead Transformation for IIR filters

7.6 Look-ahead Transformation for Generalized IIR Filters

7.7 Polyphase Structure for Decimation and Interpolation Applications

7.8 IIR Filter for Decimation and Interpolation

Exercises

References

8 Unfolding and Folding of Architectures

8.1 Introduction

8.2 Unfolding

8.3 Sampling Rate Considerations

8.4 Unfolding Techniques

8.5 Folding Techniques

8.6 Mathematical Transformation for Folding

8.7 Algorithmic Transformation

Exercise

References

9 Designs based on Finite State Machines

9.1 Introduction

9.2 Examples of Time-shared Architecture Design

9.3 Sequencing and Control

9.4 Algorithmic State Machine Representation

9.5 FSM Optimization for Low Power and Area

9.6 Designing for Testability

9.7 Methods for Reducing Power Dissipation

Exercises

References

10 Micro-programmed State Machines

10.1 Introduction

10.2 Micro-programmed Controller

10.3 Counter-based State Machines

10.4 Subroutine Support

10.5 Nested Subroutine Support

10.6 Nested Loop Support

10.7 Examples

Exercises

References

11 Micro-programmed Adaptive Filtering Applications

11.1 Introduction

11.2 Adaptive Filter Configurations

11.3 Adaptive Algorithms

11.4 Channel Equalizer using NLMS

11.5 Echo Canceller

11.6 Adaptive Algorithms with Micro-programmed State Machines

Exercises

References

12 CORDIC-based DDFS Architectures

12.1 Introduction

12.2 Direct Digital Frequency Synthesizer

12.3 Design of a Basic DDFS

12.4 The CORDIC Algorithm

12.5 Hardware Mapping of Modified CORDIC Algorithm

Exercises

References

13 Digital Design of Communication Systems

13.1 Introduction

13.2 Top-level Design Options

13.3 Typical Digital Communication System

Exercises

References

Index