Figure 2.1 A first (and not very useful) circuit. 7

Figure 2.2 The ideal op amp. 10

Figure 2.3 The noninverting op amp. 10

Figure 2.4 The inverting op amp. 11

Figure 2.5 The adder circuit. 12

Figure 2.6 The differential amplifier. 13

Figure 2.7 Differential amplifier with common-mode input signal. 14

Figure 2.8 T network in feedback loop. 14

Figure 2.9 Thevenin's theorem applied to T network. 15

Figure 2.10 Impedance matching amplifier. 16

Figure 2.11 Low-pass filter. 17

Figure 2.12 High-pass filter. 17

Figure 3.1 Split-supply inverting gain op amp circuit. 21

Figure 3.2 Single-supply op amp inverting gain circuit. 22

Figure 3.3 Single-supply op amp inverting gain circuit with internal DC operating point. 23

Figure 3.4 Single-supply op amp inverting gain circuit with external DC operating point. 24

Figure 3.5 Incorrect voltage reference buffering. 25

Figure 3.6 Correct voltage reference buffering. 25

Figure 3.7 Incorrect noninverting single-supply stage. 26

Figure 3.8 Another incorrect noninverting single-supply stage. 27

Figure 4.1 A simple transducer interface example. 32

Figure 4.2 Split-supply op amp circuit with common-mode voltage. 32

Figure 4.3 Inverting op amp with DC offset. 34

Figure 4.4 Inverting op amp with V_CC bias. 35

Figure 4.5 Transfer curve for inverting op amp with V_CC bias. 36

Figure 4.6 Noninverting op amp. 36

Figure 4.7 Transfer curve for noninverting op amp. 37

Figure 4.8 Schematic for Case 1: V_OUT = +mV_IN + b. 40

Figure 4.9 Case 1 example circuit. 42

Figure 4.10 Case 1 example circuit measured transfer curve. 43

Figure 4.11 Schematic for Case 2: V_OUT = +mV_IN − b. 44

Figure 4.12 Case 2 example circuit. 45

Figure 4.13 Case 2 example circuit measured transfer curve. 46

Figure 4.14 Schematic for Case 3: V_OUT = −mV_IN + b. 46

Figure 4.15 Case 3 example circuit. 48

Figure 4.16 Case 3 example circuit measured transfer curve. 48

Figure 4.17 Schematic for Case 4: V_OUT = −mV_IN − b. 49

Figure 4.18 Case 4 example circuit. 50

Figure 4.19 Case 4 example circuit measured transfer curve. 51

Figure 5.1 Noninverting attenuator. 54

Figure 5.2 Noninverting attenuation with positive offset. 55

Figure 5.3 Noninverting attenuation with negative offset. 55

Figure 5.4 Inverting attenuation with zero offset. 56

Figure 5.5 Noninverting attenuation with positive offset. 56

Figure 5.6 Noninverting attenuation with negative offset. 57

Figure 5.7 Inverting unity gain buffer. 57

Figure 6.1 Definition of blocks. (A) Input/output impedance (B) signal flow arrows (C) block multiplication (D) blocks perform functions as indicated. 60

Figure 6.2 Summary points. (A) Additive summary point (B) subtractive summary point (C) multiple input summary points. 61

Figure 6.3 Definition of control system terms. 61

Figure 6.4 Definition of an electronic feedback circuit. 61

Figure 6.5 Multiloop feedback system. 62

Figure 6.6 Block diagram transforms. 63

Figure 6.7 Comparison of control and electronic canonical feedback systems. (A) Control system terminology (B) electronics terminology (C) feedback loop is broken to calculate the loop gain. 64

Figure 6.8 Low-pass filter. 66

Figure 6.9 Bode plot of low-pass filter transfer function. 66

Figure 6.10 Band reject filter. 67

Figure 6.11 Individual pole zero plot of band reject filter. 67

Figure 6.12 Combined pole zero plot of band reject filter. 68

Figure 6.13 The ideal op amp Bode plot, when no pole exists in Eq. (6.12). 69

Figure 6.14 When Eq. (6.12) has a single pole. 70

Figure 6.15 Magnitude and phase plot of Eq. (6.14). 72

Figure 6.16 Magnitude and phase plot of the loop gain increased to (K + C). 73

Figure 6.17 Magnitude and phase plot of the loop gain with pole spacing reduced. 73

Figure 6.18 Phase margin and overshoot versus damping ratio. 75

Figure 7.1 Feedback system block diagram. 79

Figure 7.2 Feedback loop broken to calculate loop gain. 80

Figure 7.3 Noninverting op amp. 81

Figure 7.4 Open-loop noninverting op amp. 82

Figure 7.5 Inverting op amp. 82

Figure 7.6 Inverting op amp: feedback loop broken for loop gain calculation. 83

Figure 7.7 Differential amplifier circuit. 84

Figure 7.8 Bode response of a typical op amp. 85

Figure 7.9 Bode response representation of safe operating region. 87

Figure 8.1 Miller effect compensation. 90

Figure 8.2 TL03X frequency- and time-response plots. 91

Figure 8.3 Phase margin and percent overshoot versus damping ratio. 92

Figure 8.4 TL07X frequency- and time-response plots. 93

Figure 8.5 TL08X frequency- and time-response plots. 93

Figure 8.6 TLV277X frequency-response plots. 94

Figure 8.7 TLV227X time-response plots. 94

Figure 8.8 Capacitively loaded op amp. 96

Figure 8.9 Capacitively loaded op amp with loop broken for loop gain (Aβ) calculation. 96

Figure 8.10 Possible Bode plot of the op amp described in Eq. (8.7). 98

Figure 8.11 Dominant-pole compensation plot. 98

Figure 8.12 Gain compensation. 100

Figure 8.13 Lead-compensation circuit. 100

Figure 8.14 Lead-compensation Bode plot. 101

Figure 8.15 Inverting op amp with lead compensation. 102

Figure 8.16 Noninverting op amp with lead compensation. 103

Figure 8.17 Op amp with stray capacitance on the inverting input. 103

Figure 8.18 Compensated attenuator circuit. 104

Figure 8.19 Compensated attenuator bode plot. 105

Figure 8.20 Lead-lag compensated op amp. 106

Figure 8.21 Bode plot of lead-lag compensated op amp. 106

Figure 8.22 Closed-loop plot of lead-lag compensated op amp. 107

Figure 9.1 Current-feedback amplifier model. 110

Figure 9.2 Stability analysis circuit. 111

Figure 9.3 Stability analysis circuit. 111

Figure 9.4 Noninverting current-feedback amplifier. 112

Figure 9.5 Inverting current-feedback amplifier. 114

Figure 9.6 Bode plot of stability equation. 116

Figure 9.7 Plot of current-feedback amplifier R_F, G, and BW. 118

Figure 9.8 Effects of stray capacitance on current-feedback amplifiers. 120

Figure 9.9 Bode plot with C_F. 121

Figure 10.1 Long-tailed pair. 124

Figure 10.2 Ideal current-feedback amplifier. 125

Figure 10.3 Voltage-feedback amplifier gain versus frequency. 126

Figure 10.4 Current-feedback amplifier gain versus frequency. 127

Figure 11.1 Single-ended op amp schematic symbol. 133

Figure 11.2 Fully differential op amp schematic symbol. 134

Figure 11.3 Closing the loop on a single-ended op amp. 135

Figure 11.4 Closing the loop on a fully differential op amp. 135

Figure 11.5 Single ended to differential conversion. 136

Figure 11.6 Relationship between V_IN, V_OUT+, and V_OUT−. 137

Figure 11.7 Electrical model of V_ocm. 138

Figure 11.8 Mechanical model of V_ocm. 138

Figure 11.9 A mechanical fully differential amplifier. 138

Figure 11.10 Using a fully differential op amp to drive a analog-to-digital converter 139

Figure 11.11 Instrumentation amplifier. 140

Figure 11.12 Single-pole differential low-pass filter. 141

Figure 11.13 Single-pole differential high-pass filter. 141

Figure 11.14 Differential low-pass filter. 142

Figure 11.15 Differential high-pass filter. 142

Figure 11.16 Differential speech filter. 143

Figure 11.17 Differential speech filter response. 143

Figure 11.18 Differential biquad filter. 144

Figure 12.1 Undercompensated op amp. 145

Figure 12.2 Instrumentation amplifier. 146

Figure 12.3 High-precision differential amplifier. 147

Figure 12.4 Difference amplifier. 148

Figure 12.5 High side current monitor. 149

Figure 12.6 Commercial difference amplifier. 150

Figure 12.7 A better way to use a buffer amplifier. 151

Figure 12.8 Paralleling buffer amplifiers. 152

Figure 13.1 Simple method to isolate coaxial cable capacitance. 156

Figure 13.2 50 Ω transmission method. 157

Figure 13.3 50 Ω transmission method, with DC blocking capacitor. 157

Figure 13.4 Simple method to reject RF 158

Figure 13.5 Typical op amp input stage. 159

Figure 13.6 External slew rate reduction capacitor. 160

Figure 13.7 Power supply rejection ratio. 161

Figure 13.8 Decoupling technique to reduce PSRR. 162

Figure 13.9 Op amp package with offset null pins. 163

Figure 13.10 One possible offset null correction. 163

Figure 13.11 Method to balance input bias current. 164

Figure 13.12 Noninverting gain circuit with input bias current balancing. 165

Figure 13.13 Noninverting gain circuit with low DC offset. 165

Figure 14.1 Focusing on the power supply characteristics. 169

Figure 14.2 Focusing on the input signal. 170

Figure 14.3 Focusing on the analog to digital converter. 171

Figure 14.4 Focusing on the operational amplifiers. 172

Figure 14.5 Single-ended to fully differential AC coupled interface. 174

Figure 14.6 Preferred single-ended to fully differential AC coupled interface. 174

Figure 15.1 Resistor ladder D/A converter. 178

Figure 15.2 Binary weighted D/A converter. 179

Figure 15.3 R/2R resistor array. 180

Figure 15.4 R/2R D/A converter. 181

Figure 15.5 Sigma delta D/A converter. 182

Figure 15.6 Total harmonic distortion. 185

Figure 15.7 D/A offset error. 187

Figure 15.8 D/A gain error. 188

Figure 15.9 Differential nonlinearity error. 189

Figure 15.10 Integral nonlinearity error. 189

Figure 15.11 Spurious-free dynamic range. 191

Figure 15.12 Intermodulation distortion. 191

Figure 15.13 D/A settling time. 192

Figure 15.14 D/A deglitch circuit. 193

Figure 15.15 Compensating for CMOS DAC output capacitance. 193

Figure 15.16 D/A output current booster. 195

Figure 15.17 Incorrect method of increasing voltage swing of D/A converters. 196

Figure 15.18 Correct method of increasing voltage range. 197

Figure 15.19 Single-supply DAC operation. 198

Figure 16.1 Second-order passive low-pass and second-order active low-pass. 200

Figure 16.2 First-order passive RC low-pass. 200

Figure 16.3 Fourth-order passive RC low-pass with decoupling amplifiers. 201

Figure 16.4 Frequency and phase responses of a fourth-order passive RC low-pass filter. 202

Figure 16.5 Amplitude responses of Butterworth low-pass filters. 204

Figure 16.6 Gain responses of Tschebyscheff low-pass filters. 205

Figure 16.7 Comparison of phase responses of fourth-order low-pass filters. 206

Figure 16.8 Comparison of normalized group delay (t_gr) of fourth-order low-pass filters. 206

Figure 16.9 Comparison of gain responses of fourth-order low-pass filters. 207

Figure 16.10 Graphical presentation of quality factor Q on a 10th-order Tschebyscheff low-pass filter. 208

Figure 16.11 Cascading filter stages for higher-order filters. 209

Figure 16.12 First-order noninverting low-pass filter. 210

Figure 16.13 First-order inverting low-pass filter. 210

Figure 16.14 First-order noninverting low-pass filter with unity gain. 211

Figure 16.15 General Sallen–Key low-pass filter. 212

Figure 16.16 Unity-gain Sallen–Key low-pass filter. 212

Figure 16.17 Second-order unity-gain Tschebyscheff low-pass with 3 dB ripple. 214

Figure 16.18 Adjustable second-order low-pass filter. 214

Figure 16.19 Second-order multiple feedback low-pass filter. 215

Figure 16.20 First-order unity-gain low-pass. 217

Figure 16.21 Second-order unity-gain Sallen–Key low-pass filter. 217

Figure 16.22 Fifth-order unity-gain Butterworth low-pass filter. 218

Figure 16.23 Low-pass to high-pass transition through components exchange. 219

Figure 16.24 Developing the gain response of a high-pass filter. 219

Figure 16.25 First-order noninverting high-pass filter. 220

Figure 16.26 First-order inverting high-pass filter. 220

Figure 16.27 General Sallen–Key high-pass filter. 221

Figure 16.28 Unity-gain Sallen–Key high-pass filter. 222

Figure 16.29 Second-order multiple feedback high-pass filter. 223

Figure 16.30 Third-order unity-gain Bessel high-pass. 225

Figure 16.31 Low-pass to band-pass transition. 225

Figure 16.32 Gain response of a second-order band-pass filter. 227

Figure 16.33 Sallen–Key band-pass. 228

Figure 16.34 Multiple feedback band-pass. 229

Figure 16.35 Gain responses of a fourth-order Butterworth band-pass and its partial filters. 233

Figure 16.36 Low-pass to band-rejection transition. 234

Figure 16.37 Passive Twin-T filter. 235

Figure 16.38 Active Twin-T filter. 235

Figure 16.39 Passive Wien-Robinson bridge. 236

Figure 16.40 Active Wien-Robinson filter. 237

Figure 16.41 Comparison of Q between passive and active band-rejection filters. 238

Figure 16.42 Frequency response of the group delay for the first 10 filter orders. 240

Figure 16.43 First-order all-pass. 241

Figure 16.44 Second-order all-pass filter. 242

Figure 16.45 Seventh-order all-pass filter. 244

Figure 16.46 Dual-supply filter circuit. 244

Figure 16.47 Single-supply filter circuit. 245

Figure 16.48 Biasing a Sallen–Key low-pass. 245

Figure 16.49 Biasing a second-order multiple feedback low-pass filter. 246

Figure 16.50 Biasing a Sallen–Key and a multiple feedback high-pass filter. 247

Figure 16.51 Differences in Q and f_C in the partial filters of an eighth-order Butterworth low-pass filter. 248

Figure 16.52 Modification of the intended Butterworth response to a Tschebyscheff-type characteristic. 248

Figure 16.53 Open-loop gain (A_OL) and filter response (A). 250

Figure 17.1 Low-pass response—go to Section 17.3.1. 260

Figure 17.2 High-pass response—go to Section 17.3.2. 261

Figure 17.3 Narrow (single-frequency) band pass—go to Section 17.3.4. 261

Figure 17.4 Wide band pass—go to Section 17.3.5. 261

Figure 17.5 Notch filter—single frequency—go to Section 17.3.5. 262

Figure 17.6 Low-pass filter. 262

Figure 17.7 High-pass filter. 263

Figure 17.8 Narrow band-pass filter. 263

Figure 17.9 Wide band-pass filter. 264

Figure 17.10 Notch filter. 265

Figure 17.11 Variable frequency notch filter. 266

Figure 17.12 Three-pole low-pass filter. 267

Figure 17.13 Three-pole high-pass filter. 268

Figure 17.14 Twin-T band-pass filter response. 269

Figure 17.15 Modified Twin-T topology. 269

Figure 17.16 Two Twin-T networks inside the feedback loop. 270

Figure 17.17 Stagger-tuned filter response. 271

Figure 17.18 Multiple-peak band-pass filter. 272

Figure 17.19 Single-amplifier Twin-T notch filter. 273

Figure 17.20 Twin-T band reject filter. 274

Figure 17.21 Single-amplifier Twin-T notch and band-pass filter. 275

Figure 17.22 Universal filter schematic. 276

Figure 17.23 Universal filter calculator. 276

Figure 17.24 Universal filter board. 277

Figure 17.25 Notch filter calculator. 278

Figure 17.26 Notch filter PCB. 278

Figure 17.27 Twin-T filter calculator. 279

Figure 17.28 Twin-T PC board. 280

Figure 18.1 Open-loop response. 281

Figure 18.2 Band-pass response. 283

Figure 18.3 Notch filter response for 1 MHz center frequency. 284

Figure 18.4 Notch filter response for 100 kHz center frequency. 285

Figure 18.5 Notch filter response for 10 kHz center frequency. 285

Figure 18.6 Amplitude modulation reception with and without notch filter. 286

Figure 18.7 Effect of heterodyning and the notch filter. 287

Figure 19.1 A traditional RF stage. 290

Figure 19.2 Noninverting RF op amp gain stage. 291

Figure 19.3 Frequency response peaking. 293

Figure 19.4 Noise bandwidth. 295

Figure 19.5 Typical GSM cellular base station receiver block diagram. 296

Figure 19.6 Broadband RF IF amplifier. 297

Figure 19.7 Wideband response. 297

Figure 19.8 IF amplifier response. 300

Figure 19.9 Single-ended to differential output drive circuit. 301

Figure 20.1 Rail-to-rail output stage. 304

Figure 20.2 Input circuit of a non rail-to-rail input op amp. 306

Figure 20.3 Input circuit of a rail-to-rail input op amp. 306

Figure 20.4 Input offset voltage and bias current changes with input common-mode voltage. 307

Figure 22.1 Voltage regulator operation. 323

Figure 22.2 Switching regulator. 325

Figure 22.3 Overvoltage protection circuit. 327

Figure 22.4 Active load. 329

Figure 22.5 Voltage regulator calculator. 330

Figure 23.1 Voltage regulator operation. 334

Figure 23.2 Negative output utilizing a parasitic winding. 336

Figure 23.3 Negative output utilizing a parasitic winding. 337

Figure 23.4 Negative output by referencing the regulator to −V_OUT instead of ground. 338

Figure 23.5 Negative active load. 339

Figure 24.1 Oscillator schematics. 341

Figure 24.2 Oscillator outputs. 342

Figure 24.3 Comparator oscillator analysis. 343

Figure 24.4 Composite op amp. 344

Figure 24.5 Composite op amp. 345

Figure 24.6 Paralleling output op amps. 345

Figure 25.1 Op amp attenuator done wrong. 347

Figure 25.2 Op amp attenuator done correctly. 348

Figure 25.3 Inverting op amp attenuator. 348

Figure 25.4 Similar schematic symbols, but very different parts! 349

Figure 25.5 Example op amp schematic. 350

Figure 25.6 Example comparator schematic. 350

Figure 25.7 Different ways of dealing with unused op amp sections. 352

Figure 25.8 Unexpected DC gain. 354

Figure 25.9 Current source. 354

Figure 25.10 Current feedback amplifier incorrectly applied. 355

Figure 25.11 Voltage-feedback versus current-feedback amplifier stability versus load resistor. 356

Figure 25.12 Capacitor in feedback loop. 356

Figure 25.13 Terminating a fully differential amplifier. 357

Figure 25.14 Using an input stage. 358

Figure 25.15 Incorrect DC operating point. 358

Figure 25.16 Correct DC operating point. 359

Figure 25.17 Common-mode error. 360

Figure 25.18 The effects of V_OCM on outputs. 360