There are many types of low-power embedded systems, and different systems can have different low-power requirements. Typically, we can summarize these requirements into the categories outlined in Table 11.1.

In practice, most low-power embedded products will have to consider more than one of these low-power factors. For example, some of the embedded systems operate continuously and can be switched off completely when not in use. In this case, the low operating power would be the most important factor, whereas some systems might need to be in standby mode most of the time and only wake up to execute a program for a short period. In such a case, the low standby power would be the more critical requirement, especially if the battery life of the product is important.

As embedded products are getting more and more complex, the computation capability of the processor is becoming more important. Nowadays a lot of embedded systems are interrupt driven (Figure 11.1); when there is no interrupt request, no data processing is required and the processor can enter sleep mode. When a peripheral requires servicing, it generates an interrupt request and wakes up the processor. The processor then handles the required processing and returns to sleep. The better processing capability the processor has, the more time it can stay in sleep mode and hence improve battery life.

If you are using a slow processor for an interrupt-driven system, the interrupt service routine could take a lot longer to run and increase the duty cycles of the system. But if you are using a very powerful processor, despite being able to reduce the duty cycles, you might end up with much more operating power and standby power, which will increase power consumption. Depending on the data processing requirements, different applications require different processors for the optimum balance between performance and power (Figure 11.2).

For this reason, there are different types of ARM processors for different application requirements. The ARM processors are designed with low-power embedded systems in mind. Different ARM processors are optimized for different groups of applications based on processing requirements. The Cortex-M0 processor is developed to target small embedded systems with ultra-low-power requirements and mixed-signal applications, where the processor design complexity is limited by various constraints in mixed-signal semiconductor technologies.

So how does the Cortex-M0 processor satisfy the ultra-low-power requirements in an embedded application?

First, the design of the Cortex-M0 processor is very small. For a minimum implementation, the design is only 12K gates. It is smaller than many 16-bit processors and much smaller than other 32-bit processors on the market. This reduces both operating power and static power (caused by the leakage current of transistors).

Second, the design of the Cortex-M0 processor utilizes many low-power design techniques to reduce the operating power consumption. ARM has more than 20 years of low-power processor design experience. The design of the Cortex-M0 has been extensively reviewed to ensure that the low-power design measures are utilized for lowest power consumption. This allows the operating power of the processor to be reduced.

Even with a tiny footprint, the Cortex-M0 is still able to deliver a performance that is much higher than 8-bit and 16-bit systems that have the same clock rate. The Cortex-M0 processor also has the best in class energy efficiency in the 32-bit processor market because of its small size and low power consumption.

The high code density of the Cortex-M processors also lower power by reducing the size of the flash memory required. In modern microcontroller designs, the majority of the silicon area is occupied by flash memory, SRAM, and peripherals. With traditional 8-bit microcontroller architectures, the lack of flexible addressing modes, the heavy use of accumulator registers, and limited data paths often result in large program code (Figure 11.3). By switching to Cortex-M0 or other Cortex-M processors, the program size can be greatly reduced and hence you can use a microcontroller with a smaller flash to save power and cost.

In addition, when comparing the Cortex-M0 microcontroller products to 8-bit and 16-bit microcontroller products, the Cortex-M0 offers much higher performance. As a result, an embedded developer can reduce power consumption by taking the following steps:

Either way, or by combining both approaches, the energy efficiency characteristics of the Cortex-M0 processor allow longer battery life in portable products compared with 8-bit and 16-bit microcontrollers. Besides extending battery life, the low-power capability of the Cortex-M0 processor also:

A number of low-power features are available in the Cortex-M0 processor. In addition, microcontroller vendors usually also implement a number of low-power modes in their Cortex-M0 microcontroller products. This chapter focuses mostly on the low-power features provided by the Cortex-M0 processor. Details for microcontroller specific low-power features are usually available in user manuals or application notes available from the microcontroller vendor web sites or in example software packages.

In general the Cortex-M0 processor includes the following low-power features:

In addition, various characteristics of the Cortex-M0 also help reduce power consumption:

Because the processor is only a small part of a microcontroller, to get the best energy efficiency and maximum battery life out of a microcontroller product, it is necessary to understand not only the processor but also the rest of the microcontroller. Most microcontroller vendors provide application note and software libraries to make this easier.

Most microcontrollers support at least one type of sleep mode to allow the power consumption to be reduced when no processing is required. In the Cortex-M0 processor, sleep mode support is included as part of the processor architecture.

The Cortex-M0 processor has two sleep modes:

The exact meaning and behaviors of these sleep modes depends on the implementation of the microcontroller. Microcontroller vendors can use various power-saving measures to reduce the power of the microcontroller during sleep. They can also further extend the sleep modes by adding extra power control capability. Typically, the following methods are used to reduce power during sleep:

The sleep modes can be entered by three different methods:

Whether the normal sleep mode or the deep sleep mode will be used is determined by a control bit called SLEEPDEEP. This bit is located in the System Control Register (SCR) of the System Control Block (SCB) region, which contains the control bits for the low-power features of the Cortex-M0 processor. Users of CMSIS-compliant device drivers can access to the System Control Register using the register name “SCB->SCR” (Table 11.2).

Different sleep modes and different sleep operation types can result in various combinations, as shown in Figure 11.4.

There are two instructions that can cause the Cortex-M0 processor to enter sleep: WFE and WFI (Table 11.3). The WFE can be awakened by interrupt requests as well as events, whereas WFI can be awakened by interrupt requests or debug requests only.

One of the low-power features of the Cortex-M0 processor is the Sleep-on-Exit. When this feature is enabled, the processor automatically enters a Wait-for-Interrupt sleep mode when exiting an exception handler and if no other exception is waiting to be processed.

This feature is useful for applications where the processor activities are interrupt driven. For example, the software flow could be like the flowchart in Figure 11.9.

The resulting activities of the processor are illustrated in Figure 11.10.

The Sleep-on-Exit feature reduces the active cycles of the processor and reduces the energy consumed by the stacking and unstacking of processes between the interrupts. Each time the processor finishes an interrupt service routine and enters sleep, it does not have to carry out the unstacking process because it knows that these registers will have to be stacked again when another interrupt request arrives next time.

The Sleep-on-Exit feature is controlled by the SLEEPONEXIT bit in the System Control Register. Setting this bit in an interrupt-driven application is usually carried out as the last step of the initialization process. Otherwise, if an interrupt occurs during this stage, the processor might enter sleep during the initialization of the processor.

Designers of the Cortex-M0 microcontroller can optionally include a Wakeup Interrupt Controller (WIC) in their design. The WIC is a small interrupt detection logic that mirrors the interrupt masking function in the NVIC. The WIC allows the power consumption of the processor to be further reduced by stopping all the clock signals to the processor, or even putting the processor into a retention state. When an interrupt is detected, the WIC sends a request to a power management unit (PMU) in the microcontroller to restore power and clock signals to the processor, and then the processor can wake up and process the interrupt request.

The WIC itself does not contain any programmable registers; it has an interface that couples to the Cortex-M0 NVIC, and the interrupt mask information is transferred from the processor to the WIC automatically during sleep. The WIC is activated only in deep sleep mode (SLEEPDEEP bit is set), and you might also need to program additional control registers in the power management unit in the microcontroller to enable the WIC deep sleep mode.

The WIC enables the Cortex-M0 processor to reduce standby power consumption using a technology called State Retention Power Gating (SRPG). With SRPG, the leakage power of a sequential digital system during sleep can be minimized by powering off most parts of the logic, leaving a small memory element in each flip-flop to retain the current state. This is shown in Figure 11.11.

When working with the WIC, a Cortex-M0 processor implemented with SRPG technology can be powered down during deep sleep to minimize the leakage current of the microcontroller. During WIC mode deep sleep, the interrupt detection operation is handed over to the WIC (Figure 11.12). Because the state of the processor is retained in the flip-flops, the processor can wake up and resume operations almost immediately. In practice, the use of SRPG power down can increase the interrupt latency slightly, depending on how long it takes for the voltage on the processor to be stabilized after the power-up sequence.

Not all Cortex-M0 microcontrollers support the WIC feature. The reduction of power using the WIC depends on the application and the semiconductor process being used. When the WIC mode deep sleep is used, the SysTick timer is stopped and you might need to set up a separate peripheral timer to wake up the processor periodically if your application requires an embedded OS and needs the OS to operate continuously. Also, when developing simple applications without any embedded OS and if WIC mode deep sleep is required, use a peripheral timer for periodic interrupt generation instead of the SysTick timer.