In this chapter we will look into the memory architecture of the Cortex-M0 processor and how it affects software development.

The Cortex-M0 processor has a 32-bit system bus interface with 32-bit address lines (4 GB of address space). The system bus is based on a bus protocol called AHB-Lite (Advanced High-performance Bus), which is a protocol defined in the Advanced Microcontroller Bus Architecture (AMBA) standard. The AMBA standard is developed by ARM, and is widely used in the semiconductor industry.

Although the AHB-Lite protocol provides high-performance accesses to the memory system, very often a secondary bus segment can also be found for slower devices including peripherals. In ARM microcontrollers, the peripheral bus system is normally based on the Advanced Peripheral Bus (APB) protocol. The APB is connected to the AHB-Lite via a bus bridge and may run at a different clock speed compared to the AHB system bus. The data path on the APB is also 32-bit, but the address lines are often less than 32-bit as the peripheral address space is relatively small (Figure 7.1).

Because of the separation of main system bus and peripheral bus, and in some cases with separated clock frequency controls, an application might need to initialize some clock control hardware in the microcontroller before accessing the peripherals. In some cases, there can be multiple peripheral bus segments in a microcontroller running at different clock frequencies. Besides allowing some part of the system to run at a slower speed, the separation of bus segments also provides the possibility of power reduction by allowing the clock to a peripheral system to be stopped.

Depending on the microcontroller design, some high-speed peripherals might be connected to the AHB-Lite system bus instead of the APB. This is because the AHB-Lite protocol requires fewer clock cycles for each transfer when compared to the APB. The bus protocol behavior affects the system operation and the programmer’s view on the memory system in a number of ways. This subject will be covered in various places in this chapter.

The 4GB memory space of the Cortex-M0 processor is architecturally divided into a number of regions (Figure 7.2). Each region has its recommended usage, and the memory access behavior could depend on which memory region you are accessing to. This memory region definition helps software porting between different ARM Cortex microcontrollers, as they all have similar arrangements.

Despite having an architecturally defined memory map, the actual usage of the memory map is very flexible. There are only a few limitations—for example, a few memory regions that are allocated for peripherals do not allow program code execution, and a number of internal components have a fixed memory address to ensure software portability.

Next we will look into the usage of each region.

Although the Cortex-M0 processor has this fixed memory map, the memory usage is very flexible. For example, it can have multiple SRAM memory blocks placed in the SRAM region as well as the CODE region, and it can execute program code from external memory components located in RAM region. Microcontroller vendors can also add their own system-level memory features, such as system-level cache, if needed.

So how does the memory map of a typical real system look like? For a typical microcontroller developed with the Cortex-M0 processor, normally you can find the following elements:

After putting all these components together, an example microcontroller could be illustrated as shown in Figure 7.3.

Figure 7.3 shows how some memory regions can be used. However, in many low-cost microcontrollers, the system designs do not have any external memory interface or Secure Digital (SD) card interface. In these cases, some of the memory regions, like the external RAM or the external device regions, might not be used.

Usually the program memory of the Cortex-M0 is implemented with on chip flash memory. However, it is also possible that the program is stored externally or using other types of memory devices (e.g. EEPROM).

When the Cortex-M0 processor comes out of reset, it accesses the vector table in address zero for initial MSP value and reset vector value, and it then starts the program execution from the reset vector. To ensure that the system works correctly, a valid vector table and a valid program memory must be available in the system to prevent the processor from executing rogue program code.

Usually this is done by a flash memory starting from address zero. However, an off-the-shelf microcontroller product might not have any program in the flash memory before the user programs it. To allow the processor to start up correctly, some Cortex-M0 based microcontrollers come with a boot loader, a small program located on the microcontroller chip that executes after the processor powers up and branches to the user application in the flash memory only if the flash is programmed. The boot loader is preprogrammed by the chip manufacturer. Sometimes it is stored on the on-chip flash memory with a separate memory section from user applications (to allow the user to update the program without affecting the boot loader); other times is it stored on a nonvolatile memory that is separate from the user programmable flash memory (to prevent the users from accidentally erasing the boot loader).

When a boot loader is present, it is common for the microcontroller vendor to implement a memory map-switching feature called “remap” on the system bus. The switching of the memory map is controlled by a hardware register, which is programmed when the boot loader is executed. There are various types of remap arrangements. One common remap arrangement is to allow the boot loader to be mapped to the start of the memory during the power-up phase using address alias, as shown in Figure 7.4.

The boot loader might also support additional features like hardware initialization (clock and PLL setup), supporting of multiple boot configurations, firmware protection, or even flash erase utilities. The memory remap feature is implemented on the system bus and is not a part of the Cortex-M0 processor, therefore different microcontrollers from different vendors have different implementations.

Another common type of remap feature implemented on some ARM microcontrollers allows an SRAM block to be remapped to address 0x0 (Figure 7.5). Normally nonvolatile memory used on microcontrollers like flash memory is slower than SRAM. When the microcontroller is running at a high clock rate, wait states would be required if the program is executed from the flash memory. By allowing an SRAM memory block to be remapped to address 0x0, then the program can be copied to SRAM and executed at maximum speed. This also avoids wait states in vector table fetch, which affects interrupt latency.

The data memory in Cortex-M0 processor is used for software variables, stack memory, and, in some cases, heap memory. Sometimes local variables in C functions could be stored onto the stack memory. The heap memory is needed when the applications use C functions that require dynamically allocated memory space.

In most embedded applications without operating systems (OSs), only one stack is used (only the main stack pointer is required). In this case, the data memory can be arranged as shown in (Figure 7.6).

Because the stack operation is based on a full descending stack arrangement, and heap memory allocation is ascending, it is common to put the stack at the end of the memory block and heap memory just after normal memory to get the most efficient arrangement.

For embedded applications with embedded OS, each task might have its own stack memory range (see Figure 4.15 from Chapter 4). It is also possible for each task to have its own allocated memory block, with each memory block containing a memory layout consisting of stack, heap, and data.

The Cortex-M0 processor supports either the little endian or big endian memory format (Figure 7.7 and Figure 7.8). The microcontroller vendor makes the choice when the system is designed, and embedded programmers cannot change it. Software developers must configure their development tools project options to match the endianness of the targeted microcontroller.

The big endian mode supported on the Cortex-M0 processor is called the Byte-Invariant big endian mode, or “BE8.” It is one of the big endian modes in ARM architectures. Traditional ARM processors, like ARM7TDMI, use a different big endian mode called the Word-Invariant big endian mode, or “BE32.” The difference between the two is on the hardware interface level and does not affect the programmer’s view.

Most of the Cortex-M0 processor–based microcontrollers are using the little endian configuration. With the little endian arrangement, the lowest byte of a word-size data is stored in bit 0 to bit 7 (Figure 7.7).

In the big endian configuration, the lowest byte of a word-size data is stored in bit 24 to bit 31 (Figure 7.8)

Both memory configurations support data handling of different sizes. The Cortex-M0 processor can generate byte, half-word, and word transfers. When the memory is accessed, the memory interface selects the data lanes base on the transfer size and the lowest two bits of the address. Figure 7.9 illustrates the data access for little endian systems.

Similarly, a big endian system supports data access of different sizes (Figure 7.10).

Note that there are two exceptions in big endian configurations: (1) the instruction fetch is always in little endian, and (2) the accesses to Private Peripheral Bus (PPB) address space is always in little endian.

The Cortex-M0 processor can be used with wide range of memory systems and devices. To make porting of software between different devices easier, a number of memory attribute settings are available for each region in the memory map. Memory attributes are characteristics of the memory accesses; they can affect data and instruction accesses to memory as well as accesses to peripherals.

In the ARMv6-M architecture, which is used by the Cortex-M0 processor, a number of memory access attributes are defined for different memory regions:

For most users of the Cortex-M0 products, only the XN attribute is relevant because it defines which regions can be used for program execution. The other attributes are used only if cache unit or multiple processors are used. Because the Cortex-M0 processor does not have an internal cache unit, in most cases these memory attributes are not used. If a system-level cache is used or when the memory controller has a built-in cache, then these memory attributes, exported by the processor via the AHB interface, could be used.

Based on the memory attributes, various memory types are architecturally defined and are used to define what type of devices could be used in each memory region:

The memory attribute for each memory region in the Cortex-M0 processor is defined using these memory type definitions (Table 7.3). During the memory accesses, the memory attributes are exported from the processor to the AHB system.

The PPB memory region is defined as strongly ordered (SO). This means the memory region is nonbufferable and noncacheable. In the Cortex-M0, operations following an access to a strongly order region do not begin until the access has been completed. This behavior is important for changing registers in the System Control Space (SCS), where we often expect the operation of changing a control register to take place immediately, before next instruction is executed.

In some other ARM processors like the Cortex-M3, there can also be default memory access permission for each region. Because the Cortex-M0 processor does not have a separated privileged and nonprivileged (user) access level, the processor is in the privilege access level all the time and therefore does not have a memory map for default memory access permission.

In practice, most of the memory attributes and memory type definitions are unimportant (apart from the XN attribute) to users of Cortex-M0 microcontrollers. However, if the software code has to be reused on high-end processors, especially on systems with multiple processors and cache memories, these details can be important.