Appendix E. Debug Registers Quick Reference

Overview

The Cortex-M0 debug system contains a number of programmable registers. These registers can be accessed by an in-circuit debuggers only and cannot be accessed by the application software. This quick reference is intended for tools developers, or if you are using a debugger that supports debug scripts (e.g., RealView Debugger), you can use debug scripts to access to these registers to carry out testing operations automatically.
The debug system in the Cortex-M0 is partitioned into the following segments:
• Debug support in the processor core
• Breakpoint unit
• Data watchpoint unit
• ROM table.
System-on-chip developers can add debug support components if required. If additional debug components are added, another ROM table unit can also be added to the system so that a debugger can identify available debug components included in the system.
The debug support is configurable; some Cortex-M0 based products might not have any debug support.

Core Debug Registers

The processor core contains a number of registers for debug purpose.
AddressNameDescriptions
0xE000ED24SHCSRSystem Handler Control and State Register—indicate system exception status
0xE000ED30DFSRDebug Fault Status Register—allow debugger to determine the cause of halting
0xE000EDF0DHCSRDebug Halting Control and Status Register—control processor debug activities like halting, single stepping, restart
0xE000EDF4DCRSRDebug Core Register Selector Register—control read and write of core registers during halt
0xE000EDF8DCRDRDebug Core Register Data Register—data transfer register for reading or writing core registers during halt
0xE000EDFCDEMCRDebug Exception Monitor Control Register—for enabling of data watchpoint unit and vector catch feature; vector catch allows the debugger to halt the processor if the processor is reset or if a hard fault exception is triggered
0xE000EFD0 to 0xE000EFFCPIDs, CIDsID registers
System Handler Control and State Register (0xE000ED24)

BitsFieldTypeReset ValueDescriptions
31:16Reserved——Reserved
15SVCALLPENDEDRO0
1 indicates SVC execution is pended;
accessible from debugger only
14:0Reserved——Reserved
Debug Fault Status Register (0xE000ED30)

BitsFieldTypeReset ValueDescriptions
31:5Reserved——Reserved
4EXTERNALRWc0EDBGRQ was asserted
3VCATCHRWc0Vector catch occurred
2DWTTRAPRWc0Data watchpoint occurred
1BKPTRWc0Breakpoint occurred
0HALTEDRWc0Halted by debugger or single stepping
Debug Halting Control and Status Register (0xE000EDF0)

BitsFieldTypeReset ValueDescriptions
31:16DBGKEY (during write)WO—Debug Key. During write, the value of 0xA05F must be used on the top 16-bit. Otherwise the write is ignored.
25S_RESET_ST (during read)RO—Reset status flag (sticky). Core has been reset or being reset; this bit is clear on read.
24S_RETIRE_ST (during read)RO—Instruction is completed since last read; this bit is clear on reset.
19S_LOCKUPRO—When this bit is 1, the core is in lockup state.
18S_SLEEPRO—When this bit is 1, the core is sleeping.
17S_HALT (during read)RO—When this bit is 1, the core is halted.
16S_REGRDY_STRO—When this bit is 1, the core completed a register read or register write operation.
15:4Reserved——Reserved.
3C_MASKINTSR/W0Mask exceptions while stepping (does not affect NMI and hard fault); valid only if C_DEBUGEN is set.
2C_STEPR/W0Single step control. Set this to 1 to carry out single step operation; valid only if C_DEBUGEN is set.
1C_HALTR/W0Halt control. This bit is only valid when C_DEBUGEN is set.
0C_DEBUGENR/W0Debug enable. Set this bit to 1 to enable debug.
Debug Core Register Selector Register (0xE000EDF4)

BitsFieldTypeReset ValueDescriptions
31:17Reserved——Reserved
16REGWnRWO—
Set to 1 to write value to register
Set to 0 to read value from register
15:5Reserved——Reserved
4:0REGSELWO0Register select
Debug Core Register Data Register (0xE000EDF8)

BitsFieldTypeReset ValueDescriptions
31:0DBGTMPRW0Data value for the core register transfer
Debug Exception and Monitor Control Register (0xE000EDFC)

BitsFieldTypeReset ValueDescriptions
31:25Reserved——Reserved
24DWTENARW0Data watchpoint unit enable
23:11Reserved——Reserved
10VC_HARDERRRW0Debug trap at hard fault exception
9:1Reserved——Reserved
0VC_CORERESETRW0Halt processor after system reset and before the first instruction executed

Breakpoint Unit

The breakpoint unit contains up to four comparators for instruction breakpoints. Each comparator can produce a breakpoint for up to two instructions (if the two instructions are located in the same word address). Additional breakpoints can be implemented by inserting breakpoint instructions in the program image if the program memory can be modified.
The breakpoint unit design is configurable. Some microcontrollers might contain no breakpoint unit or a breakpoint unit with fewer than four comparators.
AddressNameDescriptions
0xE0002000BP_CTRLBreakpoint Control Register—for enabling the breakpoint unit and provide information about the breakpoint unit
0xE0002008BP_COMP0Breakpoint Comparator Register 0
0xE000200CBP_COMP1Breakpoint Comparator Register 1
0xE0002010BP_COMP2Breakpoint Comparator Register 2
0xE0002014BP_COMP3Breakpoint Comparator Register 3
0xE0002FD0 to 0xE0002FFCPIDs, CIDsID registers
Breakpoint Control Register (0xE0002000)

BitsFieldTypeReset ValueDescriptions
31:17Reserved——Reserved
7:4NUM_CODERO0 to 4Number of comparators
3:2Reserved——Reserved
1KEYWO—Write Key—when there is a write operation to this register, this bit should be set to 1, otherwise the write operation is ignored
0ENABLERW0Enable control
Breakpoint Comparator Registers (0xE0002008–0xE0002014)

BitsFieldTypeReset ValueDescriptions
31:30BP_MATCHRW—Breakpoint setting:
00: No breakpoint
01: Breakpoint at lower half word address
10: Breakpoint at upper half word address
11: Breakpoint at both lower and upper half word
29Reserved——Reserved
28:2COMPRW—Compare instruction address
1Reserved——Reserved
0ENABLERW0Enable control for this comparator

Data Watchpoint Unit

The data watchpoint unit has two main functions:
• Setting data watchpoints
• Providing a PC sampling register for basic profiling
Before accessing the DWT, the TRCENA bit in Debug Exception and Monitor Control Register (DEMCR, address 0xE000EDFC) must be set to 1 to enable the DWT. Unlike the Data Watchpoint and Trace unit in the Cortex-M3/M4, the DWT in the Cortex-M0 does not support trace. But the programming models of its registers are mostly compatible to the DWT in ARMv7-M.
The DWT design is configurable. Some microcontrollers might contain no DWT or a DWT with just 1 comparator.
AddressNameDescriptions
0xE0001000DWT_CTRLDWT Control Register—provide information about the data watchpoint unit
0xE000101CDWT_PCSRProgram Counter Sample Register—provide current program address
0xE0001020DWT_COMP0Comparator Register 0
0xE0001024DWT_MASK0Mask Register 0
0xE0001028DWT_FUNCTION0Function Register 0
0xE0001030DWT_COMP1Comparator Register 1
0xE0001034DWT_MASK1Mask Register 1
0xE0001038DWT_FUNCTION1Function Register 1
0xE0001FD0 to 0xE0001FFCPIDs, CIDsID registers
DWT Control Register (0xE0001000)

BitsFieldTypeReset ValueDescriptions
31:28NUMCOMPRO0 to 2Number of comparator implemented
27:0Reserved——Reserved
Program Counter Sample Register (0xE000101C)

BitsFieldTypeReset ValueDescriptions
31:0EIASAMPLERO—Execution instruction address sample; read as 0xFFFFFFFF if core is halted or if DWTENA is 0
DWT COMP0 Register and DWT COMP1 Registers (0xE0001020, 0xE0001030)

BitsFieldTypeReset ValueDescriptions
31:0COMPRW—Address value to compare to; the value must be aligned to the compare address range defined by the compare mask register
DWT MASK0 Register and DWT MASK1 Registers (0xE0001024, 0xE0001034)

BitsFieldTypeReset ValueDescriptions
31:4Reserved——Reserved
3:0MASKRW—Mask pattern:
0000: compare mask = 0xFFFFFFFF
0001: compare mask = 0xFFFFFFFE
…
1110: compare mask = 0xFFFFC000
1111: compare mask = 0xFFFF8000
DWT FUNC0 Register and DWT FUNC1 Registers (0xE0001028, 0xE0001038)

BitsFieldTypeReset ValueDescriptions
31:4Reserved——Reserved
3:0FUNCRW0Function:
0000: Disable
0100: Watchpoint on PC match
0101: Watchpoint on read address
0110: Watchpoint on write address
0111: Watchpoint on read or write address
Other values: Reserved

ROM Table Registers

The ROM table is used to allow a debugger to identify available components in the system. The lowest two bits of each entry are used to indicate if the debug component is present and if there is another valid entry following in the next address in the ROM table. The rest of the bits in the ROM table contain the address offset of the debug unit from the ROM table base address:
AddressValueNameDescriptions
0xE00FF0000xFFF0F003SCSPoints to System Control Space base address 0xE000E000
0xE00FF0040xFFF02003DWTPoints to DW base address 0xE0001000
0xE00FF0080xFFF03003BPUPoints to BPU base address 0xE0002000
0xE00FF00C0x00000000endEnd of table marker
0xE00FFFCC0x00000001MEMTYPEIndicates that system memory is accessible on this memory map
0xE00FFFD0 to 0xE00FFFFC0x000000--IDsPeripheral ID and component ID values (values dependent on the design versions)
Using the ROM table, the debugger can identify the debug components available as shown in Figure E.1.
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Figure E.1
The debugger can use the ROM table to detect available debug components automatically.
The ROM table lookup can be divided into multiple stages if a system-on-chip design contains additional debug components and an extra ROM table. In such cases, the ROM table lookup can be cascaded so that the debugger can identify all the debug components available (Figure E.2).
B9780123854773100278/app02-9780123854773.jpg is missing
Figure E.2
Multistage ROM table lookup when additional debug components are present.
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