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Part II
by David J. Kinniment
Synchronization and Arbitration in Digital Systems
Cover Page
Title Page
Copyright
Contents
Preface
List of Contributors
Acknowledgements
Chapter 1: Synchronization, Arbitration and Choice
1.1 INTRODUCTION
1.2 THE PROBLEM OF CHOICE
1.3 CHOICE IN ELECTRONICS
1.4 ARBITRATION
1.5 CONTINUOUS AND DISCRETE QUANTITIES
1.6 TIMING
1.7 BOOK STRUCTURE
Part I
Chapter 2: Modelling Metastability
2.1 THE SYNCHRONIZER
2.2 LATCH MODEL
2.3 FAILURE RATES
2.4 LATCHES AND FLIP-FLOPS
2.5 CLOCK BACK EDGE
Chapter 3: Circuits
3.1 LATCHES AND METASTABILITY FILTERS
3.2 EFFECTS OF FILTERING
3.3 THE JAMB LATCH
3.4 LOW COUPLING LATCH
3.5 THE Q-FLOP
3.6 THE MUTEX
3.7 ROBUST SYNCHRONIZER
3.8 THE TRI-FLOP
Chapter 4: Noise and its Effects
4.1 NOISE
4.2 EFFECT OF NOISE ON A SYNCHRONIZER
4.3 MALICIOUS INPUTS
Chapter 5: Metastability Measurements
5.1 CIRCUIT SIMULATION
5.2 SYNCHRONIZER FLIP-FLOP TESTING
5.3 RISING AND FALLING EDGES
5.4 DELAY-BASED MEASUREMENT
5.5 DEEP METASTABILITY
5.6 BACK EDGE MEASUREMENT
5.7 MEASURE AND SELECT
Chapter 6: Conclusions Part I
Part II
Chapter 7: Synchronizers in Systems
7.1 LATENCY AND THROUGHPUT
7.2 FIFO SYNCHRONIZER
7.3 AVOIDING SYNCHRONIZATION
7.4 PREDICTIVE SYNCHRONIZERS
7.5 OTHER LOW-LATENCY SYNCHRONIZERS
7.6 ASYNCHRONOUS COMMUNICATION MECHANISMS (ACM)
7.7 SOME COMMON SYNCHRONIZER DESIGN ISSUES
Chapter 8: Networks and Interconnects
8.1 COMMUNICATION ON CHIP
8.2 INTERCONNECT LINKS
8.3 SERIAL LINKS
8.4 DIFFERENTIAL SIGNALLING
8.5 PARALLEL LINKS
8.6 PARALLEL SERIAL LINKS
Chapter 9: Pausible and Stoppable Clocks in GALS
9.1 GALS CLOCK GENERATORS
9.2 CLOCK TREE DELAYS
9.3 A GALS WRAPPER
Chapter 10: Conclusions Part II
Part III
Chapter 11: Arbitration
11.1 INTRODUCTION
11.2 ARBITER DEFINITION
11.3 ARBITER APPLICATIONS, RESOURCE ALLOCATION POLICIES AND COMMON ARCHITECTURES
11.4 SIGNAL TRANSITION GRAPHS, OUR MAIN MODELLING LANGUAGE
Chapter 12: Simple Two-way Arbiters
12.1 BASIC CONCEPTS AND CONVENTIONS
12.2 SIMPLE ARBITRATION BETWEEN TWO ASYNCHRONOUS REQUESTS
12.3 SAMPLING THE LOGIC LEVEL OF AN ASYNCHRONOUS REQUEST
12.4 SUMMARY OF TWO-WAY ARBITERS
Chapter 13: Multi-way Arbiters
13.1 MULTI-WAY MUTEX USING A MESH
13.2 CASCADED TREE ARBITERS
13.3 RING-BASED ARBITERS
Chapter 14: Priority Arbiters
14.1 INTRODUCTION
14.2 PRIORITY DISCIPLINE
14.3 DAISY-CHAIN ARBITER
14.4 ORDERED ARBITER
14.5 CANONICAL STRUCTURE OF PRIORITY ARBITERS
14.6 STATIC PRIORITY ARBITER
14.7 DYNAMIC PRIORITY ARBITER
Chapter 15: Conclusions Part III
References
Index
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Chapter 6: Conclusions Part I
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Chapter 7: Synchronizers in Systems
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