The authors would like to acknowledge the many contributions of Charles E. Dike, Intel Corp, arising from collaborative work between Intel and Newcastle University, and supported by UK EPSRC research grant EP/C007298/1. The help of Ran Ginosar and Mark Greenstreet in discussing the issues, and at Cambridge and Newcastle Universities, Robert Mullins, Fei Xia, Enzo D'Alessandro and Jun Zhou in commenting on several of the chapters is also gratefully acknowledged.
Some of the material in this book has been based on work published in the following papers and is reproduced by permission of the IEEE:
Synchronization Circuit Performance, by D.J. Kinniment, A. Bystrov, and A.V. Yakovlev which appeared in IEEE Journal of Solid-State Circuits, 37(2), 202–209 © 2002 IEEE.
Analysis of the oscillation problem in tri-flops, by O. Maevsky, D.J. Kinniment, A. Yakovlev, and A. Bystrov which appeared in Proc. IS-CAS'02, Scottsdale, Arizona, May 2002, IEEE, volume I, pp 381–384 © 2002 IEEE.
Priority Arbiters, by A Bystrov, D.J. Kinniment, and A. Yakovlev which appeared in ASYNC'00, pp 128–137. IEEE CS Press, April 2000 © 2002 IEEE.
Measuring Deep Metastability, by D.J. Kinniment, K Heron, and G Russell which appeared in Proc. ASYNC'06, Grenoble, France, March 2006, pp 2–11 © 2006 IEEE.
A Robust Synchronizer Circuit, by J Zhou, D.J. Kinniment, G Russell, and A Yakovlev which appeared in Proc. ISVLSI'06, March 2006, pp 442–443 © 2006 IEEE.
Multiple-Rail Phase-Encoding for NoC, by C. D'Alessandro, D. Shang, A. Bystrov, A. Yakovlev, and O. Maevsky which appeared in Proc. ASYNC'06, Grenoble, France, March 2006, pp 107–116 © 2006 IEEE.
Demystifying Data-Driven and Pausible Clocking Schemes, by R Mullins and S Moore which appeared in Proc. 13th Intl. Symp. on Advanced Research in Asynchronous Circuits and Systems (ASYNC), 2007 pp 175–185 © 2007 IEEE.
Efficient Self-Timed Interfaces for crossing Clock Domains by Chakraborty and M. Greenstreet, which appeared in Proc. ASYNC2003, Vancouver, 12–16 May 2003, pp 78–88 © 2003 IEEE.
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