Contents

Preface

List of Contributors

Acknowledgements

1 Synchronization, Arbitration and Choice

1.1 Introduction

1.2 The Problem of Choice

1.3 Choice in Electronics

1.4 Arbitration

1.5 Continuous and Discrete Quantities

1.6 Timing

1.7 Book Structure

Part I

2 Modelling Metastability

2.1 The Synchronizer

2.2 Latch Model

2.3 Failure Rates

2.3.1 Event Histograms and MTBF

2.4 Latches and Flip-flops

2.5 Clock Back Edge

3 Circuits

3.1 Latches and Metastability Filters

3.2 Effects of Filtering

3.3 The Jamb Latch

3.3.1 Jamb Latch Flip-flop

3.4 Low Coupling Latch

3.5 The Q-flop

3.6 The MUTEX

3.7 Robust Synchronizer

3.8 The Tri-flop

4 Noise and its Effects

4.1 Noise

4.2 Effect of Noise on a Synchronizer

4.3 Malicious Inputs

4.3.1 Synchronous Systems

4.3.2 Asynchronous Systems

5 Metastability Measurements

5.1 Circuit Simulation

5.1.1 Time Step Control

5.1.2 Long-term τ

5.1.3 Using Bisection

5.2 Synchronizer Flip-flop Testing

5.3 Rising and Falling Edges

5.4 Delay-based Measurement

5.5 Deep Metastability

5.6 Back Edge Measurement

5.7 Measure and Select

5.7.1 Failure Measurement

5.7.2 Synchronizer Selection

6 Conclusions Part I

Part II

7 Synchronizers in Systems

7.1 Latency and Throughput

7.2 FIFO Synchronizer

7.3 Avoiding Synchronization

7.4 Predictive Synchronizers

7.5 Other Low-latency Synchronizers

7.5.1 Locally Delayed Latching (LDL)

7.5.2 Speculative Synchronization

7.6 Asynchronous Communication Mechanisms (ACM)

7.6.1 Slot Mechanisms

7.6.2 Three-slot Mechanism

7.6.3 Four-slot Mechanism

7.6.4 Hardware Design and Metastability

7.7 Some Common Synchronizer Design Issues

7.7.1 Unsynchronized Paths

7.7.2 Moving Metastability Out of Sight

7.7.3 Multiple Synchronizer Flops

8 Networks and Interconnects

8.1 Communication on Chip

8.1.1 Comparison of Network Architectures

8.2 Interconnect Links

8.3 Serial Links

8.3.1 Using One Line

8.3.2 Using Two Lines

8.4 Differential Signalling

8.5 Parallel Links

8.5.1 One Hot Codes

8.5.2 Transition Signalling

8.5.3 n of m Codes

8.5.4 Phase Encoding

8.5.5 Time Encoding

8.6 Parallel Serial Links

9 Pausible and Stoppable Clocks in GALS

9.1 GALS Clock Generators

9.2 Clock Tree Delays

9.3 A GALS Wrapper

10 Conclusions Part II

Part III

11 Arbitration

11.1 Introduction

11.2 Arbiter Definition

11.3 Arbiter Applications, Resource Allocation Policies and Common Architectures

11.4 Signal Transition Graphs, Our Main Modelling Language

12 Simple Two-way Arbiters

12.1 Basic Concepts and Conventions

12.1.1 Two-phase or Non-return-to-zero (NRZ) Protocols

12.1.2 Four-phase or Return-to-zero (RTZ) Protocols

12.2 Simple Arbitration Between Two Asynchronous Requests

12.3 Sampling the Logic Level of an Asynchronous Request

12.4 Summary of Two-way Arbiters

13 Multi-way Arbiters

13.1 Multi-way MUTEX Using a Mesh

13.2 Cascaded Tree Arbiters

13.3 Ring-based Arbiters

14 Priority Arbiters

14.1 Introduction

14.2 Priority Discipline

14.3 Daisy-chain Arbiter

14.4 Ordered Arbiter

14.5 Canonical Structure of Priority Arbiters

14.6 Static Priority Arbiter

14.7 Dynamic Priority Arbiter

15 Conclusions Part III

References

Index