Preface
Most books on digital design only briefly touch on the design of synchronizers and arbiters, with maybe two or three pages in a 300 page book, or a chapter at most. This is because there was no real need for it in the early years of computer design. Processors were largely self-contained and used a single clock, so interfacing the processor to slow peripherals, or other processors was not seen as a major task. The fact that it is not simple emerged in the 1970s and 1980s when data rates between processors increased, and sometimes systems with more than one time zone were being designed. Despite frequent synchronization failures because of lack of understanding of the design principles at that time, synchronization still did not make it into the standard literature, and very little has been written since about how they should be designed. More recently processors are being designed with many more high-speed ports linked to networks, and the systems themselves are often made up of several core processors connected to an internal bus or network on chip. This means that processors operating on different time frames must communicate at high data rates, and when two or more processors request access to a common resource, there has to be some arbitration to decide which request to deal with first.
The need for synchronizers to ensure that data coming from one time frame is readable in another, and arbiters to ensure that a clean decision is taken has always been there, but the understanding has not. Our aim is to promote good design in these areas because the number of timing interface circuits is escalating as the number of multiprocessor systems grows. A single processor interfacing to the real world through a few slow peripherals will not have many problems, but as the number of input/output ports increases, and the data rates increase, difficulties with reliability, data latency and design robustness will also increase.
This book has been written to meet the need for an understanding of the design of synchronizers and arbiters. It is intended for those involved in the design of digital hardware that has to interface to something else; other hardware, a communication system, or in the end, people. Only systems that do not interface to the outside world are free from the need to deal with synchronization and arbitration. It is divided into three sections. Section I deals with the fundamental problem of metastability. Any system that has to make a choice between two similar alternatives will end up taking longer and longer as the two alternatives approach each other in desirability, and if the amount of time available is limited, the decision mechanism will fail at a predictable rate. We describe the theory of this and how it affects practical circuits, so that the reader may be able to choose a suitable circuit for a particular application, and how to measure its reliability and performance. Section II looks at synchronizers in systems. In a multiprocessor system, the timing in each processor may be completely independent, linked by stoppable clocks as in globally asynchronous locally synchronous (GALS) systems, or partly linked for example by means of phase-locked loops. To optimize the system performance and reliability the synchronization method should be chosen to fit the methodology, and several examples are given. Arbitration has a section of its own, Section III, where the design of arbiters is approached by starting from a specification and developing asynchronous arbiters from simple daisy-chain circuits up to fully dynamic arbiters taking account of the priority required by each packet of data.
I am indebted to many of my colleagues for discussions over the years about the design of computer systems, but most particularly to those involved with the ASYNC series of seminars where interfacing systems using different timing methods, synchronous, asynchronous, and clocks with different frequencies has been a recurring theme. Because asynchronous systems are themselves made up of many high-speed components interacting together, it is there that the problems of timing are at their most acute, and many of the methods described had their first outing at one of the ASYNC seminars. Colleagues at Newcastle University have not only contributed to the text and reviewing of much of the manuscript, but have also provided much to the ideas contained in the book. In the end what matters is whether the techniques are applicable in the industrial world, and for this reason I am grateful for the input provided over many years from people who designed computers ranging from the Ferranti ATLAS in the early 1960s to SUN and INTEL in 2007. Those that are interested in a fuller bibliography that the references provide at the end of the book might like to look at Ian Clark's excellent website:
http://iangclark.net/metastability.html
David J. Kinniment
Newcastle, UK