References

[1] N. Rescher, Choice without preference: A study of the logic and the history of the problem of Buridan's Ass, Kant-Studien, 1959/60, No. 51, pp 142–175.

[2] S. Lubkin, Asynchronous signals in digital computers, Discussion, Proc ACM, 1952, pp 238–241.

[3] I. Catt, Time loss through gating of asynchronous logic pulses, IEE Trans., 1966, EC15, 108–111.

[4] T.J. Chaney and C.E. Molnar, Anomalous behavior of synchronizer and arbiter circuits, IEEE Transactions on Computers, C-22(4), 412–422, April 1973.

[5] D.J. Kinniment and D.B.G. Edwards, Circuit Technology in a large computer System, Proc. conference on Computers-Systems and Technology London, October 1972, pp 441–449.

[6] D.J. Kinniment and J.V. Woods, Synchronization and arbitration circuits in digital systems, Proc. IEE 123(10), 961–966, October 1976.

[7] H.J.M. Veendrick, The behavior of flip-flops used as synchronizers and prediction of their failure rate, IEEE Journal of Solid-State Circuits, SC-15(2), 169–176, April 1980.

[8] K.O. Jeppson, Comments on the Metastable Behavior of Mismatched CMOS Latches, IEEE Journal of Solid State Circuits 31(2) 275–277, February 1996.

[9] C.L. Seitz, Ideas about arbiters, Lambda, 1 (first quarter):10–14, 1980.

[10] C. Dike and E. Burton, Miller and Noise Effects in a Synchronizing Flip-Flop IEEE Journal of Solid State Circuits, 34(6), 849–855, June 1999.

[11] N.H.E. Weste, and K Eshraghian, Principles of CMOS VLSI design: A systems perspective, 2nd edn, Addison-Wesley, 1992, p 326.

[12] F.U. Rosenberger, C.E. Molnar, T.J. Chaney and T-P. Fang, Q-Modules: Internally Clocked Delay-Insensitive Modules, IEEE Transactions on Computers, 37(9), 1005–1018, September 1988.

[13] C.H. van Berkel and C.E. Molnar, Beware the 3-Way Arbiter, IEEE Journal of Solid-State Circuits, 34, 840–848, 1999.

[14] O. Maevsky, D.J. Kinniment, A. Yakovlev, and A. Bystrov, Analysis of the oscillation problem in tri-flops, Proc. ISCAS'02, Scottsdale, Arizona, May 2002, IEEE, vol. I, pp 381–384.

[15] A. van der Ziel, Thermal Noise in Field Effect Transistors, Proc. IEEE, August 1962, 1801–12.

[16] G.R. Couranz, and D.F. Wann, The theoretical and experimental behaviour of synchronizers operating in the metastable region, IEEE Transactions on Computers C-24(6), 604–616 June 1975.

[17] S. Yang and M. Greenstreet, Computing Synchronizer Failure Probabilities, Proc. DATE 07, April 2007.

[18] D.J. Kinniment, A. Bystrov, A.V. Yakovlev, Synchronization Circuit Performance, IEEE Journal of Solid-State Circuits, 37(2), 202–209, 2002.

[19] C. Dike and E. Burton, Miller and Noise Effects in a Synchronizing Flip-Flop, IEEE Journal of Solid State Circuits, 34(6), 849–855, June 1999.

[20] QuickLogic Corporation, Metastability report for FPGAs, Application Note, 1997.

[21] D.J. Kinniment and J.V. Woods, Synchronization and arbitration circuits in digital systems, Proc. IEE, 123(10), 961–966, October 1976.

[22] M. Maymandi-Nejad and M. Sachdev, A digitally programmable delay element: Design and analysis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(10), 1126–1126, October 2004.

[23] J. Zhou, D.J. Kinniment, G. Russell, and A. Yakovlev, A Robust Synchronizer Circuit, Proc. ISVLSI'06, pp 442–443, March 2006.

[24] K.A. Bowman, X. Tang, J.C. Eble, and J.D. Meindl, Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance, IEEE J. Solid-State Circuits, 35, 1186–1193, August 2000.

[25] W.J. Dally, and J.W. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.

[26] T. Chelcea and S.M. Nowick, Robust interfaces for mixed-timing systems with application to latency insensitive protocols, Proc. 38th ACM/IEEE Design Automation Conference, pp 21–26, June 2001.

[27] A. Iyer and D. Marculescu, Power-performance evaluation of globally asynchronous, locally synchronous processors. Proc. 29th International Symposium on Computer Architecture, pp 158–168, June 2002.

[28] A. Chakraborty. and M. Greenstreet, Efficient Self-Timed Interfaces for crossing Clock Domains. Proc. ASYNC 2003, Vancouver, 12–16 May 2003, pp 78–88.

[29] A. Chakraborty and M.R. Greenstreet, A minimalist source-synchronous interface. Proc. 15th IEEE ASIC/SOC Conference, pp 443–447, September 2002.

[30] L.R. Dennison, W.J. Dally, and D. Xanthopoulos, Low latency plesiochronous data retiming. Proc. 16th Anniversary Conference on Advanced Research in VLSI, pp 304–315, 1995.

[31] M.R. Greenstreet, STARI: A Technique for High-Bandwidth Communication. PhD Thesis, Department of Computer Science, Princeton University, January 1993.

[32] M.R. Greenstreet, Implementing a STARI chip. Proc. 1995 International Conference on Computer Design, pp 38–43, Austin, Texas, October 1995.

[33] I. Sutherland and S. Fairbanks, GasP: A minimal FIFO control. Proc. 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp 46–53, April 2001.

[34] Y. Semiat and R. Ginosar, Timing Measurements of Synchronization Circuits. Proc. ASYNC2003, Vancouver, 12–16 May 2003, pp 68–77.

[35] R. Ginosar and R. Kol, Adaptive Synchronization. Proc. AINT2000, Delft, 19–20 July 2000, pp 93–101.

[36] R. Dobkin, R. Ginosar and C. Sotirou, Data Synchronization Issues in GALS SoCs. Proc ASYNC 2004 pp 170–179.

[37] R. Dobkin, R. Ginosar, and C. Sotirou, High Rate Data Synchronization in GALS SoCs. IEEE Trans. VLSI systems 14(1), 1063–1074, October 2006.

[38] N.A. Kurd, J.S. Barkatullah, R.O. Dizon, T.D. Fletcher, and P.D. Madland, Multi-GHz Clocking Schemes for Intel Pentium 4 Microprocessors, Proc. ISSCC 2001, February 2001, pp 404–405.

[39] S. Tam, S. Rusu, U.N. Desai, R. Kim, J. Zhang, and I. Young, Clock Generation and Distribution for the first IA-64 Microprocessor. IEEE JSSC 35(11), 1545–1552, November 2000.

[40] G.K. Konstadinidis, K. Normoyle, et al. Implementation of a third-generation 1.1-GHz 64-bit microprocessor. IEEE Journal of Solid-State Circuits, 37(11), 1461–1469, November 2002.

[41] A. Kowalczyk, V. Adler, et al. The first MAJC microprocessor: a dual CPU system-on-a-chip. IEEE Journal of Solid-State Circuits, 37(11), 1461–1469, November 2001.

[42] P.J. Restle, T.G. McNamara, et al. A clock distribution network for microprocessors. IEEE Journal of Solid State Circuits, 36(5), 792–799, May 2001.

[43] F.U. Rosenberger, C.E. Molnar, T.J. Chaney, and T.-P. Fang, Q-Modules: Internally Clocked Delay-Insensitive Modules. IEEE Transactions on Computers, 37(9), 1005–1018, September 1988.

[44] A. Bystrov, D. Sokolov, and A. Yakovlev, Low Latency Control Structures with Slack, Proc. ASYNC2 003, Vancouver, 12–16 May 2003, pp 164–173.

[45] H.R. Simpson, Four-slot fully asynchronous communication mechanism, IEE Proceedings 137(E1), 17–30, January 1990.

[46] H.R. Simpson, Correctness analysis of class of asynchronous communication mechanisms. IEE Proceedings 139(E1) 35–49, January 1992.

[47] F. Xia, A. Yakovlev, D. Shang, A. Bystrov, A. Koelmans, D.J. Kinniment, Asynchronous Communication Mechanisms Using Self-timed Circuits. Proc. 6th Int. Symp. on Advanced Research in Asynchronous Circuits and Systems (Async2000), April 2000, Eilat Israel IEEE Computer Society Press, pp 150–159.

[48] R. Ginosar, Fourteen ways to fool your synchronizer. Proc. ASYNC2003, Vancouver, 12–16 May 2003, pp 89–196.

[49] A. El-Amawy, M. Naraghi-pour, and M. Hegde. Noise modeling effects in redundant synchronizers. IEEE Trans Computers 42(12), 1487–1494, December 1993.

[50] B.S. Landman and R.L. Russo, On a Pin Versus Block Relationship For Partitions of Logic Graphs. IEEE Trans. Comput., C-20, 1469–1479, 1971.

[51] W.E. Donath, Placement and Average Interconnection Lengths of Computer Logic, IEEE Trans. Circuits Syst. CAS-26, 272–277, 1979.

[52] L. Benini and G. De Micheli, Networks on chip: a new paradigm for systems on chip design Design, Automation and Test in Europe Conference and Exhibition, Proceedings DATE 2002. pp 418–419.

[53] E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, QNoC: QoS Architecture and Design Process for Network on Chip, Journal of Systems Architecture, special issue on Network on Chip, 50, 105–128, February 2004.

[54] E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, Cost Considerations in Network on Chip. Integration-The VLSI Journal, special issue on Network on Chip, 38(1), 19–42, October 2004.

[55] International Technology Roadmap for Semiconductors (ITRS), Semiconductor Industry Association, 2001.

[56] T Bjerregaard and J Sparso, A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip. Proc. 11th IEEE International Symposium on Asynchronous Circuits and Systems, Salt lake City 2005, pp 34–43.

[57] R. Ho, K.W. Mai, and M.A. Horowitz, The Future of Wires, Proc. IEEE, 89(4), 490–504, 2001.

[58] R. Dobkin, Y. Perelman, T. Liran, R. Ginosar, and A. Kolodny, High Rate Wave-Pipelined Asynchronous On-Chip BitSerial Data Channel. Proc. 13th IEEE International Symposium on Asynchronous Circuits and Systems, Berkeley, CA 2007, pp 3–14.

[59] M.T. Dean, T. Williams, et al. Efficient Self-timing with Level Endcoded 2-Phase Dual-Rail (LEdR). Proc. ARVLSI, pp 55–70, 1991.

[60] W.J. Bainbridge and S.B. Furber, CHAIN: A Delay Insensitive CHip Area Interconnect. IEEE Micro special issue on Design and Test of System on Chip, 142(4), 16–23, September 2002.

[61] C. D'Alessandro, D. Shang, A. Bystrov, A. Yakovlev, and O. Maevsky, Multiple-Rail Phase-Encoding for NoC. Proc. 12th ASYNC, pp 107–116, March 2006.

[62] E. Raisanen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, Time interval measurements using time-to-voltage conversion with built-in dual-slope A/D conversion. Proc. 1991 International Symposium on Circuits and Systems (ISCAS'91), 5, 2573–2576, Singapore, 1991.

[63] P. Dudek, S. Szczepanski, and J. Hatfield, A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE Transactions Solid-State Circuits, 35, 240–247, February 2000.

[64] P.M. Levine and G.W. Roberts, A High Resolution Flash Time-to-Digital Converter and Calibration for System-on-Chip Testing. IEE Proceeding-Computers and Digital Techniques, 152(3), 415–426, May 2005.

[65] R. Mullins and S. Moore, Demystifying Data-Driven and Pausible Clocking Schemes. Proc. 13th Intl. Symp. on Advanced Research in Asynchronous Circuits and Systems (ASYNC), 2007, pp 175–185.

[66] S. Das, S. Pant, D. Roberts, S. Lee, D. Blaauw, T. Austin, T. Mudge, and K. Flautner, A self-tuning DVS processor using Delay-error Ddetection and correction. Digest of Technical Papers, 2005 Symposium on VLSI Circuits, pp 258–261.

[67] D. Bormann, GALS test chip on 130 nm process. Electro Nobes Theor. Comput. Sci., 146(2), 29–40, 2006.

[68] K. Yun and A. Dooply, Pausible clocking based heterogeneous systems. IEEE Transactions VLSI Systems, 7(4), 482–487, December 1999.

[69] J. Sparsø and S. Furber, Principles of Asynchronous Circuit Design–A Systems Perspective, Kluwer Academic Publishers, 2001.

[70] I. Sutherland, Micropipelines: Turing Award Lecture. Communications of the ACM, 32(6), 720–738, June 1989.

[71] J. Kessels, A. Peelers, P. Wielage, and S.-J. Kim, Clock synchronization through handshaking. 8th Intl. Symp. on Advanced Research in Asynchronous Circuits and Systems (ASYNC), 2002, pp 59–68.

[72] M. Krstic, E. Grass, and C. Stahl, Request-Driven GALS Technique for Wireless Communication System. 11th Intl. Symp. on Advanced Research in Asynchronous Circuits and Systems (ASYNC), 2005, pp 76–85.

[73] W. Lim, Design methodology for stoppable clock systems. IEE Proc. Computers and Digital Techniques, 133(pt.E)(1), 65–69, January 1986.

[74] S. W. Moore, G. S. Taylor, P. Cunningham, R. D. Mullins, and P. Robinson, Self-calibrating clocks for globally asynchronous locally synchronous systems. Proc. Intl. Conf. on Computer Design (ICCD), 2000, pp 74–79.

[75] R. Dobkin, R. Ginosar, and C. P. Sotiriou, Data synchronization issues in GALS SoCs. 10th Intl. Symp. on Advanced Research in Asynchronous Circuits and Systems (ASYNC), 2004, pp 170–179.

[76] A. E. Sjogren and C. J. Myers, Interfacing synchronous and asynchronous modules within a high-speed pipeline. Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 8(5), 573–583, October 2000.

[77] D. Bormann and P. Cheung, Asynchronous wrapper for heterogeneous systems. Proc. Intl. Conf. on Computer Design (ICCD), pp 307–314, 1997.

[78] C.A. Petri, Kommunikation mit Automaten. PhD Thesis, Bonn, Institut für Instrumentelle Mathematik, 1962.

[79] T. Murata, Petri Nets: Properties, analysis and applications. Proc. IEEE, 77(4), 541–580, April 1989.

[80] L. Ya. Rosenblum and A.V. Yakovlev, Signal graphs: from self-timed to timed ones. Proc. Int. Workshop on Timed Petri Nets, Torino, Italy, July 1985, IEEE CS Press, pp 199–207, 1985.

[81] T.-A. Chu, C.K.C. Leung, and T.S. Wanuga, A design methodology for concurrent VLSI systems. Proc Int. Conf. Computer Design (ICCD), pp. 407–410. IEEE CS Press, 1985.

[82] A. Yakovlev, A. Petrov, and L. Lavagno. A low latency asynchronous arbitration circuit. IEEE Trans. on VLSI Systems, 2(3), 372–377, September 1994.

[83] A. Yakovlev, Designing arbiters using Petri nets. Proc. Workshop on Asynchronous VLSI, Nof Genossar, Israel, March 1995, VLSI Systems Research Center, Technion, Haifa, Israel, pp 178–201.

[84] M. Renaudin and A. Yakovlev, From Hardware Processes to Asynchronous Circuits via Petri nets: an Application to Arbiter Design. Int. Workshop on Token-Based Computing (ToBaCo'04) within ICATPN'04, Bologna, Italy, pp 59–66, June 2004.

[85] J. Cortadella, L. Lavagano, P. Vanbekbergen and A. Yakovlev, Designing asynchronous circuits from behavioural specifications with internal conflict. Proc. Int. Symp. on Advanced Research in Asynchronous Circuits and Systems (ASYNC'94), Salt Lake City, Utah, pp 106–115, IEEE CS Press, Nov. 1994.

[86] J.-B. Rigaud, J. Quartana, L. Fesquet and M. Renaudin, High-level modeling and design of asynchronous arbiters for on-chip communication systems. Proc. Design, Automation and Test in Europe (DATE'02), p 1090, March 2002.

[87] Bystrov, D.J. Kinniment, and A. Yakovlev, Priority arbiters. Proc. ASYNC'00, pp 128–137. IEEE CS Press, April 2000.

[88] Mitrani and A. Yakovlev, Tree Arbiter with Nearest-Neighbour Scheduling. Proc. 13th Int. Symp. on Computer and Information Sciences (ISCIS'98), 26–28 October, Belek-Anatlya, Turkey. In: Advances in Computer and Information Sciences'98 (Eds. U. Gudukbay, T. Dayar, A. Gursoy, E. Gelenbe) Concurrent Systems Engineering Series Vol. 53, pp 83–92.

[89] K.S. Low and A. Yakovlev. Token Ring Arbiters: an Exercise in Asynchronous Logic Design with Petri Nets, TR. no. 537, Dept of Comp. Sci., University of Newcastle upon Tyne, November 1995.

[90] B. Grahlmann, The PEP Tool. LNCS 1254: CAV'97 (Computer Aided Verification), Haifa, pp 440–443. Springer-Verlag, June 1997.

[91] V. Khomenko and M. Koutny, Towards an Efficient Algorithm for Unfolding Petri Nets, LNCS 2154: CONCUR 2001 – Concurrency Theory, pp 366–380, Springer Verlag, 2001.

[92] Benko and J. Ebergen, Delay-insensitive solutions to the committee problem. Proc. ASYNC'94, IEEE CS Press, pp 228–237, November 1994.

[93] Ch. E. Dickson, A Macromodule User's Manual. Technical Report No. 25, Computer Systems Laboratory, Washington University, St. Louis, Missouri, 1974.

[94] R.M. Keller, Towards a theory of universal speed-independent modules. IEEE Trans. Computers, C-23(1), 21–33, January 1974.

[95] C.H. van Berkel and C.E. Molnar, Beware the 3-Way Arbiter, IEEE Journal of Solid-State Circuits, 34, 840–848, 1999.

[96] O. Maevsky, D.J. Kinniment, A. Yakovlev, and A. Bystrov, Analysis of the oscillation problem in tri-flops. Proc. ISCAS'02, Scottsdale, Arizona, IEEE, vol. I, pp 381–384, May 2002.

[97] M.B. Josephs and J. Yantchev, CMOS Design of the Tree Arbiter Element. IEEE Trans. VLSI Systems, 4(4), 472–476, 1996.

[98] A.J. Martin, Synthesis of asynchronous VLSI circuits. In J. Straunstrup (ed., Formal Methods for VLSI Design, Chapter 6, pp 237–283. North-Holland, 1990.

[99] N. Thorne, On-chip buses enable block based ASIC/FPGA design. IP'97-Europe, October 1997, Bracknell.

[100] Clements, Microprocessor System Design, 3rd edn, Int. Thomson Publishers, 1997.

[101] D. Del Corso, H. Kirrmann, and J.D. Nicoud, Microcomputer Buses and Links. Academic Press, 1986.

[102] A.J. Martin, Collected Papers on Asynchronous VLSI Design, Caltech-CS-TR-90-09, Dept. of Computer Science, Caltech, 1990.

[103] D.E. Muller and W.S. Bartky, A theory of asynchronous circuits. Proc. Int. Symp. on the Theory of Switching, April 1959, Harvard University Press, pp 204–243.

[104] Bystrov and A. Yakovlev, Ordered Arbiters. IEE Electronics Letters, 35(11), 877–879, 27 May 1999.

[105] A.J. Martin, Collected Papers on Asynchronous VLSI Design, Caltech-CS-TR-90-09, Dept. of Computer Science, California Institute of Technology, 1990, p 50.

[106] D.J. Kinniment and J.V. Woods, Synchronization and arbitration circuits in digital systems. Proc. IEE, 123(10) 961–966, October 1976.

[107] J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces. Springer Series in Advanced Microelectronics, vol. 8, Springer, 2002.

[108] A. Yakovlev, L. Lavagno, and A. Sangiovanni-Vincentelli, A unified signal transition graph model for asynchronous control circuit synthesis. Formal Methods in System Design, vol. 9, No. 3, Kluwer pp 139–188, November 1996.