26.2.2.1 Metal-Oxide Semiconductor Field-Effect Transistors (MOSFET)

MOSFETs are very fast unipolar-carrier enhancement-mode semiconductor devices controlled by the v_Gs voltage applied at the gate-source terminals (Fig. 26.5a) [10, 11, 13]. Their speed is mostly due to the absence of carrier recombination since in N-type MOSFETs, the carriers are almost only electrons. MOSFET semiconductor structure forms a N⁺N⁻PN⁺ shorted base-emitter bipolar transistor (Fig. 26.5a), which is often referred as behaving as an intrinsic antiparallel PIN diode (Fig. 26.5b).

FIGURE 26.5 (a) MOSFET structure showing the Drain-Source current path; (b) Electronic symbol including intrinsic diode; and (c) MOSFET model with parasitic components.

The MOSFET has the capabilities for high-speed switching in the nanosecond or subnanosecond range [14, 15].

In pulsed power applications, MOSFETs should behave as ideal switches, being switched-on if v_Gs exceeds the threshold value V_GSth, v_GS > V_GSth + V_DSon, with V_DSon ≈ The ON MOSFET behaves almost like a resistor RDSon with low value and positive temperature coefficient. The MOSFET opens (OFF state, I_D ≈ 0) if v_Gs < V_Gsth, but usually the gate driver enforces v_Gs < 0 with v_Ds > 0. If v_Ds < 0, then the intrinsic diode starts to conduct (the on voltage is V_PINon), which is seldom advantageous since the internal PIN diode is usually not optimized for low voltage drop or high-speed switching. In this case, it is better that the gate driver turns on the MOSFET channel in order to prevent the PIN diode conduction, if − R_DSonI_D < V_PINon.

The gate current after charging or discharging of gate stray capacitances is almost null, and therefore, needed gate power is very low. In pulsed power applications, fast switching is needed, therefore the circuits that drive the v_Gs voltage must charge/discharge the MOSFET parasitic nonlinear capacitances considering the effects of device terminal inductances (Fig. 26.5c). The switching speed of existing MOSFETs is limited mainly by packaging (lead inductances) and drain, gate and source resistances together with intrinsic capacitances.

The switching times can be in the order of some nanoseconds or lower and are affected by the driver R_G value. Resistor R_G dampens the RLC series circuit that contains C_Gs, C_DG, gate and source stray inductances L_S. The gate resistor can be sized adopting a suitable value for the damping factor of the RLC series circuit τ = R_G/(2Z_G), where , where C_G is the equivalent gate capacitor, being .

The equivalent gate capacitor C_G, can be known from the manufacturers datasheets (C_Gs = C_iss –C_rss; Cdg = C_rss; and Cds = Coss –C_rss), giving C_G ≈ C_GS + C_DG(dv_GS/dv_GS), while the gate and source stray inductances L_S can be estimated considering typical per unit values. For printed circuit boards (strip lines) or typical parallel wires, inductance L_S is usually given nearly by 10nH/cm times the current path total length in centimeters (typical TO220 package of MOSFETs exhibits source terminal inductances of l_S ≈ 5 nH). For twisted wire pairs or other low-inductance connections, the value can be lowered down to 3nH/cm. The inductor estimation (and C_G nonlinear capacitor calculation) does not need to be very precise since they only affect R_G by their square root values.

EXAMPLE 26.2 Calculate the gate resistor for a MOSFET with Cgs ≈ 800 pF and Cdg ≈ 40 pF, operating at a drain voltage of 800 V, driven by v_GS = 15 V through a printed circuit strip-line of 5 cm total length.

SOLUTION. For the given strip-line length, it is obtained L_S ≈ 50 nH. The gate capacitor is C_G ≈ C_GS+C_DG(dv_GD/dv_GS)≈ 10− 12 × [800 + 40 × (800/15)]≈ 2.9 nF. Therefore, the gate resistor is . As C_GS and Cdg are nonlinear voltage-dependent capacitances, using R_G << Zg can establish gate-source overvoltages two to three times the applied v_GS voltage, which can disrupt the gate insulation oxide if they exceed the breakdown voltage V_gss, destroying the MOSFET. To minimize the R_G value, for faster gate capacitor charging and switching, it is essential to strongly reduce the stray inductances (if L_S ≈ 0, then R_G ≈ 0).

Fast MOSFET drivers require low stray inductances and often must be based on avalanche transistors [12] (switching bipolar transistors optimized to operate near their collector emitter breakdown voltage V_B, but at limited current) or resonant circuits [13]. The avalanche transistors rapidly charge the capacitors C_Gs and C_DG, by transferring capacitor charge from a capacitor reservoir C_a to C_gs and C_dg (Fig. 26.6a). Supposing charge continuity, the MOSFET gate voltage should be V_GS ≈ V_BC_a/(C_a + C_G). The Zener diode Z18V helps protect the gate oxide against disruption, but the Zener junction capacitance should be added to the above C_G value.

FIGURE 26.6 (a) Avalanche transistor MOSFET driver; (b) Tailoring switching speed using two resistors.

MOSFET switching behavior includes crossing the saturation zone (MOSFET active zone) where i_D ≈ K(v_GS –V_GSth)2 being K, a MOSFET structural parameter (see Chapter 4, “MOSFET,” in this book). This effect can be worsened when switching pulsed power capacitive loads.

Switch-on t_on and Switch-off t_off times can be tailored using different resistive paths to turn-on (R₂) and to turn-off (R₁||R₂) (Fig. 26.6b) limiting the charging current and the drain voltage rise or fall rates, at the expense of increased switching losses.

Considering the on and off switching times (t_on, t_off), the dissipated switching power at the switching frequency f_s is P_S = [(t_on + t_off) V_DSI_D + C_DSV²_DS]f_s/2.

Pulsed power applications often need semiconductor switch protection to limit load short-circuit current. Since in MOSFETs V_DSon ≈ R_DSonI_D, and if R_DSon is fairly constant, then short-circuit protection circuits can be based on the measured V_DSon voltage (Fig. 26.7a) [10]. Sensed by diode D_b3, this voltage, if low enough, maintains the C_z voltage low preventing D_z to avalanche and maintaining Q_t2 off. However, if V_DSon rises, then D_b3 turns off, C_z voltage rises, and D_z avalanches turning Q_t2 into saturation that shorts the v_GS voltage and turns off the MOSFET. Capacitor C_z acts as a memory, creating a delay that enables the MOSFET turn-on. Figures 26.7b,c show alternatives in which the rate of the v_GS decay is slowed to lower the rate of rise of the v_DS preventing this voltage to exceed the MOSFET hold-off (avalanche) voltage V_dss. Figure 26.7b shows a capacitive method in which C_g C_G, whereas in Fig. 26.7c, the low-power P MOSFET M_p, in series with the main MOSFET gate, is turned off, putting the high-valued resistor R_g2 in the turn-off path to limit the v_GS decay and v_DS rate of rise.

FIGURE 26.7 (a) Active protection against load short circuits; (b) Active protection including capacitive v_DS rate limiter; (c) Active protection including resistive v_DS rate limiter.

The maximum turn-off overvoltage can also be limited either by using MOSFET parallel connected Zeners (or voltage clamping Metal Oxide Varistors [MOV]) or by using an avalanche diode (with avalanche voltage higher than the supply voltage but somewhat lower than maximum semiconductor voltage rating) in series with a blocking diode connected to the gate-drain terminals (Fig. 26.8).

FIGURE 26.8 MOSFET overvoltage protection circuit.

26.2.2.2 Insulated Gate Bipolar Transistors (IGBT)

IGBTs are MOS technology based semiconductor devices, which reduce on-state voltage drop, by adding an extra P⁺ semiconductor layer in the drain side (Punch-Through IGBT) or by substituting the N⁺ by a P⁺ layer (NonPunch-Through [NPT] or Reverse-Blocking IGBT [RB-IGBT]) [10, 11, 13]. The P⁺ layer injects holes in the drift layer reducing voltage drop by conductivity modulation. The resulting device can be viewed as a low gain high-voltage PNP bipolar transistor driven by a power MOSFET (Fig. 26.9). Gate drivers for IGBTs are similar to those of MOSFETs.

FIGURE 26.9 IGBT equivalent circuit and common symbols.

IGBTs can turn-on almost as fast as MOSFETs, using v_GE > V_GEth. The on-state saturation voltage V_CEsat depends on the v_ge value and increases rapidly for v_ge < 12 V, the device risks working into the active zone for lower v_ge values.

Due to the injected minority recombination into the base, IGBTs are relatively slow turned-off devices and exhibit tail currents. However, they can withstand much higher hold-off voltages (up to 6.5 kV) and currents (up to 3 kA) than MOSFETs, which are limited to nearly 1.2 kV, 100 A peak current. At 6 kV voltages and 3 kA currents, IGBTs on-state losses are significant, degrading efficiency and causing heat removal problems, yet they are being used in very high-voltage systems [16–19].

Most considerations about the MOSFET drive and protections are still valid for IGBTs. In particular, in shoot-through situations, the IGBT device can be protected by detecting desaturation voltage, then shutting down the IGBT using gate-drive circuits similar to those in Fig. 26.7.

26.2.2.3 Injection-Enhanced Gate Transistors (IEGT)

IEGT are IGBT-like structures with deep trench-gates and wider cell widths. Hole concentration in the P layer under the gate electrode is enhanced due to hole accumulation, similar to the conductivity modulation of a PIN diode, lowering the on-state voltage and increasing the efficiency specially in high-voltage devices. The enhanced carrier distribution under the gate electrode leads to higher conductivity of the N-base region in the trench-gate IGBT structure, as the gate region extends into the N-base region below the P-base layer. This phenomenon has been called the injection enhancement effect in deep trench-gate IGBT structures and enables higher device voltage rating. As this phenomenon of carrier enhancement under the gate electrode occurs in all IGBT structures, including the planar-gate structures, the IEGT device is a kind of IGBT and can be viewed as such, although their particular physical structure enables them to withstand higher voltages and currents than planar IGBTs structures. The same is valid for similar proposed structures such as the Carrier-Stored Trench-gate Bipolar Transistor (CSTBT-IGBT).

26.2.5.1 Semiconductor Series Stacks

For applications where the needed working voltage is higher than the available semiconductor ratings, one possible solution is to series connect several power devices. Steady state and transient balance or sharing of the voltage between series semiconductor devices are very important, since most power semiconductor devices do not hold voltages above their rating and their reverse currents and reverse recovered charges differ from device-to-device even within the same type and maker, the semiconductor with the least reverse leakage current will hold higher voltages.

EXAMPLE 26.3 Consider a string of two series diodes and suppose the total voltage U = 10 kV, the two diodes both with nominal repetitive reverse voltage V_RRM = 6 kV, but reverse leakage currents of I_Rmax = 40 mA, and I_Rmin = 10 mA. Calculate the diodes reverse voltages.

SOLUTION. We can calculate R_eqoffmin =V_RRM/I_Rmax = 150 kΩand R_eqoffmax =V_RRM/I_Rmin = 600 kΩ(Fig.26.18). Therefore, the diode with R_eqoffmin would have the voltage V_Reqoffmin = 10 × 10³ × 150/(150 + 600) = 2 kV, while V_Reqoffmax=lQ × 10³ × 600/(150 + 600) = 8 kV that exceeds the diode maximum rating. This diode would operate near its avalanche voltage (≈ 6 kV), which could be destructive.

Steady-state balancing can be achieved using high-value parallel resistors R_h, so that the parallel of R_h, with R_eqoffmin, or R_eqoffmax should give a resistance able to maintain the semiconductor reverse voltage within acceptable limits.

FIGURE 26.18 Series connection of power semiconductors.

Considering n-series-connected power semiconductors and one of them with I_Rmin = 0 (R_eqoffmax≈∞), while the remaining n –1 have the typical value R_eqoff, the total value R_T of the string of resistors is R_T=R_h + (n − l)(R_h||R_eqoff) (Fig. 26.19). The maximum voltage occurs in the diode with R_eqoffmax≈∞ being V_Rmax = UR_h/R_T. This value should observe a safety margin U/n < V_Rmax < κV_RRM, where κ < 1, that permits to obtain n > U/V_Rmax and <R_h =R_eqoff(nκV_RRM–U)/(U.κV_RRM). Note that U > κ V_RRM and nκV_RRM > U.

FIGURE 26.19 (a) Steady-state balancing a series connection of power semiconductors; (b) Equivalent model.

The R_h resistors should be as high as possible to minimize their dissipated power. The maximum R_h value can be obtained considering the I_Rmin and I_Rmax semiconductor currents (instead of I_Rmin = 0) to obtain R_h < (nκV_RRM –U)/[(n − 1)(I_Rmax –I_Rmin)].

An alternative to the use of the dissipative resistors is to antiparallel avalanche or Zener diodes or Metal Oxide Varistors (MOV) with each series device.

To help share the voltage during transients, R_SC_S parallel snubbers must be also included (Fig. 26.20). If they are designed just to balance the reverse recovered charge Q_RR, then the capacitor value can be given by C_Smin≈ Δ Q_RR/ Δ U, Δ U is the allowed voltage mismatch and Δ Q_RR is the Q_RR variation among devices. Resistor R_S limits the discharge current when the power semiconductor turns on.

FIGURE 26.20 Dynamic- and steady-state balancing of seriesconnected power semiconductors.

To operate the R_SC_S as a parallel snubber, the circuit associated stray inductance L_S should be estimated. Assuming energy conservation, a rough estimation of theC_S value is C_S ≈ L_SI²_RR/[n(κV_RRM)²]. Resistor R_S should define the damping factor τ of the equivalent RLC circuit, being . For controlled turn-on and turn-off devices, the R_sC_s parallel snubber can be improved using an extra diode (R_VC_VD_V in Fig. 26.11, with L_V = L_S). To obtain near-balanced turn-on t_r and turn-off t_f times for each series semiconductor, with direct current I_AK, hold-off voltage κV_DRM and pulse on minimum time T_pmin, L_S should have the value L_S ≈ κV_DRMt_r/I_AK and C_V ≈ I_AKt_f/(κV_DRM), beingR_V ≈ T_pminτ²/(πC_V).

26.2.5.2 Generalized Cascodes

To use a series stack of controlled turn-off semiconductors such as MOSFETs, SITs, or even IGBTs, the generalized cascode association (Fig. 26.21) is a valuable alternative to the simple series connection [10, 14, 15]. The simple series association of turn-off devices usually needs optical fibre isolated gate drivers fed from transformer isolated current source power inverters with series connection through high-voltage closed-loop cables, to assure the insulation between the voltage levels.

FIGURE 26.21 Generalized cascade associations: (a) using SIT devices; (b) using only MOSFETs; and (c) alternative connection of gate capacitor.

The Cascode association is faster than other associations when unipolar carrier semiconductors such as MOSFETs or SITs are used. For MOSFET devices (Fig. 26.21b), the capacitor C must hold the charge to turn the MOSFET on, being C_a ≈ V_GSC_G/(V_DSoff –V_GS). Zener diodes should be used to protect the gate-source oxide. In Fig. 26.21b, the charge-holding gate capacitors are placed in a configuration where the m capacitor C_m should have the value C_m ≈ C_a(n − m + 1), n being the total number of MOSFETs and m > 1 [15].

For stacking IGBTs, care must be taken when designing the drivers of the totem pole IGBTs [20, 21]. The positive voltage of each driver can be obtained from the capacitor of the below R_SC_S snubber through a blocking diode connecting the resistor R_s to a turn-off MOSFET driving the IGBT [20, 21]. The C_s capacitor should hold the needed charge to turn-on the IGBT.

When dealing with cascodes, it is mandatory to minimize the source (or emitter) inductances as they can badly affect the charging rate of the gate capacitances. Bare chips (bare dice) and surface mount design should be used, instead of packaged MOSFETs, IGBTs, or SITs.

26.2.5.3 Parallel Stacks

Parallel associations of power devices can be used when the available semiconductors do not present the needed current ratings.

For positive temperature coefficient devices such as MOSFETs, SITs, and most of their derived structures, the devices can be just connected in parallel, taking care of symmetry to minimize stray inductances and capacitances and to balance junction temperatures. Individual gate drivers and protection circuits (except if stray effects are not a concern) should also be used. This is not valid for the MOSFET intrinsic diode, which must be disabled.

For negative temperature coefficient devices such as diodes, thyristors, bipolar transistors, GTO, and other bipolar devices, several methods could be used as follows:

FIGURE 26.22 Using transformers or coupled inductors for paralleling power devices: (a) two diodes; (b) modeling the parallel connection of two diodes; (c) and (d) two ways of connecting n-paralleled power semiconductors.

FIGURE 26.23 Parallel connections of power semiconductors using current sharing resistors.

One of the previous approaches has to be selected upon the pulsed power application to minimize costs and maximize performance.

26.4.1.1 Floating Switch

Consider the circuit in Fig. 26.26, where the HV power supply, PS, V_dc charges an energy storage capacitor bank C_dc. The PS internal resistance added by the switch and wiring ohmic resistances is represented by r_dc that limits the maximum charging current. Sometimes, a series inductor L_aux is also added, which acts as a current limiter and causes some boost of the capacitor voltage during the charging period.

The voltage is modulated into the load by the series floating switch Sp, which operates with duty ratio D. The switch-onand switch-off control applies the full bank voltage to the load with the pulse width and frequency being controlled by the gate trigger. Supposing C_dc charged with V_dc, when S_m is on, during t_on, the C_dc capacitor applies a voltage V_dc into the load. During this period, the inductance L_aux limits the discharge of the PS to the load.

If the load has capacitive behavior, an auxiliary circuit must be added to discharge the load capacitance to zero after the voltage pulse. For low duty ratio operation or low-power operation, a permanent parallel resistor R_a1 can be connected to the load, which must hold-off the applied voltage. The R_a1 value depends on its average power dissipation

(26.3)

and the required load voltage fall time.

As an alternative, for high duty ratio operation or high-power operation, it is preferable to use an auxiliary series switch S_a with R_a2 to short the load after the pulse. In this case, the value of R_a2 can be significantly reduced.

The main advantages of Fig. 26.26 topology are associated with the generation of voltage pulses with low rise time, low voltage droop, and also the flexibility to change the frequency and duty ratio operation. However, the pulse characteristics are limited by the energy stored in the capacitor bank and on the performance and power dissipated in the switches, and also on the rate of charge of C_dc.

The energy initially stored in the C_dc capacitor is

(26.4)

if the S off time, T –t_on, is enough for the PS V_dc to charge C_dc. Following, during t_on, the energy delivered to the load is

(26.5)

For PP applications, only a small fraction of the stored energy should be transferred to the output during the pulse mode, otherwise the pulse voltage has a typical RC discharge waveform, as shown in Fig. 26.27, and not an almost rectangular shape, as shown in Fig. 26.25.

FIGURE 26.27 Typical RC discharge waveform.

For a resistive load, the pulse voltage decay V_dcf can be calculated as

(26.6)

Considering a resistive load R_L, the capacitance of the C_dc capacitor (Fig. 26.26 circuit) can be determined according to energy delivered to the load. For the required pulse voltage droop Δ v₀,

(26.7)

where V_Cdcf is the capacitor voltage at the end of pulse, t_on, and V_Cdci is the capacitors voltage immediately before the pulse. Considering (26.7), the difference between (26.4) and (26.5) is the energy stored in the C_dc capacitor at end of pulse mode, E_Cdcf,

(26.8)

where (26.8) for this case results in

(26.9)

considering that V_Cdci = V_dc. Equating (26.9), the capacitor value should satisfy the condition

(26.10)

Considering (26.3) through (26.10), it is mandatory to store in C_dc an energy greater than five times the pulse energy in order to have an output voltage droop better than 10%, but if a 1% voltage droop is expected, a 50 times storage energy is required, which may impose limits to the design of the modulator.

In addition, the V_dc power supply must be able to recharge the C_dc capacitor with an energy equal to the delivered pulse energy, E₀, plus losses, during the charging, T –t_on, and pulse, t_on, periods

(26.11)

During the initial charging of the capacitor C_dc, the PS takes a longer time in order to limit the power dissipation in the R_dc resistor.

The main disadvantages associated with the circuit in Fig. 26.6 are the S_m switch floating trigger terminals, resulting in a trigger signal that must be transmitted with galvanic isolation. Also, switch S_m must hold the total V_dc voltage during the off period, T –t_on, and conduct the load current during the on period.

EXAMPLE 26.5 Consider the HV pulse modulator of Fig. 26.26, where V_dc = 20 kV. Calculate the value of the capacitor C_dc for applying 50 μs, 1600 Hz, into a R_L = 1 kΩ load, and the minimum power of the power supply, V_dc, considering 20% losses during the charging and pulse modes.

SOLUTION. Considering the capacitor C_dc initially charged with V_dc and a voltage droop of 5%, then (26.7)

which results (26.3)

Choosing a 1.2 μF, then the energy stored in C_dc initially is

The energy delivered to the pulse is

This means that after the pulse, the energy stored in the C_dc capacitor is 220 J, corresponding to a final pulse voltage of 19.149 V that is 4.2% voltage droop.

Finally, the PS V_dc must recharge the 20 J, plus 4 J (i.e., 20% losses) in T –t_on = 625 μs, then

26.4.1.2 Ground Switch

It is possible to connect the switch S_m referenced to ground and the C_dc capacitor floating as shown in Fig. 26.28. Considering Fig. 26.27 circuit, when S_p is off, the C_dc capacitor is charged through the load. Supposing C_dc charged with V_dc, when S_m turns on the positive terminal of C_dc is grounded and a voltage of V_dc is applied into the load.

The main advantage of Fig. 26.28 configuration in relation to Fig. 26.26 is that S_m is grounded, which makes the triggering process easier. However, in the Fig. 26.28 circuit, during the pulse period t_on, the V_dc power supply is shorted, increasing dramatically the power dissipation in R_dc, which is a significant disadvantage that limits the operation to very low duty ratios.

If inductive-type loads are to be connected in both circuits, it is mandatory to use a free wheeling diode in parallel with the load to reset it after the pulse and, also, to maintain the magnetic energy continuity.

26.4.1.3 Series Stacks of Semiconductors

Considering the dozens of kilovolt range pulse amplitude in the majority of pulsed power applications and the limited maximum reverse voltage of semiconductor switches, such as power BJT, MOSFET, IGBT, GTO, and IGCT, it is necessary to connect many semiconductors in series to assemble the S_m and S_a switches in Fig. 26.26 and Fig. 26.28, as shown in Fig. 26.29 [36–41].

FIGURE 26.29 Series-stacked semiconductor topology for high-voltage pulse generation.

As seen, sharing resistors for steady state and RCD snubber circuits for transient voltage balance are needed for on-off-controlled semiconductors. In addition, it is complex to synchronously trigger many devices in series, placed at different floating high-voltage potentials.

Gate-control delay techniques, or generalized cascades, are used to force the synchronized operation of semiconductors with mismatched switching on/off characteristics [42].

Nevertheless, in order to prevent shutdown of a series-stacked semiconductor switch due to a defect arising in one semiconductor, redundant switches are, usually, included in the series, about 20% more, such that the surviving semiconductors share the voltage and the failed semiconductor is still able to carry the load current. This is true since the power switches used are built to short circuit when failing [43].

In order to decrease the voltage hold-off stress on the semiconductors, it is possible to add a high-voltage step-up pulse transformer in the output, further increasing the output voltage to the desired amplitude. However, several following issues must be taken into consideration before designing the circuit [44–47]:

Some of the topologies used in power electronics, designed for dc–dc isolated converters, can be specially modified for pulse generation, where the addition of the transformer gives the galvanic insulation and contributes to the reduction of the hold-off voltage in the semiconductors as described in the following sections.

26.4.2.1 Forward Topology

The simplified forward-type circuit used to generate negative unipolar high-voltage pulses into a load is shown in Fig. 26.30 and the theoretical key waveforms are shown in Fig. 26.31. For positive unipolar pulses, the ground should be placed on the opposite secondary transformer terminal. The auxiliary RCD voltage clamp circuit connected to the transformer primarywinding is used to reset the transformer using the lowest constant voltage. Considering that the RCD clamp capacitance C_s is sufficiently large, the voltage V_c across it can be assumed constant [48, 49].

FIGURE 26.30 Simplified layout of the pulsed power forward-type circuit used to generate negative, high-voltage pulses to a load.

FIGURE 26.31 Theoretical key waveforms for the circuit in Fig. 26.30, for a resistive load: (a) switch-trigger signal v_gs; (b) primary winding voltage, v_i; (c) switch voltage v_s; (d) D₂ reverse voltage; (e) D₁ reverse voltage; and (f) load voltage v₀.

For pulse generation, the circuit operation can be explained considering only three operating modes [32, 50]. In the first mode, the pulse mode, when the main switch S is turned on during Δ₁ T = DT = t_on, where D and T are, respectively, the S duty ratio and operating period, the energy is transferred from the transformer primary winding circuit to the output. As the voltage applied to the transformer primary winding N₁ is V_dc, the secondary winding N₂ diode D₂ is on, thus the voltage applied to the load is

(26.12)

where N₂/N₁ is the transformer turns ratio, N. In addition, the RCD diode D₁ is off, with a reverse voltage of

(26.13)

For a resistive load R_L, the pulse amplitude is given by

(26.14)

In the second mode, the reset mode, when the main switch S turns off, the RCD diode D₁ goes on and the voltage applied to transformer primary winding is –V_C, which resets the transformer core. During this time, Δ₂ T, the secondary diode D₂ is off, holding off a reverse voltage of

(26.15)

which results into a zero-load voltage. From (26.15), the lower the V_C voltage and the transformer turns ratio N, the lower is the voltage hold-off by diode D₂. In addition, the switch S must hold-off a voltage

(26.16)

where V_C must be as low as possible to decrease this voltage.

Finally, in the third mode, the safety mode, following the transformer reset period, during Δ₃ T, still with S off, the voltage applied to S is

(26.17)

and the voltage applied to the transformer is zero. It is important to have Δ₃ T > 0 in order to guarantee a safety operating margin for the transformer core reset. For practical operation, values between 20% and 30% should be sufficient. This is done by increasing the V_C clamp voltage above the calculated value.

The operation of Fig. 26.30 circuit for high-voltage pulse generation imposes several conditions as follows:

Considering the second condition, it is important to understand the relation between the reset voltage V_C with the operating conditions, such as the duty ratio D.

The reset voltage V_C can be calculated by equating the integral of the primary winding voltage, v₁, over one time period to zero

(26.18)

where Δ₂ T = τ is the transformer core reset period.

For the boundary condition Δ₃ T= 0 (i.e., Δ₁ T + Δ₂ T = T and Δ₂ = D), (26.18) becomes

(26.19)

Substituting (26.19) in (26.15) results for v_ka in diode D₂ results in

(26.20)

Considering (26.18) and (26.20) and introducing the load voltage module |V₀| and the ratio of τ/t_off, the reset time and the time switch S is off, results in

(26.21)

Simplifying (26.21) becomes

(26.22)

which can be represented graphically by Fig. 26.32, where

(26.23)

with Δ₁ + Δ₂ + Δ₃ = 1 and Δ₁ = D.

FIGURE 26.32 Graphic representation of the reverse voltage of diode D₂ as a function of the reset time and duty ratio of the forward topology (26.30).

The graphie in Fig. 26.32 shows the maximum load voltage hold-off by diode D₂ as a function of S duty ratio, D, and the transformer reset factor, τ/t_off.

Various conditions can be presented for high-voltage pulse generation by forward converters using low-voltage solid-state devices as follows:

For safety reasons in order to ensure that the transformer core is fully reset, the transformer resetting time must end before the off state of the S switch ends, Δ₃ T > 0.

The short duty cycles required for generation of HV pulses with low-voltage semiconductors is not a shortcoming, as most PP applications require short-pulse widths and large recovery times.

Much care should be put in the design and assembling of the transformer as this element must sustain the HV between its terminals. In addition, this topology requires the polarity of the primary winding of the transformer to be identical to that of the secondary winding and so the energy of the load is obtained during the on-state of the switching device. Therefore, it behaves like a true transformer, wherein energy storage is undesirable, associated with the leakage inductance. However, the forward converter transformers have the poorest utilization and efficiency ratios, because neither the core nor the windings are used during the lengthy core reset interval.

Due to the low, main switch S duty-cycle operation and transformer behavior, the RCD clamp voltage is designed for a low current, typically, a few percent of the main circuit current.

The RCD clamp can be considered a buck-boost converter in discontinuous mode of operation, and designed so that, under any load conditions, during the S switch-off period, the transformer core is fully reset [49].

For resetting the transformer core, other solutions can be implementing, such as a third auxiliary winding, but the fact that this transformer is for HV pulse generation, limits in terms of parasitic, assembling complexity and safety.

EXAMPLE 26.6 Suppose the generation of–5 kV amplitude pulses with 5 μs and f = 10 kHz (D = 5%) from the circuit in Fig. 26.30. The circuit is supplied from a mains transformer at V_dc = 500 V and a N=10 pulse transformer is used. Calculate the semiconductor switches S, D₁, and D₂ hold-off voltage.

SOLUTION. Consider first boundary condition (26.19), then

The semiconductors hold-off at 526.3 V for the S switch and diode D₁, and 263 V for diode D₂, respectively, 10.5% and 5.26% of the output voltage.

Consider now a reset factor of τ/t_off ≈ 65%, then Δ₁ = 5%, Δ₂ ≈ 62.5%, and Δ₃ ≈ 32.5%. From (26.18)

resulting in 540 V for the S switch and diode D₁, and 400 V for diode D₂, respectively, 10.8% and 8% of the output voltage.

Hence, for generating 5-kV pulse, 800 V semiconductors could be used, considering a 100% safety factor.

26.4.2.2 Flyback Topology

The simplified flyback-type circuit used to generate negative high-voltage pulses into a load is shown in Fig. 26.33; for positive pulses, the ground should be placed on the opposite terminal.

FIGURE 26.33 Simplified layout of the pulsed power flyback-type circuit used to generate negative high-voltage pulses to a load.

The circuit in Fig. 26.33 is similar to the circuit shown in Fig. 26.30, but the polarity of the diode D₂ on the secondary winding is reversed. However, this simple change imposes completely different circuit behavior [48].

Considering the circuit in Fig. 26.33 and the theoretical key waveforms of Fig. 26.34, for boundary conditions, when the main switch S turns on, the energy is stored in the transformer as magnetic flux, the transformer must act as a coil storing energy. The voltage applied to the transformer primary winding is V_dc; the RCD diode D₁ and the secondary winding diode D₂ are off, thus the voltage applied to the load is zero. The secondary diode D₂ reverse voltage is

(26.24)

and the RCD diode D₁ reverse voltage is

(26.25)

FIGURE 26.34 Theoretical key waveforms for the circuit in Fig. 26.33, for a resistive load: (a) switch-trigger signal v_gs; (b) primary winding voltage, v₁; (c) switch voltage v_s; (d) D₂ reverse voltage; (e) D₁ reverse voltage; and (f) load voltage v₀.

When the main switch S is turned off, the energy stored in the transformer is transferred to the output. The voltage applied to the transformer primary winding is –V_C; the RCD diode D₁ and the secondary winding diode D₂ are on, and voltage applied to the load is, approximately,

(26.26)

The voltage hold-off the main switch S is

(26.27)

The RCD clamp voltage has two purposes: (1) reduce the voltage spike that occurs due to the resonance between the transformer leakage inductance and the switch S output capacitance, in the off state; and (2) establish the pulse voltage during the same period of time.

Considering the transformer primary winding voltage waveform given in Fig. 26.34, the clamp voltage, V_C, can be approximately derived by equating the integral of the primary winding voltage, v₁, over one time period to zero

(26.28)

similar to the V_C voltage in the buck-boost topology (26.19).

Concerning high-voltage pulse generation [50], if the switching duty ratio is near 100%, D₂ blocks only a small fraction of the output voltage. Additionally, if the RCD diode D₁ is on during the S switch-off time, meaning the flyback circuit runs in continuous mode, the output voltage pulse is well defined by the RCD capacitors voltage V_C. Moreover, with a step-up transformer (N 1), this topology also enables relatively low-voltage semiconductor devices in the primary side.

For efficiency reasons, the flyback circuit parameters should be calculated in order that the circuit works at the boundary between the continuous and noncontinuous state. This is done by assuring that the RCD diode D₁ turns off at the same instant the switch S turning on. The RCD clamp voltage is sized by the main circuit current due to the high duty ratio operation of switch S and the coil-like transformer behavior.

The flyback transformer design is more complex than the forward transformer, as the energy is supplied to the load during the off state of the S switch, meaning that the transformer must be designed to store energy during the on state of the S switch, behaving as a coupled inductor.

The S switch current interruption requirements and the coupled inductor design can be much more challenging in the flyback topology at power levels of interest and represent a limitation of this topology. This is normally the realm of much higher current devices such as the IGBT and GTO or the use of parallel semiconductors.

Nevertheless, the flyback circuit is much more fault tolerant to a short circuit in the load or load faults since the switch S is in the off state during the output pulse and will not see the fault current as would the forward converter topology.

Comparing the forward and flyback topologies for HV pulse generation for the same output voltage pulse amplitude, using the same turn ratio transformer, the forward circuits need a high amplitude dc PS voltage V_dc, but the RCD voltage is lower and the switch S duty ratio is low. Also, in the flyback topology, the voltage pulse width is not as well defined as in the forward because it is generated by the RCD circuit.

Both topologies have problems in dealing with capacitive loads because the dynamic variations in the load impedance mismatch the output of the transformer. The solution requires the use of a permanent dummy load, but this increases the power dissipation. Another possibility is the use of a switch dummy load, which will put a semiconductor device in the high-voltage region.

EXAMPLE 26.7 Suppose the generation of–5 kV amplitude pulses with 5 μs and f = 10kHz (D = 95%) from the circuit in Fig. 26.33. The circuit is supplied at V_dc = 25 V and a N=10 pulse transformer is used. Calculate the semiconductor switches S, D₁, and D₂ hold-off voltage.

SOLUTION. Consider (26.28), then

The semiconductors hold-off at 526.3 V for the S switch and diode D₁, and 263V for diode D₂, respectively, 10.5% and 5.26% of the output voltage.

Hence, for generating 5-kV pulse, 800 V semiconductors could be used, considering a 100% safety factor.

26.4.2.3 Bridge Topologies

The forward and flyback topologies are suitable for the generation of unipolar HV pulses. If bipolar pulses are needed, bridge configurations should be used, like the full- and half-bridge topologies with or without a step-up transformer [32–35].

Considering a half-bridge topology (Fig. 26.35a) shows the configuration for obtaining positive pulses, where the switch S₁ applies the pulse to the load, and switch S₂ is capable of applying a zero voltage to the load, which can be important if the load is capacitive, as shown in Fig. 26.35b, otherwise, the load will stay charged. If antiparallel diodes are connected to the switches, pulses can be applied to inductive loads, where the S₂ antiparallel diode reset the load after the pulse. For negative pulses, the circuit is presented in Fig. 26.36a, similar operating behavior applies now for opposite polarity, as shown in Fig. 26.36b.

FIGURE 26.35 Half-bridge topology for generating positive HV pulses; (a) simplified circuit and (b) output voltage, v₀, for a capacitive load, C_L//R_L.

FIGURE 26.36 Half-bridge topology for generating negative HV pulses; (a) simplified circuit and (b) output voltage, v₀, for a capacitive load, C_L//R_L.

The main limitation of this topology is the hold-off voltage of the semiconductors, which must block the same voltage as the dc HV power supply V_dc. If a transformer is connected in parallel with switch S₂, its antiparallel diode can reset the transformer core after the pulse, but this is limited to low duty ratio operation due to the low-reset voltage impose by the diode.

If positive and negative pulses (i.e., bipolar) need to be generated using a half-bridge topology, then two power supplies are required, as shown in Fig. 26.37. In this case, each switch S_i, must hold-off the sum of the two power supplies voltages, that is, 2V_dc. However, for capacitive-type loads, it is not possible to discharge the load capacitance after the pulse, as shown in Fig. 26.37b, since both S₁ and S₂ must be off.

FIGURE 26.37 Half-bridge topology for generating positive and/or negative HV pulses; (a) simplified circuit and (b) output voltage, v₀, for a capacitive load, C_L//R_L.

In order to decrease the switches voltage hold-off, it is common to use the full-bridge topology, shown in Fig. 26.38a, which also uses one less power supply. Each switch hold-off voltage is only V_dc. The use of more switches also increases the capability to deal with different load conditions, as shown in Fig. 26.38b. In fact, with the full-bridge topology, positive and/or negative pulses can be applied to any type of load. Nevertheless, depending on the flux of energy not all the controlled turn-off switches are always required.

FIGURE 26.38 Full-bridge topology for generating positive and/or negative HV pulses; (a) simplified circuit and (b) output voltage, v₀, for a capacitive load, C_L//R_L.

These topologies are used in applications such as rapid high-voltage capacitor charging, food processing, or air pollution control, where bipolar pulses enhance the process [26–30].

It is also possible to connect a transformer at the output terminals to increase the output voltage amplitude and to lower the hold-off voltage in the semiconductors switches if high-voltage pulses are to be generated, with the limitations already described. In order to limit the switches losses, it is common to use auxiliary inductors and capacitors in series or parallel configurations to couple the H-bridge to the HV transformer and also to guarantee a zero average voltage applied to the primary winding.

26.4.3.1 Circuit without Output Transformers

In the topology shown in Fig. 26.39, there is no transformer between the energy storing capacitors and the load, the system is composed of basic pulse generator cells, made by a capacitor C_i and a switch S_i, stacked in series. The challenge in this type of generator is the uniform distribution of the voltage between each cell due to the floating nature of each cells and the high dv/dt with respect to the ground occurring during the rise and falling time of the pulse. For this reason, great care must be taken in order to limit capacitance between each cell and the ground [17].

FIGURE 26.39 Series-stacked modulator topology.

For proper operation, the capacitors in each cell of Fig. 26.39 circuit need to be charged using a galvanically isolated power supply One of the possible methods includes the use of floating transformer secondary windings connected to an ac-dc converter, as shown in Fig. 26.39.

During the pulse period, the voltages of the individual cells are added up, hence the output voltage is

(26.29)

and the current through all the switches is almost the same.

The freewheeling diode D_i in the output of each cell enables the switch of each cell on and off independently of other cells, which makes the system capable of adjusting the output voltage. This technique protects also the switches during the on-off commutation transient for any mismatch in the voltage distribution, where the R_i resistors help on equalizing the voltage in the S_i switches during off-state (see Section 26.2.5, “Semiconductor Series, Parallel Stacks and Generalized Cascodes”).

26.4.3.2 Circuit with Output Transformers

The construction of a single, high-voltage pulse transformer, needing a high enough turns ratio (N > 1) to increase the output voltage, is complex due to the transformer’s nonideal behavior leading to significant parasitic effects as the output voltage rises. To solve this problem, it is possible to stack series several pulse transformers with lower turns ratio, in order to have only a fraction of the total voltage in each one [27, 51, 52]. With a careful design, the leakage inductance and distributed capacitances of the equivalent circuit are reduced as compared with one single equivalent transformer, leading to a better rise-time performance [53].

The most common ways to associate pulse transformers are shown in Fig. 26.40 [54]. The auto-transformer type cascade layout, is shown in Fig. 26.40a, with three transformers, each one holding one-third of the output voltage v₀

(26.30)

FIGURE 26.40 Simplified transformers association: (a) cascade; and (b) secondary windings in series.

In this topology, power is supplied to T_p2 and T_p3 from the previous transformers. Transformer T_p1 and T_p2 have three secondary terminals, two of them to feed the primary of the next transformer, and the third to step up the voltage of the next transformer. This configuration decreases significantly the distributed capacitive between windings.

The major advantage of the cascade association, of Fig. 26.40a, is that the isolation voltage between windings of each transformer is the same, and equal to v₀/3. However,

Alternatively, Fig. 26.40b presents three transformers with the secondary windings in series, each one designed for one-third of the output voltage v₀. In the primary side, windings are in parallel, supplied by v_in, and referenced to ground. Hence, the isolation voltage between windings of each transformer is different.

Considering Fig. 26.40b, although the secondary winding potential in transformer T_p2 and T_p3, is, respectively, increased by v₀/3 and 2v₀/3 through the secondary winding of transformer T_p1 and T_p2, in the primary windings the reference potential stays constant. As a result, each transformer holds a different voltage between windings, depending on the series position of each transformer, which increases toward higher potentials. Thus, transformer galvanic isolation between windings must be designed to v₀/3 for T_p1, 2v₀/3 for T_p2, and v₀ for T_p3.

The above-mentioned drawback sets serious difficulties for pulse applications of the Fig. 26.40b circuit. Since the pulse transformers placed at higher potentials hold higher voltages, the isolation distance should be increased. Consequently, the pulse waveform is distorted due to the increase of the parasitic leakage inductance with the isolation distance.

To overcome this problem, it is possible to feed the primary windings of the pulse transformers with galvanic isolated power supplies. This can be achieved with the introduction of isolation transformers, in order to keep the secondary windings of the pulse transformers in series, but with the same isolation voltage between windings. This solution has the immediate advantage that all the pulse transformers are similarly built, with the same minimum isolation distance, which helps to reduce the output pulse rise-time. Two configurations can be considered, Fig. 26.41, as follows:

FIGURE 26.41 Simplified layout of series-connected secondary windings transformers fed by (a) independent isolation transformers and (b) cascade isolation transformers.

For both circuits in Fig. 26.41, the secondary windings of the pulsed transformer are series connected, delivering each one (T_p1, T_p2, and T_p3 ), v₀/3 of the total output voltage v₀. In the circuit of Fig. 26.41a, the primary windings of T_p1, T_p2, and T_p3 are fed, respectively, by the secondary windings of the isolation transformers T_i1, T_i2, and T_i3, these ones being fed by the input voltage v_in. In this way, the pulse transformers T_p1, T_p2, and T_p3 can be assembled with the same structure and characteristics, for the same isolation voltage of v₀/3. The voltage increase due to the secondary winding series connection of T_p2 and T_p3 is sustained by the isolation transformer T_i2 and T_i3. Then, for the worst running condition (considering a high capacitance between primary and secondary of the pulse transformers), the galvanic isolation of T_i2 and T_i3 must be predicted to hold, respectively, v₀/3 and 2v₀/3. The isolation transformer T_i1 is not necessary.

In the circuit of Fig. 26.41b, the primary windings of T_p1, T_p2, and T_p3 are fed, respectively, by the secondary windings of T_i1, T_i2, and T_i3, with primary windings fed successively by the secondary windings of the previous transformer (i.e., T_i3fed by T_i2which is fed by T_i1, which is fed by v_in). In this way, the pulse transformers T_p1, T_P2, and T_p3 can be assembled with the same structure and characteristics, for the same isolation voltage of v₀/3. The voltage increase due to the secondary winding series connection of T_P2 and T_P3 is held by the isolation transformer T_i2 and T_i3 The isolation transformer T_i1 is not needed.

Taking into account the two circuits of Fig. 26.41 as follows:

Considering only the pulse transformers, the two topologies, in Fig. 26.41, are equivalent. Hence, the choice between the two should be based on the characteristics preferred for the isolation transformers and the features desired for the pulse generator.

Regarding the last, it is considered a great advantage for the high-voltage pulse generator to be of modular construction, built upon several equal modules, where each one could occupy any position in the generator.

EXAMPLE 26.8 Consider the generation of − 15-kV pulse from a series stack of three − 5 kV forward HV pulse generators based on the topology shown in Fig. 26.30, with the operating conditions of Example 26.6. Select the stack method to implement and draw the complete assembly, taking into consideration a modular perspective. Specify, also, the energy supply to the three stages, the selection of semiconductors and their triggering.

SOLUTION. The modular high-voltage generator construction is based on three main principles as follows:

The proposed circuit layout is shown in Fig. 26.42. If positive pulses are desired, it is only necessary to invert the polarity of the secondary diodes D_ri, where i ε {1,2,…, n}. Power is supplied to the three modules via isolation transformers (1:1), T_ii which must hold-off a maximum voltage of 1 k kV between primary and secondary. These transformers are assembled with primary windings in parallel, connected to a dc-ac high-frequency inverter to reduce the size and increase the efficiency of the system. In addition, each secondary winding is connected to an ac–dc rectifier that produces the necessary v_dci voltage to the forward converters.

FIGURE 26.42 Modular, pulsed generator simplified layout for − 15 kV output pulses.

Considering the − 5-kV voltage at each individual forward pulse generator with the operating condition of Example 26.3, then 800 V semiconductors can be used. Hence MOSFETs can be selected for switches S_i.

Considering the three modules, in Fig. 26.42, with switch S_i on, diodes D_ri are conducting, and the voltage applied to the load is

considering three equal modules, v₀₁ = v₀₂ = v₀₃ = v_{0 i}. During this time, the voltage reference at the secondary terminal with a dot point of each pulse transformer is raised

During the off time of switches S_i the voltage applied to the load goes to zero, diodes D_ri in each module hold-off only the reset voltage of their respective pulse transformer. Voltage-sharing resistors, R_si, are used to equally distribute the reset voltages of each module through diodes D_ri. In order to hold the high-voltage potential in each module relative to ground, high-valued R_di resistances can also used.

Regarding the triggering of the MOSFETs in each stage, dc isolated power supplies are used in each stage to supply the necessary energy to the trigger drives that receives the signals by optic fiber from the ground control circuit.

26.4.4.1 Generation of Negative Pulses

During the last years, various semiconductors based on Marx, SM, and topologies have been described, with analogous characteristics in order to reduce the losses and increase the performance of the circuit for different types of applications and loads [56–59].

Figure 26.44 shows a typical SM topology, with n stages, able to deliver negative high-voltage repetitive pulses into a load R_L, the theoretical key waveforms are shown in Fig. 26.45. Each stage of the SM consists of a energy storing capacitor C_i, a diode D_ci, and two switches S_ci and S_pi, with antiparallel diodes, where the subscript i ε {1,2,…, n–1, n, n+ 1}. The Si switches can be implemented with BJTs, GTOs, IGCTs, IGBTs, MOS-FETS, or other on-off devices. The inclusion of S_c1 guarantees that during the pulse period, the dc charging power supply V_dc is not short-circuited, preventing high current load pulses through the power supply.

FIGURE 26.44 Circuit for applying HV-negative repetitive pulses into resistive load.

FIGURE 26.45 Theoretic waveform for the operation of the circuit in Fig. 26.44: (a) trigger signal of switches S_pi, v_gs(Spi); (b) trigger signal of switches S_ci, v_gs(Sci); (c) output voltage, v₀ ; and (d) output current, i₀.

Considering resistive load, R_L, the operation of the Fig. 26.44 modulator can be understood considering two operating modes, for a switch duty ratio D=t_on/T. In the first one, switches S_ci and S_pi are, respectively, turned on and turned off. During the charging period, (T-t_on), capacitors C_i are charged from the dc charging power supply, V_dc, with current limited by the internal resistance of the semiconductors, wires, and the dc charging power supply internal resistance (or externally added) r_dc, resulting in a small time constant that enables kHz operation. The on-state of D_ci ensures that during this period, the voltage, v₀, applied to the load is, approximately, zero.

In the second operating mode, switches S_ci and S_pi are, respectively, turn-off and turn-on. During the pulse mode, t_on, capacitors C_i are connected in series and their voltage applied to the load. The load voltage v₀ is proportional to the charging power supply

(26.32)

where n is the number of stages, and k < 1 characterizes the nonideal behavior of the passive and active elements in the circuit and operating conditions.

The D_ci diodes guarantee, also, that the S_pi switches only block a maximum voltage of V_dc, even in fault condition, such as lack of synchronization. Considering Fig. 26.44, for example, if switch T_pn is off during pulse mode, D_cn conducts and short circuits the last stage, imposing an output voltage of

(26.33)

The operation of Fig. 26.44 circuit can be represented by its equivalent model during both operating modes, considering ideal switches and C_i = C. During the charging mode, the C_i capacitors are in parallel, and the circuit can be modeled as shown in Fig. 26.46a, where nC is the equivalent capacitance, seen by the power supply, charged with V_dc. In addition, during pulse mode, the C_i capacitors are in series, where C/n is the equivalent capacitance, seen by the load, charged with nV_dc, as shown in Fig. 26.46b.

FIGURE 26.46 Equivalent circuit of Fig. 26.44: (a) the charging mode; and (b) the pulse mode, for negative output pulses.

The energy stored in the C_i capacitors, during T –t_on, is

(26.34)

and the energy delivered to the load, during t_on, is

(26.35)

For pulse power applications, only a small fraction of the stored energy should be transferred to the output during the pulse mode; otherwise, the pulse voltage has a typical RC discharge waveform, not an almost rectangular shape. Considering a resistive load R_L, the capacitance of the C_i capacitors in the Fig. 26.44 circuit can be determined according to energy delivered to the load. For the required pulse voltage droop,

(26.36)

where V_Cf is the capacitors voltage at the end of pulse mode, t_on, and V_Ci is the capacitors voltage immediately before pulse mode. Considering (26.36), the difference between (26.34) and (26.35) is the energy stored in the C_i capacitors at end of pulse mode, E_Cf,

(26.37)

where (26.37) for this case results in

(26.38)

Assuming that V_ci = V_dc. Equating (26.38), the capacitor value should satisfy the condition

(26.39)

Considering (26.34) through (26.39), it is mandatory to have storage energy greater than five times the pulse energy in order to have an output voltage droop better than 10%, but if a 1% voltage droop is expected a 50 times storage energy is required, which impose limits to the design of the modulator.

The power dissipation in the switches and the capacitors charging time impose a high-voltage pulse frequency limitation. Therefore, this circuit operates better with low duty ratio, D, pulses as required in most PP applications.

In addition, the V_dc power supply must be able to charge the C_i capacitors with an energy equal to the delivered pulse energy, E₀, plus losses during the charging time, T –t_on.

(26.40)

where the P_loss term represents the power dissipated in the circuit wiring and switches.

This determines the maximum power rating for the V_dc power supply that imposes the maximum operating frequency, pulse duty ratio, and load power to the modulator.

To build and operate the circuit of Fig. 26.44, some design consideration must be considered. First, during start-up, when the energy storing capacitors are completely discharged, the charging voltage V_dc must be slowly increased in order to limit the charging current on the switches S_ci and D_ci, which is critical in the first stages due to the parallel charging topology of the capacitors.

Actually, in the parallel charging method, the semiconductor modules current loading is not equal. For instance, in Fig. 26.44 circuit, switch S_c1 conducts current required to capacitors C₁, C₂,…, C_n-1, C_n, and switch S_c2 conducts charging current for C₂, C₃,…, C_n-1, C_n, and so forth. Thus, in practical implementation, modules with successive decreasing current ratings can be used, the benefits of standardization being somewhat compromised.

Also, the S_ci and S_pi switches conduct different current values, respectively, the discharge and pulse current. Hence, instead of switches needing to block unequal voltages, they are required to conduct unequal currents.

Consequently, when choosing semiconductors to implement the S switches, it is fundamental that the semiconductor current rating must be selected to guarantee that the devices work always in the saturation region inside the forward safe operating area. If not, during the first instants of the on-state (when the current is high), the semiconductors can operate in the active region where the voltage drop and losses are higher, which might destroy the devices.

The switches triggering is another important concern in these circuits. There are two drive signals, V_gs(Spi) and V_gs(Sci), respectively, to S_pi and S_ci, which should be triggered synchronously. Since all the semiconductor switches are at different high-voltage potentials, gate-drive circuits with galvanic isolation are required (the use of optic fibers is mandatory to transmit the gate signals and to reduce stray capacitances to ground and neighbor cells), together with isolated power supplies to further process the transmitted gate signal and supply power to the gate drivers.

Several authors have come up with solutions to supply power to semiconductor triggering drivers for high-voltage applications. The most common include isolation transformers [60], but diode strings are also described [58].

The circuit in Fig. 26.44 enables the use of typical half-bridge semiconductor structures currently integrated in modular packages, which is advantageous to assemble the circuit and trigger the semiconductors, since it allows bootstrap operation [10].

However, the circuit topology shown in Fig. 26.44 is not suitable for dealing with capacitive loads. In fact, if a capacitive-type load is connected to the circuit output, the load stays charged after the HV pulse with a negative voltage until the charging mode of the energy storing capacitors. However, during the charging period, the load is not shorted by the D_ci, except if the energy stored in the load is very low and the charging current of capacitors C_i is sufficient to turn-on diodes D_ci.

In order to guarantee the discharge of the load capacitances after the negative HV pulse, it is necessary to change the Fig. 26.44 circuit topology for the one shown in Fig. 26.47, which also produces negative HV pulses into the load.

FIGURE 26.47 Circuit for applying HV-negative repetitive pulses into a capacitive load, with a negative dc power supply, V_dc.

Considering the circuit in Fig. 26.47, as the V_dc power supply is negative, it is necessary to change the topology in comparison with Fig. 26.44 in order to maintain a similar operating behavior. The two main differences are the addition of an extra switch, S_c0, which guarantees that, during the pulse period, the dc charging power supply V_dc does not participate in the pulse mode, t_on. The most important regards the fact that during the charging period, T –t_on, the S_ci switches short circuit the load discharging any capacitance, as the one shown in Fig. 26.47.

Considering now the application of negative HV pulses into inductive loads, the circuit in Fig. 26.44 requires an additional half-bridge switching structure that connects to the load, as shown in Fig. 26.48.

FIGURE 26.48 Circuit for applying HV-negative repetitive pulses into an inductive load.

As shown in Fig. 26.49, the operation of the circuit in Fig. 26.48 in comparison with circuit in Fig. 26.44 as some changes, which includes one additional time period for enabling the reset of the inductive load by the freewheeling diodes, t_ab, besides the charging, t_c, and pulse modes, t_on, in order to impose a zero average voltage to the load.

FIGURE 26.49 Theoretic waveform for the operation of the circuit in Fig. 26.48: (a) trigger signal of switches S_pi, v_gs(Spi) ; (b) trigger signal of switches S_ci, v_gs(Sci); (c) output voltage, v₀ ; and (d) output current, i₀.

During the charging period, the on-state of D_ci and the S_{p(n+ 1)} antiparallel diode ensures that the output voltage, v₀, applied to the load is approximately zero.

After the HV-negative pulse, t_on, the S_ci and S_pj switches are turned off, but in order to conserve energy, the inductiveload current, i₀, must have an alternative path. This path is set by freewheeling diodes (S_ci antiparallel diodes and D_ci diodes) and the capacitor with the lowest voltage, which is charged. Normally, C_n has the lowest voltage, thus the current path is through the S_{c(n+ 1)} antiparallel diode D_B, capacitor C_n, and diodes D_c1 to D_cn. During this time, t_a, the voltage applied to the load is, about, V_dc (voltage in capacitor C_n), resetting the inductive load. Capacitor C_n is charged until its voltage is equal to the capacitor C_n–1 voltage, after which, if there is still energy in the load, the current path changes to capacitor C_n-1. As the maximum clamping voltage is V_dc, the higher the number of stages the longer the resetting time.

In this way, most of the load magnetic energy is sent back to energy storing capacitors C_i, after which the load current i₀ goes to zero and it can be imposed again the charging mode of operation. It is important to have a safety time t_b in order to guarantee the completely reset of the load. Due to this load energy recovery method, the power supply energy needed to charge the capacitors after each pulse is lower, and the yield of this modulator can be higher.

EXAMPLE 26.9 A negative solid-state Marx generator needs to be assembled for delivering –9 kV, 25 µs pulses into a 900 Ω resistive load, with less than 20% voltage droop. Considering the existent equipment, there are two alternatives as follows: (1) V_dc= 1.5 kV, n = 6, and C_i=l µF; (2) V_dc=l kV, n = 9, and C_i=l µF. Determine which is the best alternative.

SOLUTION. Considering the capacitance of 1 µs in each stage, then the pulse voltage droop can be determined by (26.39). Hence, for the first alternative

and for the second alternative

which gives, respectively, 18.35% and 29.23% voltage droop, meaning that after the pulse the capacitors stay charged with about (26.36), respectively, 1224.7 and 707.1 V. Hence, only the first alternative keeps the pulse voltage droop below 20%. In this case, the energy stored in the capacitors is (26.34) 6.75 J, three times bigger than the energy delivered to the load during each pulse (26.35) 2.25 J.

26.4.4.2 Generation of Positive Pulses

The solid-state Marx modulators for generating positive HV pulses, with different load conditions, have equivalent properties as the ones for negative pulses, shown in the previous section, besides the necessary modifications to enable the change in the output polarity. Thus, Fig. 26.50 shows the basic topology of the SM, with n stages, able to deliver positive high-voltage repetitive pulses into resistive and capacitive loads, R_lC_l.

FIGURE 26.50 Circuit for applying HV-positive repetitive pulses into resistive and capacitive loads.

During the pulse mode, t_on, the switches S_ci and S_pi are, respectively, turned off and turned on. Capacitors C_i are connected in series and their voltage applied to the load. The load voltage vq, is proportional to the charging power supply,

(26.41)

where n is the number of stages, and k < 1 characterizes the nonideal behavior of the passive and active elements in the circuit and operating conditions. Also, in this topology, for example, if S_pn is off during pulse mode, the antiparallel S_cn diode conducts and short circuits the last stage, imposing an output voltage of

(26.42)

Actually, the Fig. 26.50 circuit is equivalent to Fig. 26.44 circuit, whereas in this case, with a positive V_dc power supply, it can produce positive HV pulses for both resistive and capacitive loads. The capacitive load can be driven, given that during the charging mode of capacitors C_i, the load is short circuited by the S_ci switches, stray inductances limiting the discharge rate.

Considering now the application of positive HV pulses into inductive loads, the circuit in Fig. 26.50 requires an additional switch Sp₀ and diode D₀ at the input, as shown in Fig. 26.51.

FIGURE 26.51 Circuit for applying HV-positive repetitive pulses into an inductive load.

The circuit operation requires, also, an additional time period for resetting the inductive load by the added freewheeling diodes, t_ab, in addition to the charging, t_c, and pulse modes, t_on, in order to impose a zero average voltage to the load.

Considering an inductive load, after the HV-positive pulse, the S_ci and S_pi switches are off, and the path for the inductive current i₀ is set by the capacitor C_n, which usually has the lowest voltage, the S_ci antiparallel diode and diode D_B. During this time, the voltage applied to the load is approximately –V_dc (the voltage in capacitor C_n), resetting the inductive load. After the load current i₀ goes to zero, the charging mode of operation can be imposed.