Topic II: Modeling

“All models are wrong, but some are useful.”

—George Box

The design methodology for a complex SoC is based fundamentally on a diverse set of models used to represent the logic functionality and the electrical response of the fabricated silicon. These models are provided to EDA software tools that simulate and analyze the design behavior. The functional models originate from the SoC design team and the IP library vendor. The circuit electrical models are derived from the basic device and interconnect models provided by the foundry in the PDK release. The electrical models are commonly abstracted to the level of the library cell as the output of the library characterization flow. This part of the text describes key features of the models used in the SoC methodology.