Topic III: Design Validation

The evolution of VLSI process nodes enables system architects to integrate an increasing number of functional blocks into a single SoC chip design. The complexity and diversity of the IP blocks is growing, as well. There are a greater number of concurrent operations in flight at any time, resulting in blocks contending for shared memory resources and bus interface bandwidth. To address product markets requiring low power dissipation, the SoC design must support a growing number of clock and power domains with multiple power modes and intricate power state transitions. As a result, the validation of the SoC functional model is a demanding task.

The resources applied to preparing the functional validation plan, composing and executing testcases on the model, measuring testcase coverage, and debugging testcase failures is the largest contingent of the SoC development expense. It is crucial that the productivity and efficiency of the validation team is optimized. This part of the text describes the functional validation methodology steps used throughout the SoC design schedule. In addition, the flow steps to prove functional equivalence between two models are discussed.

There are ongoing industry-wide initiatives to provide standards for testcase structure and to release the corresponding software libraries into the public domain. The primary goals are to reduce the time required to develop the testcase suite and to enable EDA tool vendors to optimize simulation model compilation and execution. The detailed nature of these object-oriented programming class-based testcase generation software functions is beyond the scope of this text; the reader is encouraged to review the references and future research recommendations at the end of Chapter 5.