Topic V: Electrical Analysis

After the design implementation of a block is complete, the layout database is presented to the electrical analysis flows to determine the suitability for sign-off to fabrication. The initial step in electrical analysis is to extract accurate interconnect parasitics, replacing the existing estimates used in physical design optimization algorithms. The new network model with the annotated parasitics is then submitted to the breadth of analysis flows, to evaluate path timing, coupled noise, power dissipation, and electromigration reliability.

The results of block-level electrical analysis are used to generate abstracts for subsequent global evaluation. An exception to the use of block abstract models for global analysis is typically made for the full-chip power and ground distribution grids, to ensure that I*R voltage drop and electromigration current density limits are observed.

A number of electrical analysis flows are applicable to specific IP block types. The electrical model for the power state transient that connects and disconnects the power/ground distribution to a block requires a specific type of circuit simulation. Memory arrays are susceptible to the disruption of a stored bit value from external radiation, necessitating an analysis of the probabilistic soft error rate. Chip I/O circuits may be subjected to an electrical stress condition applied at the package pins. An analysis of the electrostatic discharge protection circuitry connected to the I/O pad is required.

The results of the electrical analysis flows are captured in the methodology manager application, to be monitored closely by the SoC project management team. Electrical issues identified by the analysis flows may require design iterations, commonly with an engineering change (ECO) that minimally disrupts the existing implementation. If the magnitude and number of analysis flow errors are significant, a full implementation iteration loop may need to be pursued with the corresponding impact to the project schedule and resources.