Topic IV: Design Implementation

This section of the text describes the methodology flow steps associated with the translation of the functional model of a VLSI design block to a completed physical implementation. Chapter 7 focuses on the logic synthesis of the functional description to a target technology cell library. Logic optimization algorithms are applied to the functional model to optimize the resulting cell netlist. Additional optimization algorithms are employed that evaluate the cell-level model against performance, power, and clocking constraints provided as inputs to the synthesis flow. Logic synthesis will iterate on the cell selection and signal fan-out repowering topologies to address these constraints.

Chapter 8 discusses the placement of the netlist cells on the floorplan image allocated for the design block.

Chapter 9 focuses on the completion of the netlist interconnect routes between cell pins. Throughout these design implementation flows, the estimation of interconnect electrical parasitics is a crucial aspect of the optimization algorithms, and is discussed in detail.