- Cover Page
- About This eBook
- Title Page
- Copyright Page
- Dedication Page
- Contents at a Glance
- Contents
- Preface
- About the Author
- Topic I: Overview of VLSI Design Methodology
- I.1 Methodology Guidelines for Logical and Physical Design Hierarchy Correspondence
- I.2 Managing Inter-Block Glue Logic
- Chapter 1. Introduction
- Chapter 2. VLSI Design Methodology
- 2.1 IP Design Methodology
- 2.2 SoC Physical Design Methodology
- 2.3 EDA Tool and Release Flow Management
- 2.4 Design Methodology “Trailblazing” and Reference Flows
- 2.5 Design Data Management (DDM)
- 2.6 Power and Clock Domain Management
- 2.7 Design for Testability (DFT)
- 2.8 Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) Requirements
- 2.9 Design Optimization
- 2.10 Methodology Checks
- References
- Further Research
- Chapter 3. Hierarchical Design Decomposition
- 3.1 Logical-to-Physical Correspondence
- 3.2 Division of SRAM Array Versus Non-Array Functionality
- 3.3 Division of Dataflow and Control Flow Functionality
- 3.4 Design Block Size for Logic Synthesis and Physical Design
- 3.5 Power and Clock Domain Considerations
- 3.6 Opportunities for Reuse of Hierarchical Units
- 3.7 Automated Test Pattern Generation (ATPG) Limitations
- 3.8 Intangibles
- 3.9 The Impact of Changes to the SoC Model Hierarchy During Design
- 3.10 Generating Hierarchical Electrical Abstracts Versus Top-Level Flat Analysis
- 3.11 Methodologies for Top-Level Logical and Physical Hierarchies
- 3.12 Summary
- References
- Further Research
- Topic II: Modeling
- Topic III: Design Validation
- Chapter 5. Characteristics of Functional Validation
- 5.1 Software Simulation
- 5.2 Testbench Stimulus Development
- 5.3 Hardware-Accelerated Simulation: Emulation and Prototyping
- 5.4 Behavioral Co-simulation
- 5.5 Switch-Level and Symbolic Simulation
- 5.6 Simulation Throughput and Resource Planning
- 5.7 Validation of Production Test Patterns
- 5.8 Event Trace Logging
- 5.9 Model Coverage Analysis
- 5.10 Switching Activity Factor Estimates for Power Dissipation Analysis
- 5.11 Summary
- References
- Further Research
- Chapter 6. Characteristics of Formal Equivalency Verification
- 6.1 RTL Combinational Model Equivalency
- 6.2 State Mapping for Equivalency
- 6.3 Combinational Logic Cone Analysis
- 6.4 Use of Model Input Assertions for Equivalency
- 6.5 Sequential Model Equivalency
- 6.6 Functional and Test-Mode Equivalence Verification
- 6.7 Array Equivalence Verification
- 6.8 Summary
- References
- Further Research
- Chapter 5. Characteristics of Functional Validation
- Topic IV: Design Implementation
- Chapter 7. Logic Synthesis
- 7.1 Level of Hardware Description Language Modeling
- 7.2 Generation and Verification of Timing Constraints
- 7.3 Technology Mapping to the Cell Library
- 7.4 Signal Repowering and “High-Fan-out” Net Synthesis (HFNS)
- 7.5 Post-Synthesis Netlist Characteristics
- 7.6 Synthesis with a Power Format File
- 7.7 Post-Technology Mapping Optimizations for Timing and Power
- 7.8 Hold Timing Optimization
- 7.9 Clock Tree Synthesis (CTS)
- 7.10 Integration of Hard IP Macros in Synthesis
- 7.11 Low-Effort Synthesis (LES) Methodology
- 7.12 Summary
- References
- Further Research
- Chapter 8. Placement
- Chapter 9. Routing
- Chapter 7. Logic Synthesis
- Topic V: Electrical Analysis
- Chapter 10. Layout Parasitic Extraction and Electrical Modeling
- Chapter 11. Timing Analysis
- Chapter 12. Noise Analysis
- Chapter 13. Power Analysis
- Chapter 14. Power Rail Voltage Drop Analysis
- Chapter 15. Electromigration (EM) Reliability Analysis
- Chapter 16. Miscellaneous Electrical Analysis Requirements
- Topic VI: Preparation for Manufacturing Release and Bring-Up
- Epilogue
- Index
To Pat, for his inspiration
and
To Martha, who loved to write
-
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