Topic VI: Preparation for Manufacturing Release and Bring-Up

The initial chapters in this topic describe the steps for the preparation of the full-chip SoC design database to release to the foundry for fabrication. Chapter 17 discusses the application of an engineering design change (ECO) to the chip database, a change request that arises after the database has completed the design freeze project milestone. The characteristics of the ECO methodology flows are unique, as a primary goal is to implement the change with a minimal disruption to the existing physical design database. Chapter 18 reviews the physical verification of the database to the foundry PDK checking runsets to ensure manufacturability and yield. Chapter 19 discusses various approaches to the generation of the manufacturing test patterns to be applied by the foundry and the package assembly service provider. In all these cases, specific EDA tool algorithms have been developed to efficiently manage the data volume of the full-chip design.

Chapter 20 covers the project management tasks associated with the tapeout release to the foundry. This critical milestone requires stringent review of the information recorded in the methodology manager application. The project management team needs to assess the quality of the design as reflected by the results of functional validation, test pattern generation, and the electrical analysis flows.

Chapter 21 describes the activities undertaken by the engineering “bring-up” team. This team exercises the prototype silicon received from the foundry, pursuing performance measurements and verifying circuit behavior at extended environmental conditions. These electrical and thermal stress experiments are intended to identify any issues with design robustness and product lifetime. Successful completion of these experiments qualifies the design to proceed to production fabrication and product volume ramp.