11.4.1 Timing Slack Calculation

A signal arrival time that fails a test at a timing path endpoint is indicative of the need to make an engineering change to the physical design. However, in a large network with potentially many failing tests, the SoC designer would need additional insight into where to focus timing optimizations. The concept of timing slack is used to identify the criticality of all input and output cell pins in the timing model, as depicted in Figure 11.12.

The forward propagation of calculated cell and interconnect delays provides the arrival time (AT) at each pin. The timing test involves a comparison between the AT and the required arrival time (RAT) at the path endpoint. In late mode, the endpoint RAT is derived from the setup time constraint, the clock period specification, the clock launch-to-capture skew, and clock jitter margin. If the network timing model were to be traversed in reverse levelized order from the endpoint RAT, subtracting the cell and interconnect delays, a specific RAT value could be assigned to each pin internal to the network.

For a cell output pin, the late mode RAT is the “earliest” required time traversing back from the fan-out pins through interconnect delays. The (RAT – AT) difference at each pin is denoted as the (late mode) timing slack. A positive slack indicates a forward propagation arrival time that precedes its required arrival time, as derived from the backward calculation from all timing path endpoints. A negative slack indicates an arrival time that is later than its required arrival and, thus, needs to be addressed.

In early mode, the AT propagation uses minimum path delay calculations, as depicted in Figure 11.11. The RAT at the timing endpoint is based solely on the clock skew, clock jitter, and hold time constraint of the flop cell. For early mode timing analysis, the timing slack is the (AT – RAT) difference. If the AT is earlier than the RAT, the timing slack is negative, and a hold time error is reported. A similar backward calculation through the network using the “latest” required time through fan-out interconnect delays determines the RAT and the early mode slack at all cell output pins.

The advantage of the timing slack formulation is that it quickly identifies the cells internal to the network that have a large sensitivity to timing closure (see Figure 11.13).

Cells with a large negative slack are the primary candidates for (late mode) timing optimizations:

• Update the cell drive strength.

• Update the cell V_t selection.

• Restructure the cell netlist to implement different fan-out repowering.

• Modify the wire layer/width/spacing for segments in the fan-out interconnect tree.

If the fan-out tree from a negative slack cell has a wide range of slacks, offloading non-critical fan-out may significantly improve the overall timing closure, as illustrated in Figure 11.14.

EDA vendor STA tools offer an interactive session feature, with access to the existing timing model and the results from the STA flow. In addition to allowing the querying of the timing results data, the interactive environment allows the designer to inject timing model changes, such as the candidate cell swaps listed above. An incremental timing feature can assess the impact of the model edits on the timing results; for fastest response, the scope of the timing recalculation is limited rather than striving for highest accuracy with a full model recalibration. The output of interactive timing debug would be to generate a set of netlist ECOs that could be applied to the physical implementation. Cell and/or fan-out repowering changes would be placed, cell overlaps resolved, and affected routes updated.

11.4.2 Pin Constraints for STA

The timing paths for tests involving model PIs and POs utilize constraint data similar to that provided for the synthesis flow (see Section 7.2). The distinction for STA is that the actual clock arrival data are used as the timing test reference rather than the idealized clock latency and skew targets used during synthesis.

11.4.3 STA “Don’t Care” and “Adjust” Specifications

STA does not evaluate the logic functionality of the timing model (except the unateness) as part of the comprehensive approach to forward propagation of all potential network paths. As a result, there may be paths that are logically invalid. To exclude these paths, a directive to the STA flow indicates a timing don’t care (also known as a false path). The STA false path constraint would indicate the connections in the levelized timing graph for which propagation is not performed (e.g., a specific path with “from-through-to” pins or a larger sub-graph with “from-to” pins). Reference 11.9 describes an algorithm for efficiently removing edges in the timing graph, given a false path specification. Note that it is necessary to update the timing graph for false paths after delay calculation; the loading of the false path pins is included in the cell and interconnect delays, but the (max, min) arrival propagation step omits the false path cells. The SoC methodology should ensure that any false paths submitted to timing analysis are independently verified to avoid exclusion of a timing path that is indeed exercisable. Formal property verification would be appropriate to prove the validity of the false path constraint.

Another input constraint to the STA flow would be the identification of any multi-cycle paths (i.e., paths between testpoints that are by design expected to exceed the cycle time period specification), as illustrated in Figure 11.15.

In the figure, correct functionality is maintained when the capture flop is updated every other clock cycle. To present this case to the propagation phase of the STA flow, a delay adjust constraint is given; essentially, an artificial cell is added to the timing graph in the combinational data network with a “negative propagation delay” value. To test a two-cycle path, a delay adjust equal to one clock period would be added. The location in the timing graph for the delay adjust needs to be selected judiciously, as sub-graphs in the timing model may be part of both single- and two-cycle paths. Similar to the false path constraint, any multi-cycle delay adjusts provided to the STA flow should also be independently verified.

11.4.4 Timing Analysis Modes

In general, STA is performed without evaluation of the logic functionality of the netlist model. However, in some cases, an operating condition for the timing model defines a specific set of timing tests to be performed. Section 7.2 first introduced the concept of multi-mode analysis, in the context of timing-driven synthesis. Similarly, the STA flow can support functional modes. Logical values are assigned to specific signals in a separate mode file, along with related clock period and PI/PO constraints. These assigned values are functionally simulated to establish specific timing model paths for propagation.

The most general cell timing models may include state-dependent delays, where an input-to-output pin arc has multiple representations, based on specific logic values assigned to other pins during characterization. If this modeling approach is used, a timing mode requires recalculating delays before propagation and slack calculation.

A common use of a timing mode is to evaluate the paths associated with scan-shifting during test operation, as shown in Figure 11.16. The shift clock frequency from the tester is typically much slower than the system clock, and with the relatively short scan logic paths, setup time checking should be straightforward. The emphasis in the test timing mode would be on hold time checking, using the skew and jitter for the test clock distribution to calculate the RAT at each flop endpoint.

Another common application of timing modes relates to unique timing tests associated with an embedded IP macro. The macro timing model from the IP vendor could include multiple sets of timing constraints, whose values depend upon the specific operation being performed. For example, an embedded SRAM array may have different address/data setup constraints to the array enable input for a read operation compared to a write access. The SoC timing team needs to develop the static timing analysis modes and timing model inputs to enable verification of the different operations.

11.4.5 Reporting

The output reports from the STA flow offer (extremely) detailed delay and slack data for all pins, for all corners and modes. The first debug step is to sanity check the results. For example, a negative slack (of significant magnitude) may be indicative of a multi-cycle adjust that may have been inadvertently omitted or an additional timing mode that needs to be defined. The next step would be to explore potential updates to the timing model, using the EDA vendor’s interactive model viewer with incremental timing recalculation. From the updates to the model, an ECO netlist would be exported for physical implementation.

The design team may request a review of critical timing paths with the SoC methodology and CAD teams. There is potentially sufficient conservatism in the STA propagation method to warrant additional analysis of a failing path. A common feature of EDA vendor STA tools is to export a detailed netlist of a specified critical path—excising the cells, RC interconnect tress, side loads, and clock distribution. Note that the excised circuit simulation netlist requires attention to the k-factor applied to the coupling capacitances, which have been grounded for STA delay calculation. This netlist would be submitted for circuit simulation (at the corners of interest) to provide a more precise arrival time.

The results of the timing analysis flow are summarized in the project management scoreboard. A number of different results representations are commonly used—for example, the worst negative slack (WNS), the total negative slack summed for all failing paths (TNS), and a graphical distribution of all slack values (positive and negative) at timing test endpoints. The slack distribution is the most informative. For example, if a large number of failing paths are present, with small negative slack, the resources required to explore individual cell updates will be substantial. A review of other potential, more pervasive approaches would be warranted, such as a supply voltage increment, changes to the clock distribution to reduce the arrival skew, or modification of the design assumptions to adopt a useful skew implementation. As the tapeout schedule is likely fast approaching, the SoC and methodology teams need to be prepared to quickly address the possibility of a negative slack “timing wall” in the timing analysis path distribution curve. Finally, the review of the timing reports may result in waivers (due to assumed conservatism in timing margins), allowing the STA flow to be logged as “complete” in the SoC project management scoreboard.

11.4.6 Variation-Based Timing

The sources of manufacturing variation are more diverse in advanced process nodes, from interconnect RC tolerances due to CMP, to FinFET device fabrication parameter distributions, to layout-dependent effects. Parameter variations are derived from testsite data, measured across wafer lots, within each wafer, and within each die. As a result, the variations are typically associated with “global” and “local” distributions, as shown in Figure 11.17. The global and local n-sigma variation models used for library timing characterization are derived from measurements on device currents and extended to cell delay arcs. The figure depicts the statistical distribution of a cell delay arc at a specific voltage and temperature due to fabrication variations.

Characterization is initially performed using a set of process parameters to reflect an n-sigma slow and an n-sigma fast delay from the global distribution (typically n = 3). For variation-based timing analysis, the local distributions are also incorporated. The global delay curve in the figure represents the full variation across the manufacturing process. (As an aside, the global curve drawn in the figure is Gaussian. At leading process nodes, the delay distribution is decidedly non-Gaussian; implications of timing variation with non-Gaussian distributions are discussed in Reference 11.10. Also, most characterization flows generate the nominal delay arc tables, using the typical process parameters, at the voltage and temperature associated with the corner.)

Superimposed on the global delay curve are local distributions, in which the n-sigma endpoints of the two curves are aligned. Local parameter distributions would be applicable to within-die circuits, where there would be a degree of process tracking of parameter values in close proximity. The figure illustrates the proposal that a global worst-case (or best-case) delay characterization approach applied to all cells in the timing model would be conservative. A derating of these global delays to represent the probabilistic nature of local delays is appropriate. An analogy for the pessimism in the use of global delay models for path timing for all cells would be to schedule a cross-country driving trip. The conservative calculation of being in “rush hour traffic” through each major city is very unlikely; the more cities on the route, the more unlikely this would be.

To enable SoC designers to compensate for timing pessimism associated with this global and local delay distribution model, the EDA vendor STA tool likely includes a feature to apply a derating multiplier. A derating factor could be applied (selectively) to any of the delays in the timing model:

• All delays

• Cell delays (to all logic cells or by library logic cell name or by logic cell delay arc)

• Interconnect delays

• Specific cell instances (differentiating clock cell derates from logic cell derates)

• Specific interconnect nets

• By levelized position in a timing path

• By relative location to other cells

Derating multipliers less than one (worst case, late mode) applied to logic cells in the timing model would be used to reduce expected pessimism in the global characterization, delay calculation, and propagation algorithms. Conversely, a multiplier greater than one would add conservatism to late mode logic paths. For early mode, a logic data path derating factor greater than one would reduce pessimism for hold time checks (although given the critical nature of satisfying hold time for functional operation, application of derates for a pessimistic hold assumption should be done judiciously).

A timing path example illustrating the use of cell derating factors is shown in Figure 11.18. The logic cells in the timing path would be given derate multipliers to reflect sampling from the local delay distribution. The cells in the clock path maybe given distinct derate values from the logic path. Also, note that levelized cells in the logic timing path would typically be assigned different derates, based on path position. For longer paths, the probabilistic sampling of variations will tend to result in an “average” cell delay closer to the local mean, for the sum of the cell delays in the path. Thus, the derate multiplier for a high-levelization-number cell is selected to provide a local delay for the cell further from the global characterization value to adjust the overall path delay accordingly.

To implement a derating strategy to address pessimism in timing model delay calculation with global and local variation—or, for that matter, to address potential optimism—the SoC methodology team needs to review the statistical characterization approach used by the IP provider. The foundry releases PDK models with statistical distributions based on fabrication testsites. These distributions reflect the overall global device and interconnect parameter data, measured from lot to lot, from wafer to wafer, and across the wafer. Additional distributions represent the local variation data within die, where the σ_local would be a function of the proximity of devices and interconnects on the testsite. The IP provider utilizes these statistical process distributions to establish the derate multipliers to help SoC designers address (late mode) pessimism in the STA flow. The IP provider releases derate tables, which are similar to NLDM tables, as illustrated in Figure 11.19.

In the figure, the input parameters for cell delay derate multipliers are the physical distance spanned by the timing path and the “levelization number” of the cell. For larger dimensions spanned by the path, the “tracking” of local cell delays is reduced; the derate multipliers are closer to 1, which is the global delay value. For higher levelization numbers, the cell derate multiplier results in a delay further from the global n-sigma maximum to better reflect the statistical averaging of multiple local cells in the path.

The potential number of derate tables (and additional characterization effort) is large; recall that NLDM delay and output slew tables are provided for each cell arc across a range of input slews and output loads. Derate table generation for the delay and output slew for each cell would require significant (statistical, Monte Carlo sampling) simulation resources to derive the local distributions. For efficiency, the IP provider is likely to consolidate the derate tables considerably (e.g., one derate table per cell, selected across all arcs, slews, and loads). The path length and location dependency factors in the derate calculation are also determined using Monte Carlo–sampled simulations of representative cells and interconnect layouts, applying the local distributions from the foundry for both device and interconnect variations.

Derate factor tables may also be released by the IP provider for scaling delays with respect to supply voltage and temperature environment settings that differ (slightly) from the PVT characterization corner settings.

A newer proposed variation timing approach uses a different formulation. The cell characterization data would provide an NLDM-like table with σ_local values provided for delay arcs across input slew and output load ranges for each corner. A different statistical-propagation algorithm is now required within the STA tool, as opposed to the conventional max/min arrival time calculation, with scaled delays using derate multipliers. The timing test at the path endpoint also now becomes probabilistic, comparing clock and data distributions to establish a statistical confidence measure.^[11]

It should be highlighted that the static timing methodology to represent increased process variation is still evolving. Timing analysis involves a complex interaction between PDK models, library cell characterization, and cell plus interconnect delay calculation. There are accuracy versus resource trade-offs throughout:

• Circuit and interconnect extraction for various corners

• IP characterization, including the definition of the setup/hold timing tests

• Coupling capacitance modeling (e.g., the k-factors used in interconnect delay calculation)

• C_eff calculation

• Cell delay calculation (nominally measured as the 50 percent-to-50 percent input-to-output waveform crossing delay, with interpolation between the NLDM table entries)

• Cell output waveform definition and interconnect delay calculation

• Interconnect delay/slew calculation at cell fan-out pins

• Local supply/ground (dynamic) voltage drop

• Local temperature differences (on device and interconnect behavior)

With all these variables, the foundry, IP library provider, and EDA tool vendor are striving to define modeling and timing analysis methods that also adequately reflect process variation, without excessive pessimism (or, worse, optimism). The SoC methodology team must assess which variation-aware timing approaches are appropriate for their resource budget and schedule, relative to the design performance targets.

11.4.7 Delay-Based Timing Verification

The application of STA to VLSI methodologies has significantly diminished the use of simulation testcase-based delay testing. The comprehensive nature of STA evaluating all paths in the levelized network graph has effectively covered the need for functional simulation of the cell netlist with instance-specific delays. There are two applications where delay-based simulation may offer additional insights to the SoC design team:

• The members of the test engineering team may wish to simulate specific test patterns to ensure that the chip pin input stimulus time and output pin strobe capture settings relative to the tester clock are valid.

• The functional switching activity with instance-specific delays provides more accurate data on cell-level power dissipation.

Power estimation at the RTL level uses cycle-based simulation event traces on RTL signals and registers to gauge the switching activity. These estimates are extremely useful for relative power optimization decisions prior to physical design. The use of representative simulation testcases with a cell netlist-level model (with only delta delays) offers additional insight. Even if the cell instance delays are zero, more accurate functional switching activity factors are provided compared to the RTL estimates. However, if a delay-based netlist model is used, the results also provide insights into the glitch power due to combinational logic toggles within a cycle, as depicted in Figure 11.20.

zThere are several intricacies to enabling delay-based simulation, for both delay annotation and timing tests. The IP library HDL models need to incorporate the appropriate timing tests at the PVT corner corresponding to the power dissipation calculation. For complex macros and cores from IP providers, the internal event evaluation detail and checking in the functional model is likely to be quite limited. The SoC methodology team needs to review what delay-based model support is available for the IP and whether that meets the simulation testbench requirements. The STA tool needs to export the cell and interconnect delays in a format that can be annotated to the netlist instances. The EDA industry has established a de facto standard for netlist delay annotation; the Standard Delay Format (SDF) defines how timing model data is to be written by the STA tool and the interpretation of this file by an HDL simulator that supports annotation.^[12] This cell delay format includes the capability to define a range of (min, typ, max) transition delay values, assigned to cell pins; the simulations need to select the delay value (or range of values) appropriate for the switching activity of interest.

Transport and Inertial Delay

The SoC methodology team needs to review the HDL simulator settings to be applied when events on the simulator queue are subject to preemption. Specifically, a new event may be associated with inertial or transport signal delay, as illustrated in Figure 11.21.

An inertial delay property implies that a pending signal update on the simulator event queue would be preempted by a subsequent event of different value; the addition of the subsequent assignment to the queue includes removal of the pending event. The “inertial” response time of the signal would preclude the interim transition. A transport delay property is equivalent to a signal with infinite bandwidth; the new signal value assignment is added to the queue after the pending event, and both transitions are evaluated. A transport delay representation offers insight into the glitch switching activity. (There is also the unlikely situation in which a subsequent signal update would occur in time before pending events on the queue; in this case, all future events scheduled for times later than the most recently posted update would be preempted, regardless of the inertial or transport signal property.)

Delay-based simulation for timing verification has effectively been displaced by STA and is focused on specific power and test applications. The adoption of STA modeling based on cell arc and interconnect delays still allows timing model annotation to an HDL-based netlist, using an external delay file format. Delay-based simulation is complicated by the diverse sources of IP models and the focus by IP providers on representing timing tests in the timing model abstract, rather than the functional HDL.

Graph-Based Versus Path-Based Delay Analysis

The discussion in this chapter highlights a conservative methodology for static timing propagation at each cell; specifically, the latest input-to-output arc arrival time and the slowest output signal slew among all arcs are selected for (late mode) propagation. This approach is referred to as “graph-based” STA.

Describe the alternative “path-based” algorithm, with either NLDM or waveform tables.

Describe the runtime versus accuracy trade-offs between graph-based and path-based analysis—specifically, when and where path-based analysis is appropriate.

False Path Verification

Describe a methodology flow for independent verification of STA false path constraints.

STA Results to Be Recorded in the SoC Project Scoreboard

Describe the key information from the STA flow report to record in the SoC project methodology manager. Data to consider include the following:

• Flow input timing constraints, corners, and modes

• Assigned clock arrivals and skews (e.g., from a separate clock simulation flow)

• Derate assumptions used for local n-sigma delay scaling

• TNS and WNS, for both early mode and late mode

• Slack distributions

• Slacks for PI-to-endpoint and endpoint-to-PO paths (for budgeting review; see below)

• Specific from-through-to failing paths (especially paths through hard IP macros, which may necessitate significant physical design updates)

• Paths that have been excised and submitted to circuit simulation

• Waivers (granted after a review of a path-based timing analysis for a from-through-to path or from detailed circuit simulation results)

Block-Level Timing Constraint Budgeting

Delay-Based Functional Simulation (Advanced)

Describe the features of an SDF file used to represent the cell and interconnect delay calculation data of the STA flow (for a specific MCMM setting).

Describe the required features of the HDL model for each library cell to support annotation of the SDF information for delay-based simulation. Illustrate these HDL features using either Verilog or VHDL cell model examples.

Describe how specific timing tests at flip-flops and hard IP macros would be represented in the HDL models in support of delay-based simulation.