References

1394 Trade Association (2004) 1394-based Digital Camera Specification, Vol. Version 1.31, 1394 Trade Association.

Abd Elghany, M.A., Salama, A.E. and Khalil, A.H. (2007) Design and implementation of FPGA-based systolic array for LZ data compression. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Louisiana, USA (27–30 May, 2007), pp. 3691– 3695. doi: 10.1109/ISCAS.2007.378644

Abdou, I.E. and Pratt, W.K. (1979) Quantitative design and evaluation of edge enhancement/thresholding edge detectors. Proceedings of the IEEE, 67 (5), 753–763. doi: 10.1109/PROC.1979.11325

AbuBaker, A., Qahwaji, R., Ipson, S. and Saleh, M. (2007) One scan connected component labeling technique. IEEE International Conference on Signal Processing and Communications (ICSPC 2007), Dubai, United Arab Emirates (24–27 November, 2007), pp. 1283– 1286. doi: 10.1109/ICSPC.2007.4728561

Achronix (2009) Speedster FPGA Family, Vol. DS001 Rev 1.1, Achronix Semiconductor Corporation.

Actel (2008a) IGLOO Low-Power Flash FPGAs, vol. v1.3, Actel Corporation.

Actel (2008b) ProASIC3 Flash Family FPGAs, vol. v1.0, Actel Corporation.

Actel (2009) Axcelerator Family FPGAs, vol. c2.8, Actel Corporation.

Actel (2010) Actel's SmartFusion Intelligent Mixed-Signal FPGAs, Vol. Rev 1, Actel Corporation.

Aeroflex (2008) UT6325 RadTol Eclipse FPGA Data Sheet, Aeroflex Incorporated.

Agostini, L.V., Silva, I.S. and Bampi, S. (2001) Pipelined fast 2D DCT architecture for JPEG image compression. 14th Symposium on Integrated Circuits and Systems Design, Pirenopolis, Brazil (10–15 September, 2001), pp. 226– 231. doi: 10.1109/SBCCI.2001.953032

Agostini, L.V., Porto, R.C., Bampi, S. and Silva, I.S. (2005) A FPGA based design of a multiplierless and fully pipelined JPEG compressor. 8th Euromicro Conference on Digital System Design, Porto, Portugal (30 August–3 September, 2005), pp. 210– 213. doi: 10.1109/DSD.2005.6

Ahmed, H.M. (1982) Signal processing algorithms and architectures. PhD Thesis, Electrical Engineering Department, Stanford University, California, USA.

Ahmed, E. and Rose, J. (2000) The effect of LUT and cluster size on deep-submicron FPGA performance and density. International Symposium on Field Programmable Gate Arrays, Monterey, California, USA (10–11 February, 2000), pp. 3– 12. doi: 10.1145/329166.329171

AIA (2004) Camera Link Specifications, Vol. Version 1.1., Automated Imaging Association.

Aikens, R.S., Agard, D.A. and Sedat, J.W. (1989) Solid-state imagers for microscopy, in Methods in Cell Biology, vol. 29 (eds Y.L. Wang and D.L. Taylor), Academic Press, New York, pp. 291–313.

Akeila, H. and Morris, J. (2008) High resolution stereo in real time, in Robot Vision, Second International Workshop, Auckland, New Zealand (18–20 February, 2008). Lecture Notes in Computer Science, vol. LNCS 4931, Springer, pp. 72–84. doi: 10.1007/978-3-540-78157-8_6

Al-Hasani, F., Bainbridge-Smith, A. and Hayes, M. (2011) A new sub-expression elimination algorithm using zero dominant representations. 6th International Symposium on Electronic Design, Test and Applications, Queenstown, New Zealand (17–19 January, 2011), pp. 45--50. doi: 10.1109/DELTA.2001.18

Alnuweiri, H.M. and Prasanna, V.K. (1992) Parallel architectures and algorithms for image component labeling. IEEE Transactions on Pattern Analysis and Machine Intelligence, 14 (10), 1014–1034. doi: 10.1109/34.159904

Alston, I. and Madahar, B. (2002) From C to netlists: hardware engineering for software engineers? IEE Electronics & Communication Engineering Journal, 14 (4), 165–173. doi: 10.1049/ecej:20020404

Altera (2002) Excalibur Device Overview, vol. DS-EXCARM-2.0, Altera Corporation.

Altera (2006) Stratix Device Handbook, vol. S5V1-3.4, Altera Corporation.

Altera (2007) Stratix II Device Handbook, vol. SII5V1-4.3, Altera Corporation.

Altera (2008a) Arria GX Device Handbook, vol. AGX5V1-1.3, Altera Corporation.

Altera (2008b) Cyclone Device Handbook, vol. C5V1-2.4, Altera Corporation.

Altera (2008c) Cyclone II Device Handbook, vol. CII5V1-3.3, Altera Corporation.

Altera (2008d) Cyclone III Device Handbook, vol. CIII5V1-2.1, Altera Corporation.

Altera (2008e) Quartus II Development Software Handbook, Version 8.1, vol. 3, Altera Corporation.

Altera (2008f) Stratix III Device Handbook, vol. SIII5V1-1.6, Altera Corporation.

Altera (2009a) Generating Functionally Equivalent FPGAs and ASICs with a Single Set of RTL and Synthesis/Timing Constraints, White Paper, Altera Corporation.

Altera (2009b) Timing Closure Methodology for Advanced FPGA Designs, Application note AN-584-1.0., Altera Corporation.

Altera (2010a) Arria II GX Device Handbook, vol. IIAGX5V1-2.0, Altera Corporation.

Altera (2010b) Cyclone IV Device Handbook, vol. CYIV-5V1-1.1, Altera Corporation.

Altera (2010c) DSP Builder Handbook Volume 1: Introduction to DSP Builder, vol. HB_DSPB_INTRO_1.0, Altera Corporation.

Altera (2010d) Stratix IV Device Handbook, vol. SIV5V1-4.0, Altera Corporation.

Altera (2010e) Stratix V Device Handbook, vol. STX5 1.1, Altera Corporation.

Altera (2010f) Video and Image Processing Suite User Guide, vol. UG-VIPSUITE-10.0, Altera Corporation.

Amdahl, G.M. (1967) Validity of the single processor approach to achieving large scale computing capabilities. AFIPS Spring Joint Computer Conference, Atlantic City, New Jersey, USA, vol. 30 (18–20 April, 1967) pp. 483– 485. doi: 10.1145/1465482.1465560

Andraka, R. (1996) Building a high performance bit serial processor in an FPGA. 1996 On-Chip System Design Conference (Design SuperCon), Santa Clara, USA (January, 1996), pp. 5.1– 5.21.

Andraka, R. (1998) A survey of CORDIC algorithms for FPGA based computers. ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, Monterey, California, USA (22–25 February, 1998), pp. 191– 200. doi: 10.1145/275107.275139

Andrews, D., Niehaus, D. and Ashenden, P. (2004) Programming models for hybrid CPU/FPGA chips. IEEE Computer, 37 (1), 118–120. doi: 10.1109/MC.2004.1260732

Angelopoulou, M., Masselos, K., Cheung, P. and Andreopoulos, Y. (2006) A comparison of 2-D discrete wavelet transform computation schedules on FPGAs. International Conference on Field Programmable Technology, Bangkok, Thailand (13–15 December, 2006), pp. 181– 188. doi: 10.1109/FPT.2006.270310

Angelopoulou, M.E., Cheung, P.Y.K., Masselos, K. and Andreopoulos, Y. (2008) Implementation and comparison of the 5/3 lifting 2D discrete wavelet transform computation schedules on FPGAs. Journal of Signal Processing Systems, 51 (1), 3–21. doi: 10.1007/s11265-007-0139-5

Appiah, K. and Hunter, A. (2005) A single-chip FPGA implementation of real-time adaptive background model. IEEE International Conference on Field-Programmable Technology, Singapore (11–14 December, 2005), pp. 95– 102. doi: 10.1109/FPT.2005.1568531

Appiah, K., Hunter, A., Dickenson, P. and Owens, J. (2008) A run-length based connected component algorithm for FPGA implementation. International Conference on Field Programmable Technology, Taipei, Taiwan (7–10 December, 2008), pp. 177– 184. doi: 10.1109/FPT.2008.4762381

Arcelli, C. and Di Baja, G.S. (1985) A width independent fast thinning algorithm. IEEE Transactions on Pattern Analysis and Machine Intelligence, 7 (4), 463–474. doi: 10.1109/TPAMI.1985.4767685

Arias-Estrada, M. and Rodríguez-Palacios, E. (2002) An FPGA co-processor for real-time visual tracking, in International Conference on Field Programmable Logic and Applications, Montpellier, France (2–4 September, 2002), Lecture Notes in Computer Science, vol. LNCS 2438, Springer, pp. 710–719. doi: 10.1007/3-540-46117-5_73

Arno, S. and Wheeler, F.S. (1993) Signed digit representations of minimal Hamming weight. IEEE Transactions on Computers, 42 (8), 1007–1010. doi: 10.1109/12.238495

Arnold, M. and Corporaal, H. (2001) Designing domain-specific processors. Ninth International Symposium on Hardware Software Codesign, Copenhagen, Denmark (25–27 April, 2001), pp. 61– 66. doi: 10.1145/371636.371677

Arribas, P.C. and Maciá, F.M.H. (1999) FPGA implementation of a log-polar algorithm for real time applications. Conference on Design of Circuits and Integrated Systems, Mallorca, Spain (16–19 November, 1999), pp. 63– 68.

Ashenden, P.J. (2008) The Designer's Guide to VHDL, 3rd edn, Morgan Kaufmann Publishers, Burlington, Massachusetts, USA.

Askitis, N. (2009) Fast and compact hash tables for integer keys. Thirty-Second Australasian Computer Science Conference (ACSC 2009), Wellington, New Zealand, vol. CRPIT 91 (January 19–23, 2009), pp. 101– 110.

Astola, J., Haavisto, P., Heinonen, P. and Neuvo, Y. (1988) Median type filters for color signals. IEEE International Symposium on Circuits and Systems, Espoo, Finland, vol. 2 (7–9 June, 1988), pp. 1753– 1756. doi: 10.1109/ISCAS.1988.15274

Astola, J., Haavisto, P. and Neuvo, Y. (1990) Vector median filters. Proceedings of the IEEE, 78 (4), 678–689. doi: 10.1109/5.54807

Ataman, E., Aatre, V.K. and Wong, K.M. (1980) A fast method for real-time median filtering. IEEE Transactions on Acoustics, Speech and Signal Processing, 28 (4), 415–420. doi: 10.1109/TASSP.1980.1163426

Athanas, P.M. and Abbot, A.L. (1995) Real-time image processing on a custom computing platform. IEEE Computer, 28 (2), 16–25. doi: 10.1109/2.347995

Atmel (2006) AT40KAL Series FPGA, vol. 2818F-FPGA-07/06, Atmel Corporation.

Atmel (2008) AT94KAL Series Field Programmable System Level Integrated Circuit, vol. 1138I-FPLI-1/08, Atmel Corporation.

Auer, S. (1982) Imaging by dust rays: a dust ray camera. Optica Acta, 29 (10), 1421–1426. doi: 10.1080/713820766

Avizienis, A. (1961) Signed-digit number representation for fast parallel arithmetic. IRE Transactions on Electronic Computers, EC-10 (3), 389–400. doi: 10.1109/TEC.1961.5219227

Backus, J. (1978) Can programming be liberated from the von Neumann style?: a functional style and its algebra of programs. Communications of the ACM, 21 (8), 613–641. doi: 10.1145/359576.359579

Baer, R.L., Holland, W.D., Holm, J.M. and Vora, P.L. (1999) Comparison of primary and complementary color filters for CCD-based digital photography, in Sensors, Cameras, and Applications for Digital Photography, San Jose, California, USA (January 27–28, 1999), vol. 3650, SPIE, pp. 16–25. doi: 10.1117/12.342859

Bailey, D.G. (1985) Hardware and software developments for applied digital image processing. PhD Thesis, Department of Electrical and Electronic Engineering, University of Canterbury: Christchurch, New Zealand.

Bailey, D.G. (1988) Machine vision: a multi-disciplinary systems engineering problem, in Hybrid Image and Signal Processing, Orlando, Florida, USA (7–8 April, 1988), vol. 939, SPIE, pp. 148–155.

Bailey, D.G. (1990) A rank based edge enhancement filter. 5th New Zealand Image Processing Workshop, Palmerston North, New Zealand (9–10 August, 1990), pp. 42– 47.

Bailey, D.G. (1991) Raster based region growing. 6th New Zealand Image Processing Workshop, Lower Hutt, New Zealand (29–30 August, 1991), pp. 21– 26.

Bailey, D.G. (1992) Segmentation of touching objects. 7th New Zealand Image Processing Workshop, Christchurch, New Zealand (26–28 August, 1992), pp. 195– 200.

Bailey, D.G. (1993) Frequency domain self-filtering for pattern detection. First New Zealand Conference on Image and Vision Computing, Auckland, New Zealand (16–18 August, 1993), pp. 237– 243.

Bailey, D.G. (1995) Pixel calibration techniques. New Zealand Image and Vision Computing '95 Workshop, Lincoln, New Zealand (28–29 August, 1995), pp. 37– 42.

Bailey, D.G. (1997a) Colour plane synchronisation in colour error diffusion. IEEE International Conference on Image Processing, Santa Barbara, California, USA, vol. 1 (26–29 October, 1997) pp. 818– 821. doi: 10.1109/ICIP.1997.648089

Bailey, D.G. (1997b) Detecting regular patterns using frequency domain self-filtering. IEEE International Conference on Image Processing, Santa Barbara, California, USA, vol. 1 (26–29 October, 1997), pp. 440– 443. doi: 10.1109/ICIP.1997.647801

Bailey, D.G. (2002) A new approach to lens distortion correction. Image and Vision Computing New Zealand (IVCNZ'02), Auckland, New Zealand (26–28 November, 2002), pp. 59– 64.

Bailey, D.G. (2003) Sub-pixel estimation of local extrema. Image and Vision Computing New Zealand (IVCNZ'03), Palmerston North, New Zealand (26–28 November, 2003), pp. 414– 419.

Bailey, D.G. (2004) An efficient Euclidean distance transform, in International Workshop on Combinatorial Image Analysis, Auckland, New Zealand (1–3 December, 2004), Lecture Notes in Computer Science, vol. LNCS 3322, Springer, pp. 394–408. doi: 10.1007/b103936

Bailey, D.G. (2006) Space efficient division on FPGAs. Electronics New Zealand Conference (ENZCon'06), Christchurch, New Zealand (13–14 November, 2006), pp. 206– 211.

Bailey, D.G. (2010a) Chain coding streamed images through crack run-length encoding. Image and Vision Computing New Zealand (IVCNZ 2010), Queenstown, New Zealand (8–9 November, 2010), pp. 155--160.

Bailey, D.G. (2010b) Efficient implementation of greyscale morphological filters. International Conference on Field Programmable Technology (FPT 2010), Beijing, China (8–10 December, 2010), pp. 421– 424.

Bailey, D.G. (2011a) Automatic produce grading system, in Machine Vision Handbook (ed. B. Batchelor), Springer. doi: 10.1007/978-1-84996-169-1_29

Bailey, D.G. (2011b) Image border management for FPGA based filters. 6th International Symposium on Electronic Design, Test and Applications, Queenstown, New Zealand (17–19 January, 2011), pp. 144--149. doi: 10.1109/DELTA.2011.34

Bailey, D.G. and Bouganis, C.S. (2008) Reconfigurable foveated active vision system. in International Conference on Sensing Technology, Tainan, Taiwan (30 November–3 December, 2008), pp. 162– 169. doi: 10.1109/ICSENST.2008.4757093

Bailey, D.G. and Bouganis, C.S. (2009a) Implementation of a foveal vision mapping. International Conference on Field Programmable Technology (FPT'09), Sydney, Australia (9–11 December, 2009), pp. 22– 29. doi: 10.1109/FPT.2009.5377646

Bailey, D.G. and Bouganis, C.S. (2009b) Tracking performance of a foveated vision system. International Conference on Autonomous Robots and Agents (ICARA 2009), Wellington, New Zealand (10–12 February, 2009), pp. 414– 419. doi: 10.1109/ICARA.2000.4804029

Bailey, D.G. and Bouganis, C.S. (2009c) Vision sensor with an active digital fovea, in Recent Advances in Sensing Technology, Lecture Notes in Electrical Engineering, vol. LNEE 49 (eds. S.C. Mukhopadhyay, G. Sen Gupta and R.Y.M. Huang), Springer-Verlag, pp. 91–111. doi: 10.1007/978-3-642-00578-7_6

Bailey, D.G. and Gilman, A. (2007) Bias of higher order predictive interpolation for sub-pixel registration. 6th International Conference on Information, Communications and Signal Processing, Singapore (10–13 December, 2007), pp. 1– 5. doi: 10.1109/ICICS.2007.4449703

Bailey, D.G. and Hodgson, R.M. (1985) Range filters: local intensity subrange filters and their properties. Image and Vision Computing, 3 (3), 99–110. doi: 10.1016/0262-8856(85)90058-7

Bailey, D.G. and Hodgson, R.M. (1988) VIPS – a digital image processing algorithm development environment. Image and Vision Computing, 6 (3), 176–184. doi: 10.1016/0262-8856(88)90024-8

Bailey, D.G. and Johnston, C.T. (2007) Single pass connected components analysis. Image and Vision Computing New Zealand (IVCNZ), Hamilton, New Zealand (5–7 December, 2007), pp. 282– 287.

Bailey, D.G. and Johnston, C.T. (2010) Algorithm transformation for FPGA implementation. 5th IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2010), Ho Chi Minh City, Vietnam (13–15 January, 2010), pp. 77– 81. doi: 10.1109/DELTA.2010.17

Bailey, D.G. and Lill, T.H. (1999) Image registration methods for resolution improvement. Image and Vision Computing New Zealand (IVCNZ), Christchurch, New Zealand (30–31 August, 1999) pp. 91– 96.

Bailey, D.G. and Sen Gupta, G. (2010) Automated camera calibration for robot soccer, in Robotic Soccer (ed. V. Papic), In-Tech, Vukovar, Croatia, pp. 311–336.

Bailey, D.G. and Shand, R.D. (1996) Determining large scale sandbar behaviour. IEEE International Conference on Image Processing, Lausanne, Switzerland, vol. 2 (16–19 September, 1996), pp. 637– 640. doi: 10.1109/ICIP.1996.560958

Bailey, D.G., Hodgson, R.M. and McNeill, S.J. (1984) Local filters in digital image processing. National Electronics Conference (NELCON), Christchurch, New Zealand, vol. 21 (22–24 August, 1984), pp. 95– 100.

Bailey, D.G., Mercer, K.A., Plaw, C., Ball, R. and Barraclough, H. (2001) Three dimensional vision for real-time produce grading, in Machine Vision and Three-Dimensional Imaging Systems for Inspection and Metrology II, Boston, Massachusetts, USA, (29–30 October, 2001), vol. 4567, SPIE, pp. 171–178. doi: 10.1117/12.455254

Bailey, D.G., Mercer, K.A., Plaw, C., Ball, R. and Barraclough, H. (2004) High speed weight estimation by image analysis. 2004 New Zealand National Conference on Non Destructive Testing, Palmerston North, New Zealand (27–29 July, 2004), pp. 89– 96.

Bailey, D.G., Seal, J.R. and Sen Gupta, G. (2005) Nonparametric calibration for catadioptric stereo. Image and Vision Computing New Zealand (IVCNZ'05), Dunedin, New Zealand (28–29 November, 2005), pp. 404– 409.

Bailey, D.G., Gribbon, K. and Johnston, C. (2006) GATOS: a windowing operating system for FPGAs. 3rd IEEE International Workshop on Electronic Design, Test, and Applications (DELTA 2006), Kuala Lumpur, Malaysia (17–19 January, 2006), pp. 405– 409. doi: 10.1109/DELTA.2006.51

Bailey, D.G., Johnston, C.T. and Ma, N. (2008) Connected components analysis of streamed images. International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany (8–10 September, 2008), pp. 679– 682. doi: 10.1109/FPL.2008.4630038

Bajard, J.C., Kla, S. and Muller, J.M. (1994) BKM: a new hardware algorithm for complex elementary functions. IEEE Transactions on Computers, 43 (8), 955–963. doi: 10.1109/12.295857

Baker, S. and Matthews, I. (2004) Lucas–Kanade 20 years on: a unifying framework. International Journal of Computer Vision, 56 (3), 221–255. doi: 10.1023/B:VISI.0000011205.11775.fd

Balakrishnan, S. and Eddington, C. (2007) Efficient DSP algorithm development for FPGA and ASIC technologies, White paper. Synopsis Incorporated.

Ballard, D.H. (1981) Generalizing the Hough transform to detect arbitrary shapes. Pattern Recognition, 13 (2), 111–122. doi: 10.1016/0031-3203(81)90009-1

Banerjee, P., Shenoy, N., Choudhary, A., Hauck, S., Bachmann, C., Haldar, M., Joisha, P., Jones, A., Kanhare, A., Nayak, A., Periyacheri, S., Walkden, M. and Zaretsky, D. (2000) A MATLAB compiler for distributed, heterogeneous, reconfigurable computing systems. 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, California, USA (17–19 April, 2000) pp. 39– 48. doi: 10.1109/FPGA.2000.903391

Banerjee, P., Bagchi, D., Haldar, M., Nayak, A., Kim, V. and Uribe, R. (2003) Automatic conversion of floating point MATLAB programs into fixed point FPGA based hardware design. 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), Napa, California, USA (9–11 April, 2003), pp. 263– 264. doi: 10.1109/FPGA.2003.1227262

Barnett, V. (1976) Ordering of multivariate data. Journal of the Royal Statistical Society Series A - Statistics in Society, 139 (3), 318–355. doi: 10.2307/2344839

Barni, M. (1997) A fast algorithm for 1-norm vector median filtering. IEEE Transactions on Image Processing, 6 (10), 1452–1455. doi: 10.1109/83.624972

Barni, M., Buti, F., Bartolini, F. and Cappellini, V. (2000) A quasi-Euclidean norm to speed up vector median filtering. IEEE Transactions on Image Processing, 9 (10), 1704–1709. doi: 10.1109/83.869182

Batchelor, B.G. (1979) Streak and spot detection in digital pictures. Electronics Letters, 15 (12), 352–353. doi: 10.1049/el:19790250

Batchelor, B.G. (1994) HyperCard lighting advisor. in Machine Vision Applications, Architectures, and Systems Integration III, Boston, Massachusetts, USA (31 October–2 November, 1994), vol. 2347, SPIE, pp. 180–188. doi: 10.1117/12.188730

Batchelor, B.G. and Whelan, P.F. (1994) Machine vision systems: proverbs, principles, prejudices and priorities, in Machine Vision Applications, Architectures and Systems Integration III, Boston, Massachusetts, USA (31 October–2 November, 1994), vol. 2347, SPIE, pp. 374–383. doi: 10.1117/12.188748

Batcher, K.E. (1980) Design of a massively parallel processor. IEEE Transactions on Computers, C-29 (9), 836–849. doi: 10.1109/TC.1980.1675684

Bayer, B.E. (1976) Color imaging array, United States of America patent 3971065.

Bednar, J.B. and Watt, T.L. (1984) Alpha trimmed means and their relationship to median filters. IEEE Transactions on Acoustics, Speech and Signal Processing, 32 (1), 145–153. doi: 10.1109/TASSP.1984.1164279

Beis, J.S. and Lowe, D.G. (1997) Shape indexing using approximate nearest-neighbour search in high-dimensional spaces. IEEE Computer Society Conference on Computer Vision and Pattern Recognition, San Juan, Puerto Rico (17–19 June, 1997), pp. 1000– 1006. doi: 10.1109/CVPR.1997.609451

Bellas, N., Chai, S.M., Dwyer, M. and Linzmeier, D. (2009) Real-time fisheye lens distortion correction using automatically generated streaming accelerators. 17th IEEE Symposium on Field Programmable Custom Computing Machines (FCCM), Napa, California, USA (5–7 April, 2009), pp. 149– 156. doi: 10.1109/FCCM.2009.16

Bellows, P. and Hutchings, B. (1998) JHDL-an HDL for reconfigurable systems. IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, California, USA (15–17 April, 1998), pp. 175– 184. doi: 10.1109/FPGA.1998.707895

Bellows, P. and Hutchings, B. (2001) Designing run-time reconfigurable systems with JHDL. Journal of VLSI Signal Processing, 28 (1), 29–45. doi: 10.1023/A:1008107104782

Benitez, D. (2002) Performance of remote FPGA-based coprocessors for image-processing applications. Euromicro Symposium on Digital System Design, Dortmund, Germany (4–6 September, 2002) pp. 268– 275. doi: 10.1109/DSD.2002.1115378

Benkrid, K. (2000) Design and implementation of a high level FPGA based coprocessor for image and video processing. PhD Thesis, Department of Computer Science, Queen's University of Belfast: Belfast.

Benkrid, A. and Benkrid, K. (2008) HIDE++: a logic based hardware development environment. Engineering Letters, 16 (3), 460–468.

Benkrid, K. and Crookes, D. (2003) New bit-level algorithm for general purpose median filtering. Journal of Electronic Imaging, 12 (2), 263–269. doi: 10.1117/1.1557153

Benkrid, K., Crookes, D., Smith, J. and Benkrid, A. (2000) High level programming for real time FPGA based video processing. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '00), Istanbul, Turkey, vol. 6 (5–9 June, 2000), pp. 3227– 3230. doi: 10.1109/ICASSP.2000.860087

Benkrid, K., Crookes, D. and Benkrid, A. (2002a) Design and implementation of a novel algorithm for general purpose median filtering on FPGAs. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix, Arizona, vol. 4 (26–29 May, 2002), pp. 425– 428. doi: 10.1109/ISCAS.2002.1010482

Benkrid, K., Crookes, D., Benkrid, A. and Belkacemi, S. (2002b) A Prolog-based hardware development environment, in International Conference on Field Programmable Logic and Applications, Montpellier, France (2–4 September, 2002), Lecture Notes in Computer Science, vol. LNCS 2438, Springer, pp. 370–380. doi: 10.1007/3-540-46117-5_39

Benkrid, A., Benkrid, K. and Crookes, D. (2003a) A novel FIR filter architecture for efficient signal boundary handling on Xilinx VIRTEX FPGAs. 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), Napa, California, USA (9--11 April, 2003), pp. 273– 275. doi: 10.1109/FPGA.2003.1227267

Benkrid, K., Sukhsawas, S., Crookes, D. and Benkrid, A. (2003b) An FPGA-based image connected component labeller, in International Conference on Field Programmable Logic and Applications (FPL 2003), Lisbon, Portugal (1–3 September, 2003), Lecture Notes in Computer Science, vol. LNCS 2778, Springer, pp. 1012–1015. doi: 10.1007/b12007

Benkrid, K., Belkacemi, S. and Benkrid, A. (2006) HIDE: a hardware intelligent description environment. Microprocessors and Microsystems, 6 (30), 283–300. doi: 10.1016/j.micpro.2006.02.005

Bergland, G.D. (1969) A guided tour of the fast Fourier transform. IEEE Spectrum, 6 (7), 41–52. doi: 10.1109/MSPEC.1969.5213896

Bhasker, J. (1999) A VHDL primer, 3rd edn, Prentice-Hall, New Jersey.

Bhasker, J. (2005) A Verilog HDL Primer, 3rd edn, Star Galaxy Publishing.

Blodget, B., McMillan, S. and Lysaght, P. (2003) A lightweight approach for embedded reconfiguration of FPGAs. Design, Automation and Test in Europe Conference and Exhibition (DATE'03), Munich, Germany (3–7 March, 2003), pp. 399– 400. doi: 10.1109/DATE.2003.10160

Body, N.B. and Bailey, D.G. (1998) Efficient representation and decoding of static Huffman code tables in a very low bit rate environment. IEEE International Conference on Image Processing, Chicago, Illinois, USA, vol. 3 (4–7 October, 1998), pp. 90– 94. doi: 10.1109/ICIP.1998.727139

Bohm, A.P.W., Draper, B., Najjar, W., Hammes, J., Rinker, R., Chawathe, M. and Ross, C. (2001) One-step compilation of image processing applications to FPGAs. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01), Rohnert Park, California, USA (30 April–2 May, 2001), pp. 209– 218. doi: 10.1109/FCCM.2001.32

Bohm, W., Hammes, J., Draper, B., Chawathe, M., Ross, C., Rinker, R. and Najjar, W. (2002) Mapping a single assignment programming language to reconfigurable systems. Journal of Supercomputing, 21 (2), 117–130. doi: 10.1023/A:1013623303037

Bollaert, T. (2008) Catapult synthesis: a practical introduction to interactive C synthesis, in High-Level Synthesis (eds P. Coussy and A. Morawiec), Springer, The Netherlands, pp. 29–52. doi: 10.1007/978-1-4020-8588-8_3

Booth, A.D. (1951) A signed binary multiplication technique. Quarterly Journal of Mechanics and Applied Mathematics, 4 (2), 236–240. doi: 10.1093/qjmam/4.2.236

Borgefors, G. (1986) Distance transformations in digital images. Computer Vision, Graphics, and Image Processing, 34 (3), 344–371. doi: 10.1016/S0734-189X(86)80047-0

Bouganis, C.S., Constantinides, G.A. and Cheung, P.Y.K. (2005) A novel 2D filter design methodology for heterogeneous devices. 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), Napa, California, USA (18--20 April, 2005), pp. 13– 22. doi: 10.1109/FCCM.2005.10

Boullis, N., Mencer, O., Luk, W. and Styles, H. (2001) Pipelined function evaluation on FPGAs. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01), Rohnert Park, California, USA (30 April–2 May, 2001), pp. 304– 306. doi: 10.1109/FCCM.2001.37

Bovik, A.C., Huang, T.S. and Munson, D.C. (1983) A generalisation of median filtering using linear combinations of order statistics. IEEE Transactions on Acoustics, Speech and Signal Processing, 31 (6), 1342–1349. doi: 10.1109/TASSP.1983.1164247

Bowen, O. and Bouganis, C.S. (2008) Real-time image super resolution using an FPGA. International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany (8–10 September, 2008), pp. 89– 94. doi: 10.1109/FPL.2008.4629913

Bracewell, R.N. (2000) The Fourier Transform and its Applications, 3 edn, McGraw Hill, New York.

Braun, G.J. and Fairchild, M.D. (1999) Image lightness rescaling using sigmoidal contrast enhancement functions. Journal of Electronic Imaging, 8 (4), 380–393. doi: 10.1117/1.482706

Brisebarre, N., Muller, J.M. and Tisserand, A. (2006) Computing machine-efficient polynomial approximations. ACM Transactions on Mathematical Software, 32 (2), 236–256. doi: 10.1145/1141885.1141890

Brown, D.C. (1971) Close range camera calibration. Photogrammetric Engineering, 37 (8), 855–866.

Brown, S.R. (1987) A note on the description of surface roughness using fractal dimension. Geophysical Research Letters, 14 (11), 1095–1098.

Brown, L.G. (1992) A survey of image registration techniques. ACM Computing Surveys, 24 (4), 325–376. doi: 10.1145/146370.146374

Brown, C.W. and Shepherd, B.J. (1995) Graphics File Formats: Reference and Guide, Manning, Greenwich, Connecticut, USA.

Brumfitt, P.J. (1984) Environments for image processing algorithm development. Image and Vision Computing, 2 (4), 198–203. doi: 10.1016/0262-8856(84)90023-4

Buck, J.T. and Lee, E.A. (1993) Scheduling dynamic dataflow graphs with bounded memory using the token flow model. IEEE International Conference on Acoustics, Speech and Signal Processing, Minneapolis, Minnesota, USA, vol. 1 (27–30 April, 1993), pp. 429– 432. doi: 10.1109/ICASSP.1993.319147

Buhler, A. (2007) GateOS: a minimalist windowing environment and operating system for FPGAs. Master of Engineering Thesis, Institute of Information Sciences and Technology, Massey University, Palmerston North, New Zealand. hdl: 10179/667

Bunnik, H.M.W., Bailey, D.G. and Mawson, A.J. (2006) Objective colour measurement of tomatoes and limes. Image and Vision Computing New Zealand (IVCNZ'06), Great Barrier Island, New Zealand (27–29 November, 2006), pp. 263– 268.

Burdeniuk, A., To, K.N., Lim, C.C. and Liebelt, M.J. (2010) An event-assisted sequencer to accelerate matrix algorithms. 5th IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2010), Ho Chi Minh City, Vietnam (13–15 January, 2010), pp. 158– 163. doi: 10.1109/DELTA.2010.12

Butt, M.A. and Maragos, P. (1998) Optimal design of chamfer distance transforms. IEEE Transactions on Image Processing, 7 (10), 1477–1484. doi: 10.1109/83.718487

Buyukkurt, B., Guo, Z. and Najjar, W.A. (2006) Impact of loop unrolling on area, throughput and clock frequency in ROCCC: C to VHDL compiler for FPGAs, in Second International Workshop on Reconfigurable Computing (ARC 2006), Delft, The Netherlands, (1–3 March, 2006), Lecture Notes in Computer Science, vol. LNCS 3985, Springer, pp. 401–412. doi: 10.1007/11802839_48

Cady, F.M., Hodgson, R.M., Pairman, D., Rodgers, M.A. and Atkinson, G.J. (1981) Interactive image processing software for a microcomputer. IEE Proceedings E: Computers and Digital Techniques, 128 (4), 165–171. doi: 10.1049/ip-e:19810030

Camacho, P., Arrebola, F. and Sadoval, F. (1998) Multiresolution sensors with adaptive structure. 24th Annual Conference of the IEEE Industrial Electronics Society (IECON '98), Aachen, Germany, vol. 2 (31 August–4 September, 1998), pp. 1230– 1235. doi: 10.1109/IECON.1998.724279

Canny, J. (1986) A computational approach to edge detection. IEEE Transactions on Pattern Analysis and Machine Intelligence, 8 (6), 679–698. doi: 10.1109/TPAMI.1986.4767851

Carlotto, M.J. (1987) Histogram analysis using a scale-space approach. IEEE Transactions on Pattern Analysis and Machine Intelligence, 9 (1), 121–129. doi: 10.1109/TPAMI.1987.4767877

Castleman, K.R. (1979) Digital Image Processing, Prentice Hall, Englewood Cliffs, NJ.

Castleman, K.R. (1996) Digital Image Processing, 1st edn, Prentice-Hall, New Jersey.

Catmull, E. and Smith, A.R. (1980) 3-D transformations of images in scanline order. ACM SIGGRAPH Computer Graphics, 14 (3), 279–285. doi: 10.1145/965105.807505

Catsoulis, J. (2005) Designing Embedded Hardware, 2nd edn, O'Reilly.

Cederberg, R.T.L. (1979) Chain link coding and segmentation for raster scan devices. Computer Graphics and Image Processing, 10 (3), 224–234. doi: 10.1016/0146-664X(79)90002-9

Celebi, M.E. and Aslandogan, Y.A. (2008) Robust switching vector median filter for impulsive noise removal. Journal of Electronic Imaging, 17 (4), 043006-1-9. doi: 10.1117/1.2991415

Chai, D. and Bouzerdoum, A. (2000) A Bayesian approach to skin color classification in YCbCr color space. IEEE Region 10 Conference (TENCON 2000), Kuala Lumpur, Malaysia, vol. 2 (24–27 September, 2000), pp. 421– 424. doi: 10.1109/TENCON.2000.888774

Chakrabarti, C. and Wang, L.Y. (1994) Novel sorting network-based architectures for rank order filters. IEEE Transactions on VLSI Systems, 2 (4), 502–507. doi: 10.1109/92.335027

Chakravarty, I. (1981) A single-pass, chain generating algorithm for region boundaries. Computer Graphics and Image Processing, 15 (2), 182–193. doi: 10.1016/0146-664X(81)90078-2

Chan, F.H.Y., Lam, F.K., Li, H.F. and Liu, J.G. (1996) An all adder systolic structure for fast computation of moments. Journal of VLSI Signal Processing, 12 (2), 159–175. doi: 10.1007/BF00924524

Chandrasekaran, R. and Tamir, A. (1989) Open questions concerning Weiszfeld's algorithm for the Fermat–Weber location problem. Mathematical Programming, 44 (1–3), 293–295. doi: 10.1007/BF01587094

Chang, L. and Hernández-Palancar, J. (2009) A hardware architecture for SIFT candidate keypoints detection, in 14th Iberoamerican Conference on Pattern Recognition, Guadalajara, Mexico, Lecture Notes in Computer Science, vol. LNCS 5856, Springer, pp. 95–102. doi: 10.1007/978-3-642-10268-4_11

Chang, S.K., Barnett, M.M., Levialdi, S., Marriott, K., Pfeiffer, J.J. and Tanimoto, S.L. (1999) The future of visual languages. IEEE Symposium on Visual Languages, Tokyo, Japan (13–16 September, 1999), pp. 58– 61. doi: 10.1109/VL.1999.795875

Chang, F., Chen, C.J. and Lu, C.J. (2004) A linear-time component-labeling algorithm using contour tracing technique. Computer Vision and Image Understanding, 93 (2), 206–220. doi: 10.1016/j.cviu.2003.09.002

Chanussot, J., Paindavoine, M. and Lambert, P. (1999) Real time vector median like filter: FPGA design and application to color image filtering. IEEE International Conference on Image Processing (ICIP'99), Kobe, Japan, vol. 2 (24–28 October, 1999), pp. 414– 418. doi: 10.1109/ICIP.1999.822929

Chapweske, A. (2003) The PS/2 Mouse/Keyboard Protocol. Available from http://www.computer-engineering.org [cited 20 July, 2006].

Choo, C. and Verma, P. (2008) A real-time bit-serial rank filter implementation using Xilinx FPGA, in Real-Time Image Processing 2008, San Jose, California, USA (28–29 January, 2008) vol. 6811, SPIE, pp. 68110F-1-8. doi: 10.1117/12.765789

Chrysafis, C. and Ortega, A. (2000) Line-based, reduced memory, wavelet image compression. IEEE Transactions on Image Processing, 9 (3), 378–389. doi: 10.1109/83.826776

Claus, C., Huitl, R., Rausch, J. and Stechele, W. (2009) Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic (31 August–2 September, 2009), pp. 138– 145. doi: 10.1109/FPL.2009.5272492

Clist, R.S. and Valkenburg, R.J. (1994) Close coupling of a multiple-instruction-multiple-data (MIMD) system to a MAXbus pipeline: the Kiwivision MTM multitransputer architecture, in Machine Vision Applications, Architectures and Systems Integration III, Boston, Massachusetts, USA (31 October–2 November, 1994), vol. 2347, SPIE, pp. 106–114. doi: 10.1117/12.188723

Coffman, E.G., Elphick, M. and Shoshani, A. (1971) System deadlocks. ACM Computing Surveys, 3 (2), 67–78. doi: 10.1145/356586.356588

Comer, M. and Delp, E. (1999) Morphological operations for color image processing. Journal of Electronic Imaging, 8 (3), 279–289. doi: 10.1117/1.482677

Compton, K. and Hauck, S. (2002) Reconfigurable computing: a survey of systems and software. ACM Computing Surveys, 34 (2), 171–210. doi: 10.1145/508352.508353

Conners, R.W. and Harlow, C.A. (1980) A theoretical comparison of texture algorithms. IEEE Transactions on Pattern Analysis and Machine Intelligence, 2 (3), 204–223. doi: 10.1109/TPAMI.1980.4767008

Constantinides, G.A., Cheung, P.Y.K. and Luk, W. (2001) The multiple wordlength paradigm. IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'01), Rohnert Park, California, USA (30 April–2 May, 2001), pp. 51– 60. doi: 10.1109/FCCM.2001.46

Cope, B., Cheung, P.Y.K., Luk, W. and Witt, S. (2005) Have GPUs made FPGAs redundant in the field of video processing? IEEE International Conference on Field-Programmable Technology, Singapore (11–14 December, 2005), pp. 111– 118. doi: 10.1109/FPT.2005.1568533

Coutinho, J.G.F. and Luk, W. (2003) Source-directed transformations for hardware compilation. IEEE International Conference on Field-Programmable Technology (FPT), Tokyo, Japan (15–17 December, 2003), pp. 278– 285. doi: 10.1109/FPT.2003.1275758

Crookes, D. and Benkrid, K. (1999) An FPGA implementation of image component labelling, in Reconfigurable Technology: FPGAs for Computing and Applications, Boston, Massachusetts, USA (20–21 September, 1999), vol. 3844, SPIE, pp. 17–23. doi: 10.1117/12.359538

Crookes, D., Morrow, P.J. and McParland, P.J. (1989) An algebra-based language for image processing on transputers. Third International Conference on Image Processing and its Applications, Warwick, UK (18–20 July, 1989), pp. 457– 461.

Crookes, D., Alotaibi, K., Bouridane, A., Donachy, P. and Benkrid, A. (1998) An environment for generating FPGA architectures for image algebra-based algorithms. 1998 International Conference on Image Processing (ICIP 98), Chicago, Illinois, USA, vol. 3 (4–7 October, 1998), pp. 990– 994. doi: 10.1109/ICIP.1998.999082

Crookes, D., Benkrid, K., Bouridane, A., Alotaibi, K. and Benkrid, A. (2000) Design and implementation of a high level programming environment for FPGA-based image processing. IEE Proceedings Vision, Image and Signal Processing, 147 (4), 377–384. doi: 10.1049/ip-vis:20000579

Crow, F.C. (1984) Summed-area tables for texture mapping. SIGGRAPH'84 International Conference on Computer Graphics and Interactive Techniques, Minneapolis, Minnesota, USA (23–27 July, 1984), pp. 207– 212. doi: 10.1145/800031.808600

Cucchiara, R., Neri, G. and Piccardi, M. (1998) A real-time hardware implementation of the Hough transform. Journal of Systems Architecture, 45 (1), 31–45. doi: 10.1016/S1383-7621(97)00071-4

Cucchiara, R., Onfiani, P., Prati, A. and Scarabottolo, N. (1999) Segmentation of moving objects at frame rate: a dedicated hardware solution. Seventh International Conference on Image Processing and its Applications, Manchester, UK, vol. Conf Publ 465 (13–15 July, 1999), pp. 138– 142. doi: 10.1049/cp:19990297

Cuisenaire, O. and Macq, B. (1999) Fast Euclidean distance transformation by propagation using multiple neighbourhoods. Computer Vision and Image Understanding, 76 (2), 163–172. doi: 10.1006/cviu.1999.0783

Currie, A.J. (1995). Differentiating apple sports by pollen ultrastructure. Master of Horticultrual Science Thesis, Massey University, Palmerston North, New Zealand.

Cutler, R. and Davis, L. (1998) View-based detection and analysis of periodic motion. Fourteenth International Conference on Pattern Recognition, Brisbane, Australia, vol. 1 (16–20 August, 1998), pp. 495– 500. doi: 10.1109/ICPR.1998.711189

Dadda, L. (1965) Some schemes for parallel multipliers. Alta Frequenza, 34 (5), 349–356.

Danger, J.L., Guilley, S. and Hoogvorst, P. (2007) Fast true random generator in FPGAs. IEEE Northeast Workshop on Circuits and Systems, Montreal, Canada (5–8 August, 2007), pp. 506– 509. doi: 10.1109/NEWCAS.2007.4487970

Danielsson, P.E. (1980) Euclidean distance mapping. Computer Graphics and Image Processing, 14 (3), 227–248. doi: 10.1016/0146-664X(80)90054-4

Danielsson, P.E. (1981) Getting the median faster. Computer Graphics and Image Processing, 17 (1), 71–78. doi: 10.1016/S0146-664X(81)80010-X

Das Sarma, D. and Matula, D.W. (1995) Faithful bipartite ROM reciprocal tables. 12th Symposium on Computer Arithmetic, Bath, UK (19–21 July, 1995), pp. 17– 28. doi: 10.1109/ARITH.1995.465381

DAU (2001) Systems Engineering Fundamentals, Defense Acquisition University Press, Fort Belvoir, Virginia, USA.

Daubechies, I. and Sweldens, W. (1998) Factoring wavelet transforms into lifting steps. Journal of Fourier Analysis and Applications, 4 (3), 247–269. doi: 10.1007/BF02476026

Davies, E.R. (1988) A modified Hough scheme for general circle location. Pattern Recognition Letters, 7 (1), 37–43. doi: 10.1016/0167-8655(88)90042-6

Davies, E.R. (1999) High precision discrete model of median shifts. Seventh International Conference on Image Processing and its Applications, Manchester, UK, vol. 1 (13–15 July, 1999), pp. 197– 201.

Davies, E.R. (2000) Accuracy of multichannel median filter. Electronics Letters, 36 (25), 2068–2069. doi: 10.1049/el:20001465

Davies, E.R. (2008) Stable bi-level and multi-level thresholding of images using a new global transformation. IET Computer Vision, 2 (2), 60–74. doi: 10.1049/iet-cvi:20070071

Dawid, H. and Meyr, H. (1992) VLSI implementation of the CORDIC algorithm using redundant arithmetic. IEEE International Symposium on Circuits and Systems (ISCAS '92), San Diego, California, USA, vol. 3 (10–13 May, 1992), pp. 1089– 1092. doi: 10.1109/ISCAS.1992.230290

DDWG (1999) Digital Visual Interface (DVI), Revision 1.0., Digital Display Working Group.

de Dinechin, F. and Tisserand, A. (2001) Some improvements on multipartite table methods. IEEE Symposium on Computer Arithmetic, Vail, Colorado, USA (11–13 June, 2001), pp. 128– 135. doi: 10.1109/ARITH.2001.930112

de Haan, G. and Bellers, E.B. (1998) Deinterlacing – an overview. Proceedings of the IEEE, 86 (9), 1839–1857. doi: 10.1109/5.705528

De Smet, P. (2010) Optimized high speed pixel sorting and its application in watershed based image segmentation. Pattern Recognition, 43 (7), 2359–2366. doi: 10.1016/j.patcog.2010.01.014

DeHon, A., Adams, J., DeLorimier, M., Kapre, N., Matsuda, Y., Naeimi, H., Vanier, M., and Wrighton, M. (2004) Design patterns for reconfigurable computing. 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), Napa Valley, California, USA (20–23 April, 2004), pp. 13– 23. doi: 10.1109/FCCM.2004.29

Dempster, A.G. and Macleod, M.D. (1994) Constant integer multiplication using minimum adders. IEE Proceedings – Circuits, Devices and Systems, 141 (5), 407–413. doi: 10.1049/ip-cds:19941191

Denyer, P.B. and Renshaw, D. (1985) VLSI Signal Processing; a Bit-Serial Approach, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA.

Despain, A.M. (1974) Fourier transform computers using CORDIC iterations. IEEE Transactions on Computers, C-23 (10), 993–1001. doi: 10.1109/T-C.1974.223800

Detrey, J. and de Dinechin, F. (2004) Second order function approximation using a single multiplication on FPGAs, in 14th International Conference on Field Programmable Logic and Application, Antwerp, Belgium (29 August–1 September, 2004), Lecture Notes in Computer Science, vol. LNCS 3203, Springer, pp. 221–230. doi: 10.1007/b99787

Deutsch, P. (1996) DEFLATE Compressed Data Format Specification Version 1.3, Aladdin Enterprises.

Devernay, F. and Faugeras, O. (2001) Straight lines have to be straight. Machine Vision and Applications, 13, 14–24. doi: 10.1007/PL00013269

Diamantaras, K.I. and Kung, S.Y. (1997) A linear systolic array for real-time morphological image processing. Journal of VLSI Signal Processing, 17 (1), 43–55. doi: 10.1023/A:1007996916499

Diaz, J., Ros, E., Mota, S., Carrillo, R. and Agis, R. (2004) Real time optical flow processing system, in 14th International Conference on Field Programmable Logic and Application, Antwerp, Belgium (29 August–1 September, 2004), Lecture Notes in Computer Science, vol. LNCS 3203, Springer, pp. 617–626. doi: 10.1007/b99787

Dijkstra, E.W. (1959) A note on two problems in connexion with graphs. Numerische Mathematik, 1 (1), 269–271. doi: 10.1007/BF01386390

Dike, C. and Burton, E. (1999) Miller and noise effects in a synchronizing flip-flop. IEEE Journal of Solid-State Circuits, 34 (6), 849–855. doi: 10.1109/4.766819

Dollas, A., Ermis, I., Koidis, I., Zisis, I. and Kachris, C. (2005) An open TCP/IP core for reconfigurable logic. 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), Napa, California, USA (18–20 April, 2005), pp. 297– 298. doi: 10.1109/FCCM.2005.20

Donoho, D.L. (1995) De-noising by soft-thresholding. IEEE Transactions on Information Theory, 41 (3), 613–627. doi: 10.1109/18.382009

Donoho, D.L. and Johnstone, I.M. (1994) Threshold selection for wavelet shrinkage of noisy data. 16th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Baltimore, Maryland, USA, vol. 1 (3–6 November, 1994), pp. A24– A25. doi: 10.1109/IEMBS.1994.412133

Dougherty, E.R. and Laplante, P.A. (1985) Introduction to Real Time Imaging, The International Society for Optical Engineering, Washington.

Downton, A. and Crookes, D. (1998) Parallel architectures for image processing. IEE Electronics & Communication Engineering Journal, 10 (3), 139–151. doi: 10.1049/ecej:19980307

Doyle, W. (1962) Operations useful for similarity invariant pattern recognition. Journal of the Association for Computing Machinery, 9 (2), 259–267. doi: 10.1145/321119.321123

Draper, B., Najjar, W., Bohm, W., Hammes, J., Rinker, B., Ross, C., Chawathe, M. and Bins, J. (2000) Compiling and optimizing image processing algorithms for FPGAs. Fifth IEEE International Workshop on Computer Architectures for Machine Perception, Padova, Italy (11–13 September, 2000), pp. 222– 231. doi: 10.1109/CAMP.2000.875981

Draper, B.A., Bohm, A.P.W., Hammes, J., Najjar, W.A., Beveridge, J.R., Ross, C., Chawathe, M., Desai, M. and Bins, J. (2001) Compiling SA-C programs to FPGAs: performance results, in Second International Workshop on Computer Vision Systems, Vancouver, Canada (7–8 July, 2001), Lecture Notes in Computer Science, vol. LNCS 2095, Springer, pp. 220–235. doi: 10.1007/3-540-48222-9_15

Draper, B.A., Beveridge, J.R., Bohm, A.P.W., Ross, C. and Chawathe, M. (2002) Implementing image applications on FPGAs. 16th International Conference on Pattern Recognition, Quebec, Canada, vol. 3 (11–15 August, 2002), pp. 265– 268. doi: 10.1109/ICPR.2002.1047845

Draper, B.A., Beveridge, J.R., Bohm, A.P.W., Ross, C. and Chawathe, M. (2003) Accelerated image processing on FPGAs. IEEE Transactions on Image Processing, 12 (12), 1543–1551. doi: 10.1109/TIP.2003.819226

Dubois, J., Mattavelli, M., Pierrefeu, L. and Miteran, J. (2005) Configurable motion-estimation hardware accelerator module for the MPEG-4 reference hardware description platform. IEEE International Conference on Image Processing (ICIP 2005), Genoa, Italy, vol. 3 (11–14 September, 2005), pp. 1040– 1043. doi: 10.1109/ICIP.2005.1530573

Duda, K. (2010) Accurate, guaranteed stable, sliding discrete Fourier transform. IEEE Signal Processing Magazine, 27 (10), 124–127. doi: 10.1109/MSP.2010.938088

Duda, R.O. and Hart, P.E. (1972) Use of the Hough transformation to detect lines and curves in pictures. Communications of the ACM, 15 (1), 11–15. doi: 10.1145/361237.361242

Duff, M.J.B. (2000) Thirty years of parallel image processing, in Vector and Parallel Processing (VECPAR 2000), Porto, Portugal (21–23 June, 2000), Lecture Notes in Computer Science, vol. LNCS 1981, Springer, pp. 419–438. doi: 10.1007/3-540-44942-6_35

Duff, M.J.B., Watson, D.M., Fountain, T.J. and Shaw, G.K. (1973) A cellular logic array for image processing. Pattern Recognition, 5 (3), 229–240. doi: 10.1016/0031-3203(73)90045-9

Dumitriu, V., Marcantonio, D. and Kirischian, L. (2009) Run-time component relocation in partially-reconfigurable FPGAs. International Conference on Computational Science and Engineering (CSE'09), Vancouver, Canada, vol. 2 (29–31 August, 2009), pp. 909– 914. doi: 10.1109/CSE.2009.493

Duncan, D.B. and Leeson, G. (1999) Cost effective real-time multi-spectral digital video imaging, in Sensors, Cameras, and Systems for Scientific/Industrial Applications, San Jose, California, USA (25–26 January, 1999), vol. 3649, SPIE, pp. 100–108. doi: 10.1117/12.347065

Eadie, D., Shevlin, F.O. and Nisbet, A. (2002) Correction of geometric image distortion using FPGAs, in Opto-Ireland 2002: Optical Metrology, Imaging, and Machine Vision, Galway, Ireland (5–6 September, 2002), vol. 4877, SPIE, pp. 28–37. doi: 10.1117/12.463765

Economakos, G., Oikonomakos, P., Panagopoulos, I., Poulakis, I. and Papakonstantinou, G. (2001) Behavioral synthesis with SystemC. Design, Automation and Test in Europe, Conference and Exhibition, Munich, Germany (13–16 March, 2001), pp. 21– 25. doi: 10.1109/DATE.2001.914995

Edwards, S.A. (2005) The challenges of hardware synthesis from C-like languages. Design, Automation and Test in Europe, Munich, Germany, vol. 1 (7–11 March, 2005), pp. 66– 67. doi: 10.1109/DATE.2005.307

Edwards, S.A. (2006) The challenges of synthesizing hardware from C-Like languages. IEEE Design & Test of Computers, 23 (5), 375–383. doi: 10.1109/MDT.2006.134

Ehlers, M. (1991) Multisensor image fusion techniques in remote sensing. ISPRS Journal of Photogrammetry and Remote Sensing, 46 (1), 19–30. doi: 10.1016/0924-2716(91)90003-E

Elzinga, S., Lin, J. and Singhal, V. (2000) Design tips for HDL implementation of arithmetic functions, Application note XAPP215 (v1.0). Xilinx Inc.

EMVA (2009) GenICam Standard, Vol. 2.0., European Machine Vision Association.

Eschbach, R. and Knox, K.T. (1991) Error-diffusion algorithm with edge enhancement. Journal of the Optical Society of America A, 8 (12), 1844–1850. doi: 10.1364/JOSAA.8.001844

Evemy, J.D., Allerton, D.J. and Zaluska, E.J. (1990) Stream processing architecture for real-time implementation of perspective spatial transformations. IEE Proceedings I: Communications, Speech and Vision, 137 (3), 123–128.

Ewe, C.T., Cheung, P.Y.K. and Constantinides, G.A. (2004) Dual fixed-point: an efficient alternative to floating-point computation, in 14th International Conference on Field Programmable Logic and Applications, Antwerp, Belgium (29 August–1 September, 2004), Lecture Notes in Computer Science, vol. LNCS 3203, Springer, pp. 200–208. doi: 10.1007/b99787

Ewe, C.T., Cheung, P.Y.K. and Constantinides, G.A. (2005) Error modelling of dual fixed-point arithmetic and its application in field programmable logic. International Conference on Field Programmable Logic and Applications, Tampere, Finland (24–26 August, 2005), pp. 124– 129. doi: 10.1109/FPL.2005.1515710

Fabbri, R., Costa, L.D.F., Torelli, J.C. and Bruno, O.M. (2008) 2D Euclidean distance transform algorithms: A comparative survey, ACM Computing Surveys, 40 (1), Article #2 (44 pages). doi: 10.1145/1322432.1322434

Fahmy, S.A., Cheung, P.Y.K. and Luk, W. (2005) Novel FPGA-based implementation of median and weighted median filters for image processing. International Conference on Field Programmable Logic and Applications, Tampere, Finland (24–26 August, 2005), pp. 142– 147. doi: 10.1109/FPL.2005.1515713

Fant, K.M. (1986) A nonaliasing, real-time spatial transform technique. IEEE Computer Graphics and Applications, 6 (1), 71–80. doi: 10.1109/MCG.1986.276613

Farid, H. and Simoncelli, E.P. (2004) Differentiation of discrete multidimensional signals. IEEE Transactions on Image Processing, 13 (4), 496–508. doi: 10.1109/TIP.2004.823819

Feig, E. and Winograd, S. (1992) Fast algorithms for the discrete cosine transform. IEEE Transactions on Signal Processing, 40 (9), 2174–2193. doi: 10.1109/78.157218

Ferrari, L.A. and Park, J.H. (1997) An efficient spline basis for multi-dimensional applications: image interpolation. IEEE International Symposium on Circuits and Systems, Hong Kong, vol. 1 (9–12 June, 1997), pp. 757– 760. doi: 10.1109/ISCAS.1997.609003

Ferrari, L.A., Park, J.H., Healey, A. and Leeman, S. (1999) Interpolation using a fast spline transform (FST). IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 46 (8), 891–906. doi: 10.1109/81.780371

Finlayson, G.D., Drew, M.S. and Funt, B.V. (1994) Color constancy: generalized diagonal transforms suffice. Journal of the Optical Society of America A, 11 (11), 3011–3019. doi: 10.1364/JOSAA.11.003011

Finlayson, G.D., Hordley, S.D. and Hubel, P.M. (2001) Color by correlation: a simple, unifying framework for color constancy. IEEE Transactions on Pattern Analysis and Machine Intelligence, 20 (11), 1209–1221. doi: 10.1109/34.969113

Fitch, J.P., Coyle, E.J. and Gallagher, N.C. (1984) Median filtering by threshold decomposition. IEEE Transactions on Acoustics, Speech and Signal Processing, 32 (6), 1183–1188. doi: 10.1109/TASSP.1984.1164468

Fitch, J.P., Coyle, E.J. and Gallagher, N.C. (1985) Threshold decomposition of multidimensional ranked order operations. IEEE Transactions on Circuits and Systems, 32 (5), 445–450. doi: 10.1109/TCS.1985.1085740

Floyd, R.W. and Steinberg, L. (1975) An adaptive algorithm for spatial grey scale, in Society for Information Display Symposium Digest of Technical Papers, Society for Information Display, Campbell, California, pp. 36–37.

Flynn, M. (1972) Some computer organizations and their effectiveness. IEEE Transactions on Computers, C-21 (9), 948–960. doi: 10.1109/TC.1972.5009071

Foley, J.D. and Van Dam, A. (1982) Fundamentals of Interactive Computer Graphics, Addison-Wesley, Reading, Massachusetts.

Forster, B., Van De Ville, D., Berent, J., Sage, D. and Unser, M. (2004) Complex wavelets for extended depth-of-field: A new method for the fusion of multichannel microscopy images. Microscopy Research and Technique, 65 (1–2), 33–42. doi: 10.1002/jemt.20092

Fossum, E.R. (1993) Active pixel sensors: are CCDs dinosaurs? in Charge-Coupled Devices and Solid State Optical Sensors III, San Jose, California, USA (2–3 February, 1993), vol. 1900, SPIE, pp. 2–14. doi: 10.1117/12.148585

Frank, M., Plaue, M., Rapp, H., Köthe, U., Jähne, B. and Hamprecht, F.A. (2009) Theoretical and experimental error analysis of continuous-wave time-of-flight range cameras. Optical Engineering, 48 (1), 013601- 1-16. doi: 10.1117/1.3070634

Freeman, H. (1961) On the encoding of arbitrary geometric configurations. IRE Transactions on Electronic Computers, 10 (2), 260–268. doi: 10.1109/TEC.1961.5219197

Freeman, H. (1974) Computer processing of line-drawing images. ACM Computing Surveys, 6 (1), 57–97. doi: 10.1145/356625.356627

Freeman, H. and Davis, L.S. (1977) A corner finding algorithm for chain coded curves. IEEE Transactions on Computers, 26 (3), 297–303. doi: 10.1109/TC.1977.1674825

Freeman, H. and Shapira, R. (1975) Determining the minimum area encasing rectangle for an arbitrary enclosed curve. Communications of the ACM, 18 (7), 409–413. doi: 10.1145/360881.360919

Frei, W. (1977) Image enhancement by histogram hyperbolisation. Computer Graphics and Image Processing, 6 (3), 286–294. doi: 10.1016/S0146-664X(77)80030-0

Friedman, E.G. (2001) Clock distribution networks in synchronous digital integrated circuits. Proceedings of the IEEE, 89 (5), 665–692. doi: 10.1109/5.929649

Fryer, J.G., Clarke, T.A. and Chen, J. (1994) Lens distortion for simple C-mount lenses. International Archives of Photogrammetry and Remote Sensing, 30 (5), 97–101.

Fu, H., Mencer, O. and Luk, W. (2006) Comparing floating-point and logarithmic number representations for reconfigurable acceleration. International Conference on Field Programmable Technology, Bangkok, Thailand (13–15 December, 2006), pp. 337– 340. doi: 10.1109/FPT.2006.270342

Fu, H., Mencer, O. and Luk, W. (2008) Optimizing residue arithmetic on FPGAs. International Conference on Field Programmable Technology, Taipei, Taiwan (7–10 December, 2008), pp. 41– 48. doi: 10.1109/FPT.2008.4762364

Funt, B., Barnard, K. and Martin, L. (1998) Is machine colour constancy good enough? in 5th European Conference on Computer Vision (ECCV'98), Freiburg, Germany (2–6 June, 1998), Lecture Notes in Computer Science, vol. LNCS 1406, Springer, pp. 445–459. doi: 10.1007/BFb0055655

Galloway, D. (1995) The Transmogrifier C hardware description language and compiler for FPGAs. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, USA (19–21 April, 1995), pp. 136– 144. doi: 10.1109/FPGA.1995.477419

Gangadhar, M. and Bhatia, D. (2003) FPGA based EBCOT architecture for JPEG 2000. IEEE International Conference on Field-Programmable Technology (FPT), Tokyo, Japan (15–17 December, 2003), pp. 228– 233. doi: 10.1109/FPT.2003.1275752

Garibotto, G. and Lambarelli, L. (1979) Fast online implementation of two-dimensional median filtering. Electronics Letters, 15 (1), 24–25. doi: 10.1049/el:19790018

Gasteratos, I., Gasteratos, A. and Andreadis, I. (2006) An algorithm for adaptive mean filtering and its hardware implementation. Journal of VLSI Signal Processing, 44 (1–2), 63–78. doi: 10.1007/s11265-006-5920-3

Geer, D. (2005) Chip makers turn to multicore processors. Computer, 38 (5), 11–13. doi: 10.1109/MC.2005.160

Genest, G., Chamberlain, R. and Bruce, R. (2007) Programming an FPGA-based super computer using a C-to-VHDL compiler: DIME-C. Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), Edinburgh, UK (5–8 August, 2007), pp. 280– 286. doi: 10.1109/AHS.2007.89

Geninatti, S.R., Benitez, J.I.B., Calvio, M.H., Mata, N.G. and Luna, J.G. (2009) FPGA implementation of the generalized Hough transform. International Conference on Reconfigurable Computing and FPGAs (ReConFig '09), Cancun, Quintana Roo, Mexico (9–11 December, 2009), pp. 172– 177. doi: 10.1109/ReConFig.2009.78

Gershon, R., Jepson, A.D. and Tsotsos, J.K. (1987) From [R,G,B] to surface reflectance: computing color constant descriptors in images. International Joint Conference on Artificial Intelligence, Milan, Italy, vol. 2 (23–29 August, 1987), pp. 755– 758.

Geyer, C., Meingast, M. and Sastry, S. (2005) Geometric models of rolling-shutter cameras. 6th Workshop on Omnidirectional Vision, Camera Networks and Non-classical Cameras (OMNIVIS05), Beijing, China (21 October, 2005), pp. 12– 19.

Gigliotti, P. (2004) Implementing Barrel Shifters Using Multipliers, Application note XAPP195 (v1.1), Xilinx Inc.

Gilblom, D.L., Yoo, S.K. and Ventura, P. (2003) Real-time color imaging with a CMOS sensor having stacked photodiodes, in Ultrahigh- and High-Speed Photography, Photonics, and Videography, San Diego, California, USA (7 August, 2003), vol. 5210, SPIE, pp. 105–115. doi: 10.1117/12.506206

Gilman, A. (2009) Least-squares optimal interpolation for direct image super-resolution. PhD Thesis, School of Engineering and Advanced Technology, Massey University, Palmerston North. hdl: 10179/893

Gilman, A. and Bailey, D.G. (2007) Noise characteristics of higher order predictive interpolation for sub-pixel registration. IEEE Symposium on Signal Processing and Information Technology, Cairo, Egypt (15–18 December, 2007), pp. 269– 274. doi: 10.1109/ISSPIT.2007.4458153

Gilman, A., Bailey, D. and Marsland, S. (2010) Least-squares optimal interpolation for fast image super-resolution. 5th IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2010), Ho Chi Minh City, Vietnam (13–15 January, 2010), pp. 29– 34. doi: 10.1109/DELTA.2010.59

Ginosar, R. (2003) Fourteen ways to fool your synchronizer. Ninth International Symposium on Asynchronous Circuits and Systems, Vancouver, Canada (12–15 May, 2003), pp. 89– 96. doi: 10.1109/ASYNC.2003.1199169

Gionis, A., Indyk, P. and Motwani, R. (1999) Similarity search in high dimensions via hashing. 25th International Conference on Very Large Data Bases, Edinburgh, UK (7–10 September, 1999), pp. 518– 529.

Goertzel, G. (1958) An algorithm for the evaluation of finite trigonometric series. The American Mathematical Monthly, 65 (1), 34–35.

Goetcherian, V. (1980) From binary to grey tone imaging processing using fuzzy logic concepts. Pattern Recognition, 12 (1), 7–15. doi: 10.1016/0031-3203(80)90049-7

Gokhale, M.B. and Stone, J.M. (1998) NAPA C: compiling for a hybrid RISC/FPGA architecture. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, USA (15–17 April, 1998), pp. 126– 135. doi: 10.1109/FPGA.1998.707890

Gokhale, M., Stone, J., Arnold, J. and Kalinowski, M. (2000) Stream-oriented FPGA computing in the Streams-C high level language. IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, California, USA (17–19 April, 2000), pp. 49– 56. doi: 10.1109/FPGA.2000.903392

Golay, M.J.E. (1969) Hexagonal parallel pattern transformations. IEEE Transactions on Computers, C-18 (8), 733–740.

Goldberg, D. (1991) What every computer scientist should know about floating-point arithmetic. ACM Computing Surveys, 23 (1), 6–48. doi: 10.1145/103162.103163

Goldman, D.B. and Chen, J.H. (2005) Vignette and exposure calibration and compensation. Tenth IEEE International Conference on Computer Vision (ICCV 2005), Beijing, China, vol. 1 (17–21 October, 2005), pp. 899– 906. doi: 10.1109/ICCV.2005.249

Golin, E.J., Feng, A.C., Huang, L. and Hughes, E. (1993) A visual design environment. 1993 IEEE/ACM International Computer-Aided Design (ICCAD-93), Santa Clara, California, USA (7–11 November, 1993), pp. 364– 367. doi: 10.1109/ICCAD.1993.580082

Gonzalez, R.C. and Woods, R.E. (2004) Digital Image Processing, Using MATLAB, Pearson Prentice Hall.

Gonzalez, R.C. and Woods, R.E. (2008) Digital Image Processing, 3rd edn, Prentice-Hall, New Jersey.

Graham, P.S. (2001) Logical hardware debuggers for FPGA-based systems. PhD Thesis, Department of Electrical and Computer Engineering, Brigham Young University.

Graham, P., Nelson, B. and Hutchings, B. (2001) Instrumenting bitstreams for debugging FPGA circuits. IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'01), Rohnert Park, California, USA (30 April–2 May, 2001), pp. 41– 50. doi: 10.1109/FCCM.2001.26

Gregori, S. (2009) Full Linux on FPGA, in Embedded Computing Conference, Winterthur, Switzerland, pp 4B2 (26 May, 2009).

Gribbon, K.T. and Bailey, D.G. (2004) A novel approach to real time bilinear interpolation. 2nd IEEE International Workshop on Electronic Design, Test, and Applications (DELTA 2004), Perth, Australia (28–30 January, 2004), pp. 126– 131. doi: 10.1109/DELTA.2004.10055

Gribbon, K.T., Johnston, C.T. and Bailey, D.G. (2003) A real-time FPGA implementation of a barrel distortion correction algorithm with bilinear interpolation. Image and Vision Computing New Zealand (IVCNZ'03), Palmerston North, New Zealand (26–28 November, 2003), pp. 408– 413.

Gribbon, K.T., Bailey, D.G. and Johnston, C.T. (2004) Colour edge enhancement. Image and Vision Computing New Zealand (IVCNZ'04), Akaroa, New Zealand (21–23 November, 2004), pp. 291– 296.

Gribbon, K.T., Johnston, C.T. and Bailey, D.G. (2005) Design patterns for image processing algorithm development on FPGAs. IEEE Region 10 Conference (IEEE Tencon'05), Melbourne, Australia (21–24 November, 2005). doi: 10.1109/TENCON.2005.301109

Gribbon, K.T., Johnston, C.T. and Bailey, D.G. (2006) Using design patterns to overcome image processing constraints on FPGAs. 3rd IEEE International Workshop on Electronic Design, Test, and Applications (DELTA 2006), Kuala Lumpur, Malaysia (17–19 January, 2006), pp. 47– 53. doi: 10.1109/DELTA.2006.93

Gribbon, K.T., Bailey, D.G. and Bainbridge-Smith, A. (2007) Development issues in using FPGAs for image processing. Image and Vision Computing New Zealand (IVCNZ), Hamilton, New Zealand (5–7 December, 2007), pp. 217– 222.

Guccione, S., Levi, D. and Sundararajan, P. (1999) JBits: Java based interface for reconfigurable computing. Military and Aerospace Applications of Programmable Devices and Technologies International Conference, Laurel, Maryland, USA (28–30 September, 1999).

Gunturk, B.K., Altunbasak, Y. and Mersereau, R.M. (2002) Color plane interpolation using alternating projections. IEEE Transactions on Image Processing, 11 (9), 997–1013. doi: 10.1109/TIP.2002.801121

Habegger, A., Stahel, A., Goette, J. and Jacomet, M. (2010) An efficient hardware implementation of a reciprocal unit. 5th IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2010), Ho Chi Minh City, Vietnam (13–15 January, 2010), pp. 183– 187. doi: 10.1109/DELTA.2010.65

Hadley, J.D. and Hutchings, B.L. (1995) Design methodologies for partially reconfigured systems. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, USA (19–21 April, 1995), pp. 78– 84. doi: 10.1109/FPGA.1995.477412

Hagemeyer, J., Kettelhoit, B., Koestner, K. and Porrmann, M. (2007) Design of homogeneous communication infrastructures for partially reconfigurable FPGAs. 2007 International Conference on Engineering of Reconfigurable Systems (ERSA'07), Las Vegas, USA (25–28 June, 2007).

Haldar, M., Nayak, A., Choudhary, A. and Banerjee, P. (2001a) Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB(R). Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan (30 January–2 February, 2001), pp. 645– 648. doi: 10.1145/370155.370572

Haldar, M., Nayak, A., Shenoy, N., Choudhary, A. and Banerjee, P. (2001b) FPGA hardware synthesis from MATLAB. in Fourteenth International Conference on VLSI Design, Bangalore, India (3–7 January, 2001), pp. 299– 304. doi: 10.1109/ICVD.2001.902676

Hall, M.W., Anderson, J.M., Amarasinghe, S.P., Murphy, B.R., Liao, S.W., Bugnion, E. and Lam, M.S. (1996) Maximizing multiprocessor performance with the SUIF compiler. Computer, 29 (12), 84–89. doi: 10.1109/2.546613

Hammes, J.P., Draper, B.A. and Böhm, A.P.W. (1999) Sassy: a language and optimizing compiler for image processing on reconfigurable computing systems, in First International Conference on Computer Vision Systems (ICVS'99), Las Palmas, Spain (13–15 January, 1999), Lecture Notes in Computer Science, vol. LNCS 1542, Springer, pp. 83–97. doi: 10.1007/3-540-49256-9_6

Haralick, R.M. and Shapiro, L.G. (1991) Glossary of computer vision terms. Pattern Recognition, 24 (1), 69–93. doi: 10.1016/0031-3203(91)90117-N

Haralick, R.M., Shanmugam, K. and Dinstein, I.H. (1973) Textural features for image classification. IEEE Transactions on Systems, Man and Cybernetics, 3 (6), 610–621. doi: 10.1109/TSMC.1973.4309314

Harber, R. and Neudeck, S.B.G. (1985) VLSI implementation of a fast rank order filtering algorithm. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '85), Tampa, Florida, USA (March 26–29, 1985) pp. 1396– 1399.

Harris, F.J. (1978) On the use of windows for harmonic analysis with the discrete Fourier transform. Proceedings of the IEEE 66 (1), 51–83. doi: 10.1109/PROC.1978.10837

Harriss, T., Walke, R., Kienhuis, B. and Deprettere, E. (2002) Compilation from Matlab to process networks realized in FPGA. Design Automation for Embedded Systems, 7 (4), 385–403. doi: 10.1023/A:1020367508848

Hartley, R. (1991) Optimization of canonic signed digit multipliers for filter design. IEEE International Symposium on Circuits and Systems, Singapore, vol. 4 (11–14 June, 1991) pp. 1992– 1995. doi: 10.1109/ISCAS.1991.176054

Haselman, M. (2005) A comparison of floating point and logarithmic number systems for FPGAs. Master of Science Thesis, Department of Electrical Engineering, University of Washington.

Haselman, M., Beauchamp, M., Wood, A., Hauck, S., Underwood, K. and Hemmert, K.S. (2005) A comparison of floating point and logarithmic number systems for FPGAs. 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), Napa, California, USA (18–20 April, 2005), pp. 181– 190. doi: 10.1109/FCCM.2005.6

Hassler, H. and Takagi, N. (1995) Function evaluation by table look-up and addition. 12th Symposium on Computer Arithmetic, Bath, UK (19–21 July, 1995), pp. 10– 16. doi: 10.1109/ARITH.1995.465382

Hauck, S., Hosler, M.M. and Fry, T.W. (2000) High-performance carry chains for FPGAs. IEEE Transactions on VLSI Systems, 8 (2), 138–147. doi: 10.1109/92.831434

Hauck, S., Fry, T.W., Hosler, M.M. and Kao, J.P. (2004) The Chimaera reconfigurable functional unit. IEEE Transactions on VLSI Systems, 12 (2), 206–217. doi: 10.1109/TVLSI.2003.821545

Haviland, G.L. and Tuszynski, A.A. (1980) A CORDIC arithmetic processor chip. IEEE Journal of Solid-State Circuits, 15 (1), 4–15. doi: 10.1109/JSSC.1980.1051332

He, S. and Torkelson, M. (1996) A new approach to pipeline FFT processor. 10th International Parallel Processing Symposium (IPPS'96), Honolulu, Hawaii, USA (15–19 April, 1996), pp. 766– 770. doi: 10.1109/IPPS.1996.508145

He, L., Chao, Y. and Suzuki, K. (2007) A linear-time two-scan labelling algorithm. IEEE International Conference on Image Processing (ICIP 2007), San Antonio, Texas, USA, vol. 5 (16–19 September, 2007), pp. 241– 244. doi: 10.1109/ICIP.2007.4379810

He, L., Chao, Y. and Suzuki, K. (2008) A run-based two-scan labeling algorithm. IEEE Transactions on Image Processing, 17 (5), 749–756. doi: 10.1109/TIP.2008.919369

Hedberg, H., Kristensen, F. and Owall, V. (2007) Implementation of a labeling algorithm based on contour tracing with feature extraction. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Louisiana, USA (27–30 May, 2007), pp. 1101– 1104. doi: 10.1109/ISCAS.2007.378202

Heikkila, J. and Silven, O. (1997) A four-step camera calibration procedure with implicit correction. IEEE Computer Society Conference on Computer Vision and Pattern Recognition, San Juan, Puerto Rico (17–19 June, 1997), pp. 1106– 1112. doi: 10.1109/CVPR.1997.609468

Heikkila, J. and Silven, O. (1999) A real-time system for monitoring of cyclists and pedestrians. Second IEEE Workshop on Visual Surveillance, Fort Collins, Colorado, USA (26 June, 1999), pp. 74– 81. doi: 10.1109/VS.1999.780271

Herbordt, M.C., VanCourt, T., Gu, Y., Sukhwani, B., Conti, A., Model, J. and DiSabello, D (2007) Achieving high performance with FPGA-based computing. IEEE Computer, 40 (3), 50–57. doi: 10.1109/MC.2007.79

Heygster, G. (1982) Rank filters in digital image processing. Computer Graphics and Image Processing, 19 (2), 148–164. doi: 10.1016/0146-664X(82)90105-8

Hezel, S., Kugel, A., Manner, R. and Gavrila, D.M. (2002) FPGA-based template matching using distance transforms. Symposium on Field-Programmable Custom Computing Machines, Napa, California, USA (22–24 April, 2002), pp. 89– 97. doi: 10.1109/FPGA.2002.1106664

Hirata, T. (1996) A unified linear-time algorithm for computing distance maps. Information Processing Letters, 58 (3), 129–133. doi: 10.1016/0020-0190(96)00049-X

Hoare, C.A.R. (1985) Communicating Sequential Processes, Prentice-Hall International, London, UK.

Hodgson, R.M., Bailey, D.G., Naylor, M.J., Ng, A.L.M. and McNeill, S.J. (1985) Properties, implementations and applications of rank filters. Image and Vision Computing, 3 (1), 3–14. doi: 10.1016/0262-8856(85)90037-X

Hoffmann, G. (2000) CIE colour space. Available from http://www.fho-emden.de/~hoffmann/ciexyz29082000.pdf [cited 24 January, 2010].

Hoisko, S., Hakkarainen, H., Vihavainen, K. and Isoaho, J. (1996) Specification, hardware implementation and prototyping environment for image processing algorithms. IEEE International Symposium on Circuits and Systems (ISCAS '96), Atlanta, Georgia, USA, vol. 4 (12–15 May, 1996), pp. 834– 837. doi: 10.1109/ISCAS.1996.542154

Hollitt, C. (2009) Reduction of computational complexity of Hough transforms using a convolution approach. 24th International Conference Image and Vision Computing New Zealand (IVCNZ '09), Wellington, New Zealand (23–25 November, 2009), pp. 373– 378. doi: 10.1109/IVCNZ.2009.5378379

Horta, E.L., Lockwood, J.W., Taylor, D.E. and Parlour, D. (2002) Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. ACM IEEE Design Automation Conference, New Orleans, Louisiana, USA (10–14 June, 2002), pp. 343– 348. doi: 10.1145/513918.514007

Hough, P.V.C. (1962) Method and means for recognizing complex patterns, United States of America patent 3069654.

Hsia, S.C. (2004) Fast high-quality color-filter-array interpolation method for digital camera systems. Journal of Electronic Imaging, 13 (1), 244–247. doi: 10.1117/1.1631443

Huang, C.T. and Mitchell, O.R. (1994) A Euclidean distance transform using grayscale morphology decomposition. IEEE Transactions on Pattern Analysis and Machine Intelligence, 16 (4), 443–448. doi: 10.1109/34.277600

Huang, T.S., Yang, G.Y. and Tang, G.Y. (1979) A fast two dimensional median filtering algorithm. IEEE Transactions on Acoustics, Speech and Signal Processing, 27 (1), 13–18. doi: 10.1109/TASSP.1979.1163188

Huang, C.T., Tseng, P.C. and Chen, L.G. (2004) Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. IEEE Transactions on Signal Processing, 52 (4), 1080–1089. doi: 10.1109/TSP.2004.823509

Hudson, R.D., Lehn, D.I. and Athanas, P.M. (1998) A run-time reconfigurable engine for image interpolation. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, USA (15–17 April, 1998), pp. 88– 95. doi: 10.1109/FPGA.1998.707886

Huffman, D.A. (1952) A method for the construction of minimum-redundancy codes. Proceedings of the IRE 40 (9), 1098–1101. doi: 10.1109/JRPROC.1952.273898

Hummel, R.A. (1975) Histogram modification techniques. Computer Graphics and Image Processing, 4 (3), 209–224. doi: 10.1016/0146-664X(75)90009-X

Hummel, R.A. (1977) Image enhancement by histogram transformation. Computer Graphics and Image Processing, 6 (2), 184–195. doi: 10.1016/S0146-664X(77)80011-7

Hunt, B.R. (1983) Digital image processing. Advances in Electronics and Electron Physics, 60, 161–221. doi: 10.1016/S0065-2539(08)60890-2

Hutchings, B., Bellows, P., Hawkins, J., Hemmert, S., Nelson, B. and Rytting, M. (1999) A CAD suite for high-performance FPGA design. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99), Napa Valley, California, USA (21–23 April, 1999), pp. 12– 24. doi: 10.1109/FPGA.1999.803663

Hutton, M., Schleicher, J., Lewis, D., Pedersen, B., Yuan, R., Kaptanoglu, S., Baeckler, G., Ratchev, B., Padalia, K., Bourgeault, M., Lee, A., Kim, H. and Saini, R. (2004) Improving FPGA performance and area using an adaptive logic module, in 14th International Conference on Field Programmable Logic and Applications, Antwerp, Belgium (29 August–1 September, 2004), Lecture Notes in Computer Science, vol. LNCS 3203, Springer, pp. 135–144. doi: 10.1007/b99787

Hwang, J.N. and Jong, J.M. (1990) Systolic architecture for 2-D rank order filtering. International Conference on Application Specific Array Processors, Princeton, New Jersey, USA (5–7 September, 1990), pp. 90– 99. doi: 10.1109/ASAP.1990.145446

Hwang, J., Milne, B., Shirazi, N. and Stroomer, J.D. (2001) System level tools for DSP in FPGAs, in Field-Programmable Logic and Applications, Belfast, UK (27–29 August, 2001), Lecture Notes in Computer Science, vol. LNCS 2147, Springer, pp. 534–543. doi: 10.1007/3-540-44687-7_55

IEEE (2004) IEC 62050-2005 First edition 2005-07 IEEE Std 1076 6 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. IEEE/IEC. doi: 10.1109/IEEESTD.2004.94802

IEEE (2005) IEC 62142-2005 First edition 2005-06 IEEE Std 1364.1 Verilog Register Transfer Level Synthesis. IEEE/IEC. doi: 10.1109/IEEESTD.2005.339572

IEEE (2006a) 1364-2005 IEEE Standard for Verilog Hardware Description Language. IEEE. doi: 10.1109/IEEESTD.2006.99495

IEEE (2006b) 1666-2005 IEEE Standard System C Language Reference Manual. IEEE. doi: 10.1109/IEEESTD.2006.99475

IEEE (2008) 754-2008 IEEE Standard for Floating-Point Arithmetic. IEEE. doi: 10.1109/IEEESTD.2008.4610935

IEEE (2009) 1076-2008 IEEE Standard VHDL Language Reference Manual. IEEE. doi: 10.1109/IEEESTD.2009.4772740

Illingworth, J. and Kittler, J. (1987) The adaptive Hough transform. IEEE Transactions on Pattern Analysis and Machine Intelligence, 9 (5), 690–698. doi: 10.1109/TPAMI.1987.4767964

Illingworth, J. and Kittler, J. (1988) A survey of the Hough transform. Computer Vision, Graphics, and Image Processing, 44 (1), 87–116. doi: 10.1016/S0734-189X(88)80033-1

Irturk, A., Benson, B. and Kastner, R. (2008) Automatic generation of decomposition based matrix inversion architectures. International Conference on Field Programmable Technology, Taipei, Taiwan (7–10 December, 2008), pp. 373– 376. doi: 10.1109/FPT.2008.4762421

Iskander, Y., Craven, S., Chandrasekharan, A., Rajagopalan, S., Subbarayan, G. Frangieh, T. and Patterson, C. (2010) Using partial reconfiguration and high-level models to accelerate FPGA design validation. International Conference on Field Programmable Technology (FPT 2010), Beijing, China (8–10 December, 2010), pp. 341– 344.

ISO (1992) Digital compression and coding of continuous-tone still images – requirements and guidelines, ISO/IEC 10918-1.

ISO (2000) JPEG 2000 image coding system – part 1: core coding system, ISO/IEC 15444-1:2000.

Isshiki, T. and Dai, W.W.M. (1995) High-level bit-serial datapath synthesis for multi-FPGA systems. International Symposium on Field Programmable Gate Arrays, Monterey, California, USA (12–14 February, 1995), pp. 167– 173. doi: 10.1145/201310.201336

Jablonski, M. and Gorgon, M. (2004) Handel-C implementation of classical component labelling algorithm. 2004 Euromicro Symposium on Digital System Design (DSD 2004), Rennes, France (31 August–3 September, 2004), pp. 387– 393. doi: 10.1109/DSD.2004.1333301

Jain, A.K. (1989) Fundamentals of Image Processing, Prentice Hall, Englewood Cliffs, New Jersey.

Jarvis, R.A. (1983) A perspective on range finding techniques for computer vision. IEEE Transactions on Pattern Analysis and Machine Intelligence, 5 (2), 122–139. doi: 10.1109/TPAMI.1983.4767365

Jiulun, F. and Winxin, X. (1997) Minimum error thresholding: a note. Pattern Recognition Letters, 18 (8), 705–709. doi: 10.1016/S0167-8655(97)00059-7

Johnson, D. and Defossez, M. (1999) Programming a Xilinx FPGA in “C”. Xcell Journal (34), 26–30.

Johnson, D. (2000) Architectural synthesis from behavioral code to implementation in a Xilinx FPGA. Xcell Journal (36), 23–25.

Johnston, C.T. (2009) VERTIPH: a visual environment for real-time image processing on hardware. PhD Thesis, School of Engineering and Advanced Technology, Massey University: Palmerston North. hdl: 10179/1219

Johnston, C.T., Bailey, D.G., Lyons, P. and Gribbon, K.T. (2004) Formalisation of a visual environment for real time image processing in hardware (VERTIPH). Image and Vision Computing New Zealand (IVCNZ'04), Akaroa, New Zealand (21–23 November, 2004), pp. 297– 302.

Johnston, C.T., Bailey, D.G. and Gribbon, K.T. (2005a) Optimisation of a colour segmentation and tracking algorithm for real-time FPGA implementation. Image and Vision Computing New Zealand (IVCNZ'05), Dunedin, New Zealand (28–29 November, 2005), pp. 422– 427.

Johnston, C.T., Gribbon, K.T. and Bailey, D.G. (2005b) FPGA based remote object tracking for real-time control. International Conference on Sensing Technology, Palmerston North, New Zealand (21–23 November, 2005), pp. 66– 71.

Johnston, C.T., Bailey, D.G. and Lyons, P. (2006a) A visual environment for real time image processing in hardware (VERTIPH). EURASIP Journal on Embedded Systems, 2006, no. Article ID 72962. doi: 10.1155/ES/2006/72962

Johnston, C.T., Bailey, D.G. and Lyons, P. (2006b) Towards a visual notation for pipelining in a visual programming language for programming FPGAs. 7th International Conference of the NZ chapter of the ACM's Special Interest Group on Human-Computer Interaction (CHINZ 2006), Christchurch, New Zealand (6–7 July, 2006), ACM International Conference Proceeding Series, vol. 158, pp. 1– 9. doi: 10.1145/1152760.1152761

Johnston, C.T., Lyons, P. and Bailey, D.G. (2008) A visual notation for processor and resource scheduling. IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2008), Hong Kong (23–25 January, 2008), pp. 296– 301. doi: 10.1109/DELTA.2008.76

Johnston, C.T., Bailey, D.G. and Lyons, P. (2010) Notations for multiphase pipelines. 5th IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2010), Ho Chi Minh City, Vietnam (13–15 January, 2010), pp. 212– 216. doi: 10.1109/DELTA.2010.29

Jongenelen, A.P.P., Carnegie, D.A., Dorrington, A.A. and Payne, A.D. (2008) Heterodyne range imaging in real-time. International Conference on Sensing Technology, Tainan, Taiwan (30 November–3 December, 2008), pp. 57– 62. doi: 10.1109/ICSENST.2008.4757073

Jongenelen, A.P.P., Bailey, D.G., Payne, A.D., Carnegie, D.A. and Dorrington, A.A. (2010) Efficient FPGA implementation of homodyne-based time of flight range imaging. Journal of Real-Time Image Processing. doi: 10.1007/s11554-010-0173-6

Jongenelen, A.P.P., Bailey, D.G., Payne, A.D., Dorrington, A.A. and Carnegie, D.A. (2011) Analysis of errors in ToF range imaging with dual-frequency modulation. IEEE Transactions on Instrumentation and Measurement, 60 (5), 1861–1868. doi: 10.1109/TIM.2010.2089190

Justusson, B.I. (1981) Median filtering: statistical properties, in Two Dimensional Digital Signal Processing II, Topics in Applied Physics, vol. 43 (ed. T.S. Huang), Springer-Verlag, Berlin, pp. 161–196. doi: 10.1007/BFb0057597

Kakumanua, P., Makrogiannisa, S. and Bourbakis, N. (2007) A survey of skin-color modeling and detection methods. Pattern Recognition, 40 (3), 1106–1122. doi: 10.1016/j.patcog.2006.06.010

Kalman, R.E. (1960) A new approach to linear filtering and prediction problems. Journal of Basic Engineering, 82 (1), 35–45.

Kambe, T., Yamada, A., Nishida, K., Okada, K., Ohnishi, M., Kay, A., Boca, P., Zammit, V. and Nomura, T. (2001) A C-based synthesis system, Bach, and its application. 2001 Asia and South Pacific Design Automation Conference, Yokohama, Japan (2001), pp. 151– 155. doi: 10.1145/370155.370309

Kameda, Y. and Minoh, M. (1996) A human motion estimation method using 3-successive video frames. International Conference on Virtual Systems and Multimedia (VSMM'96), Gifu, Japan (18–20 September, 1996), pp. 135– 140.

Kamp, W.H.M., McLoughlin, I.V. and Bainbridge-Smith, A. (2006) An exploration of redundant number representations in FPGA. Electronics New Zealand Conference (ENZCon'06), Christchurch, New Zealand (27–29 November, 2006), pp. 63– 68.

Kannala, J. and Brandt, S. (2004) A generic camera calibration method for fish-eye lenses. 17th International Conference on Pattern Recognition (ICPR 2004), Surrey, UK, vol. 1 (23–26 August, 2004) pp. 10– 13. doi: 10.1109/ICPR.2004.1333993

Kao, J., Narendra, S. and Chandrakasan, A. (2002) Subthreshold leakage modeling and reduction techniques. IEEE/ACM International Conference on Computer Aided Design, San Jose, California, USA (10–14 November, 2002), pp. 141– 148. doi: 10.1145/774572.774593

Kapura, J.N., Sahoob, P.K. and Wong, A.K.C. (1985) A new method for gray-level picture thresholding using the entropy of the histogram. Computer Vision, Graphics, and Image Processing, 29 (3), 273–285. doi: 10.1016/0734-189X(85)90125-2

Karabernou, S.M., Kessal, L. and Terranti, F. (2005) Real-time FPGA implementation of Hough transform using gradient and CORDIC algorithm. Image and Vision Computing, 23 (11), 1009–1017. doi: 10.1016/j.imavis.2005.07.004

Kawada, S. and Maruyama, T. (2007) An approach for applying large filters on large images using FPGA. International Conference on Field Programmable Technology, Kitakyushu, Japan (12–14 December, 2007), pp. 201– 208. doi: 10.1109/FPT.2007.4439250

Kehtarnavaz, N. and Gamadia, M. (2006) Real-time image and video processing: from research to reality. Synthesis Lectures on Image, Video and Multimedia Processing. Morgan & Claypool. doi: 10.2200/S00021ED1V01Y200604IVM005

Keys, R.G. (1981) Cubic convolution interpolation for digital image processing. IEEE Transactions on Acoustics, Speech and Signal Processing, 29 (6), 1153–1160. doi: 10.1109/TASSP.1981.1163711

Khan, S., Bailey, D. and Sen Gupta, G. (2009) Simulation of triple buffer scheme (comparison with double buffering scheme). 2nd International Conference on Computer and Electrical Engineering (ICCEE 2009), Dubai, UAE, vol. 2 (28–30 December, 2009), pp. 403– 407. doi: 10.1109/ICCEE.2009.226

Khanna, V., Gupta, P. and Hwang, C.J. (2002) Finding connected components in digital images by aggressive reuse of labels. Image and Vision Computing, 20 (8), 557–568. doi: 10.1016/S0262-8856(02)00044-6

Kim, K. and Kumar, V.K.P. (1989) Parallel memory systems for image processing. IEEE Computer Society Conference on Computer Vision and Pattern Recognition, San Diego, California, USA (4–8 June, 1989), pp. 654– 659. doi: 10.1109/CVPR.1989.37915

Kim, S.D., Lee, J.H. and Kim, J.K. (1988) A new chain-coding algorithm for binary images using run-length codes. Computer Vision, Graphics, and Image Processing, 41 (1), 114–128. doi: 10.1016/0734-189X(88)90121-1

Kimmel, R. (1999) Demosaicing: image reconstruction from color CCD samples. IEEE Transactions on Image Processing, 8 (9), 1221–1228. doi: 10.1109/83.784434

Kingsbury, N.G. and Rayner, P.J.W. (1971) Digital filtering using logarithmic arithmetic. Electronics Letters, 7 (2), 56–58. doi: 10.1049/el:19710039

Kirsch, R.A. (1998) SEAC and the start of image processing at the National Bureau of Standards. IEEE Annals of the History of Computing, 20 (2), 7–13. doi: 10.1109/85.667290

Kittler, J. and Illingworth, J. (1986) Minimum error thresholding. Pattern Recognition, 19 (1), 41–47. doi: 10.1016/0031-3203(86)90030-0

Knuth, D.E. (1987) Digital halftones by dot diffusion. ACM Transactions on Graphics, 6 (4), 245–273. doi: 10.1145/35039.35040

Koc, C.K. and Johnson, S. (1994) Multiplication of signed-digit numbers. Electronics Letters, 30 (11), 840–841. doi: 10.1049/el:19940623

Koester, M., Kalte, H., Porrmann, M. and Rückert, U. (2007) Defragmentation algorithms for partially reconfigurable hardware. Thirteenth International Conference on Very Large Scale Integration of System on Chip, Perth, Australia, IFIP Advances in Information and Communication Technology, vol. IFIP 240 (17–19 October, 2007), pp. 41– 53. doi: 10.1007/978-0-387-73661-7_4

Kokufuta, K. and Maruyama, T. (2009) Real-time processing of local contrast enhancement on FPGA. International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic (31 August–2 September, 2009), pp. 288– 293. doi: 10.1109/FPL.2009.5272284

Koren, I. and Zinaty, O. (1990) Evaluating elementary functions in a numerical coprocessor based on rational approximations. IEEE Transactions on Computers, 39 (8), 1030–1037. doi: 10.1109/12.57042

Kota, K. and Cavallaro, J.R. (1993) Numerical accuracy and hardware tradeoffs for CORDIC arithmetic for special-purpose processors, IEEE Transactions on Computers, vol. 42, no. 7, pp. 769–779. doi: 10.1109/12.237718

Kouloheris, J.L. and El Gamal, A. (1991) FPGA performance versus cell granularity. IEEE Custom Integrated Circuits Conference, San Diego, California, USA, pp. 6.2/1-6.2/4 (12–15 May, 1991). doi: 10.1109/CICC.1991.164048

Kovac, M. and Ranganathan, N. (1995) JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard. Proceedings of the IEEE, 83 (2), 247–258. doi: 10.1109/5.364464

Krishnan, G. (2005) Flexibility with EasyPath FPGAs. Xcell Journal (55), 96–99.

Kung, S. (1985) VLSI array processors. IEEE ASSP Magazine, 2 (3), 4–22.

Kung, H.T. and Leiserson, C.E. (1978) Systolic Arrays (for VLSI). Symposium on Sparse Matrix Computations, Knoxville, Tennessee, USA (2–3 November, 1978), pp. 256– 282.

Kung, H.T. and Webb, J.A. (1986) Mapping image processing operations onto a linear systolic machine. Distributed Computing, 1 (4), 246–257. doi: 10.1007/BF01660036

Kuon, I. and Rose, J. (2006) Measuring the gap between FPGAs and ASICs. International Symposium on Field Programmable Gate Arrays, Monterey, California, USA (22–24 February, 2006), pp. 21– 30. doi: 10.1145/1117201.1117205

Kurak, C.W. (1991) Adaptive histogram equalization: a parallel implementation. Fourth Annual IEEE Symposium Computer-Based Medical Systems, Baltimore, Maryland, USA (12–14 May, 1991), pp. 192– 199. doi: 10.1109/CBMS.1991.128965

Lachowicz, S. and Pfleiderer, H.J. (2008) Fast evaluation of the square root and other nonlinear functions in FPGA. IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2008), Hong Kong (23–25 January, 2008), pp. 474– 477. doi: 10.1109/DELTA.2008.119

Lai, V. and Diessel, O. (2009) ICAP-I: a reusable interface for the internal reconfiguration of Xilinx FPGAs. International Conference on Field Programmable Technology (FPT'09), Sydney, Australia (9–11 December, 2009), pp. 357– 360. doi: 10.1109/FPT.2009.5377616

Lamoureux, J. and Wilton, S.J.E. (2006) FPGA clock network architecture: flexibility vs. area and power, in. International Symposium on Field Programmable Gate Arrays, Monterey, California, USA (22–24 February, 2006), pp. 101– 108. doi: 10.1145/1117201.1117216

Landsman, R.M., Scott, L.B. and Golay, M.J.E. (1965) Apparatus for counting bi-nucleate lymphocytes in blood, United States of America patent 3214574.

Langdon, G.G. (1984) An introduction to arithmetic coding. IBM Journal of Research and Development, 28 (2), 135–149. doi: 10.1147/rd.282.0135

Lattice (2007) LatticeXP Family Data Sheet, Vol. DS1001 V05.1., Lattice Semiconductor Corporation.

Lattice (2008a) LatticeECP/EC Family Data Sheet, Vol. DS1000 V02.7., Lattice Semiconductor Corporation.

Lattice (2008b) LatticeECP2/M Family Data Sheet, Vol. DS1006 V03.3., Lattice Semiconductor Corporation.

Lattice (2008c) LatticeSC/M Family Data Sheet, Vol. DS1004 V02.2., Lattice Semiconductor Corporation.

Lattice (2008d) LatticeXP2 Family Data Sheet, Vol. DS1009 V01.6., Lattice Semiconductor Corporation.

Lattice (2010) LatticeECP3 Family Data Sheet, Vol. DS1021 V01.6., Lattice Semiconductor Corporation.

Lavin, C., Padilla, M., Lundrigan, P., Nelson, B. and Hutchings, B. (2010) Rapid prototyping tools for FPGA designs: RapidSmith, in International Conference on Field Programmable Technology (FPT 2010), Beijing, China, pp 353--356 (8--10 December, 2010). doi: 10.1109/FPT.2010.5681429

Leavers, V.F. (1993) Which Hough transform? Computer Vision, Graphics, and Image Processing: Image Understanding, 58 (2), 250–264. doi: 10.1006/ciun.1993.1041

Lee, D. (1988) Scrambled storage for parallel memory systems. 15th Annual International Symposium on Computer Architecture, Honolulu, Hawaii, USA (30 May–2 June, 1988), pp. 232– 239. doi: 10.1109/ISCA.1988.5233

Lee, P. and Evagelos, A. (2008) An implementation of a multiplierless Hough transform on an FPGA platform using hybrid-log arithmetic, in Real-Time Image Processing 2008, San Jose, California, USA (28–29 January, 2008), vol. 6811, SPIE, pp. 68110G-1-10. doi: 10.1117/12.766459

Lee, H. and Park, R.H. (1990) Comments on An optimal multiple threshold scheme for image segmentation. IEEE Transactions on Systems, Man and Cybernetics, 20 (3), 741–742. doi: 10.1109/21.57290

Lee, C.R. and Salcic, Z. (1997) High-performance FPGA-based implementation of Kalman filter. Microprocessors and Microsystems, 21 (4), 257–265. doi: 10.1016/S0141-9331(97)00040-9

Lee, D.U., Luk, W., Villasenor, J. and Cheung, P.Y.K. (2003a) Hierarchical segmentation schemes for function evaluation. in IEEE International Conference on Field-Programmable Technology (FPT), Tokyo, Japan (15–17 December, 2003), pp. 92– 99. doi: 10.1109/FPT.2003.1275736

Lee, D.U., Luk, W., Villasenor, J. and Cheung, P.Y.K. (2003b) Non-uniform segmentation for hardware function evaluation, in International Conference on Field Programmable Logic and Applications (FPL 2003), Lisbon, Portugal (September 1–3, 2003), Lecture Notes in Computer Science, vol. LNCS 2778, Springer, pp. 796–807. doi: 10.1007/b12007

Leeser, M., Miller, S. and Yu, H. (2004) Smart camera based on reconfigurable hardware enables diverse real-time applications. 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), Napa, California, USA (20–23 April, 2004), pp. 147– 155. doi: 10.1109/FCCM.2004.53

Leeser, M., Theiler, J., Estlick, M., and Szymanski, J.J. (2000) Design tradeoffs in a hardware implementation of the K-means clustering algorithm. 2000 IEEE Sensor Array and Multichannel Signal Processing Workshop, Cambridge, Massachusetts (16–17 March, 2000), pp 520–524. doi: 10.1109/SAM.2000.878063

Leiserson, C.E. and Saxe, J.B. (1991) Retiming synchronous circuitry. Algorithmica, 6 (1–6), 5–35. doi: 10.1007/BF01759032

Leong, P.H.W. (2008) Recent trends in FPGA architectures and applications. IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2008), Hong Kong (23–25 January, 2008), pp. 137– 141. doi: 10.1109/DELTA.2008.14

Levine, B., Natarajan, S., Tan, C., Newport, D. and Bouldin, D. (1999) Mapping of an automated target recognition application from a graphical software environment to FPGA-based reconfigurable hardware. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99), Napa Valley, California, USA (21–23 April, 1999), pp. 292– 293. doi: 10.1109/FPGA.1999.803702

Lewis, D.M. (1990) An architecture for addition and subtraction of long word length numbers in the logarithmic number system. IEEE Transactions on Computers, 39 (11), 1325–1336. doi: 10.1109/12.61042

Li, Y. and Chu, W. (1996) A new non-restoring square root algorithm and its VLSI implementations. IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD '96 Austin, Texas, USA (7–9 October, 1996), pp. 538– 544. doi: 10.1109/ICCD.1996.563604

Li, M. and Lavest, J.M. (1996) Some aspects of zoom lens camera calibration. IEEE Transactions on Pattern Analysis and Machine Intelligence, 18 (11), 1105–1110. doi: 10.1109/34.544080

Liang, C.K., Chang, L.W. and Chen, H.H. (2008) Analysis and compensation of rolling shutter effect. IEEE Transactions on Image Processing, 17 (8), 1323–1330. doi: 10.1109/TIP.2008.925384

Liao, H., Mandal, M.K. and Cockburn, B.F. (2004) Efficient architectures for 1-D and 2-D lifting-based wavelet transforms. IEEE Transactions on Signal Processing, 52 (5), 1315–1326. doi: 10.1109/TSP.2004.826175

Lin, K.C. (2005) On improvement of the computation speed of Otsu's image thresholding. Journal of Electronic Imaging, 14 (2), 023011- 1-12. doi: 10.1117/1.1902997

Lindeberg, T. (1994) Scale-space theory: a basic tool for analysing structures at different scales. Journal of Applied Statistics, 21 (2), 225–270. doi: 10.1080/757582976

Litwiller, D. (2005) CMOS vs. CCD: maturing technologies, maturing markets. Photonics Spectra, 2005 (8), 54–59.

Liu, Y., Bouganis, C.S. and Cheung, P.Y.K. (2007) Efficient mapping of a Kalman filter into an FPGA using Taylor expansion. International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam, The Netherlands (27–29 August, 2007), pp. 345– 350. doi: 10.1109/FPL.2007.4380670

Liu, Q., Constantinides, G.A., Masselos, K. and Cheung, P.Y.K. (2008) Combining data reuse exploitation with data-level parallelization for FPGA targeted hardware compilation: a geometric programming framework. International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany (8–10 September, 2008), pp. 179– 184. doi: 10.1109/FPL.2008.4629928

Loeffler, C., Ligtenberg, A. and Moschytz, G.S. (1989) Practical fast 1-D DCT algorithms with 11 multiplications. 1989 International Conference on Acoustics, Speech, and Signal Processing (ICASSP-89), Glasgow, UK, vol. 2 (23–26 May, 1989) pp. 988– 991. doi: 10.1109/ICASSP.1989.266596

Longfield, S. and Chang, M.L. (2009) A parameterized stereo vision core for FPGAs. 17th IEEE Symposium on Field Programmable Custom Computing Machines (FCCM), Napa, California, USA (5–7 April, 2009) pp. 263– 265. doi: 10.1109/FCCM.2009.32

Lowe, D.G. (1999) Object recognition from local scale-invariant features. Seventh IEEE International Conference on Computer Vision, Corfu, Greece, vol. 2 (20–27 September, 1999), pp. 1150– 1157. doi: 10.1109/ICCV.1999.790410

Lowe, D.G. (2004) Distinctive image features from scale-invariant keypoints. International Journal of Computer Vision, 60 (2), 91–110. doi: 10.1023/B:VISI.0000029664.99615.94

Lu, W.S., Wang, H.P. and Antoniou, A. (1990) Design of two-dimensional FIR digital filters by using the singular-value decomposition. IEEE Transactions on Circuits and Systems, 37 (1), 35–46. doi: 10.1109/31.45689

Lubbers, E. and Platzner, M. (2007) ReconOS: an RTOS supporting hard- and software threads. International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam, The Netherlands (27–29 August, 2007), pp. 441– 446. doi: 10.1109/FPL.2007.4380686

Lucas, B.D. and Kanade, T. (1981) An iterative image registration technique with an application to stereo vision. 7th International Joint Conference on Artificial Intelligence, Vancouver, British Columbia, Canada (24–28 August, 1981), pp. 674– 679.

Lucke, L.E. and Parhi, K.K. (1992) Parallel structures for rank order and stack filters. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP-92), San Francisco, California, USA, vol. 5 (23–26 March, 1992) pp. 645– 648. doi: 10.1109/ICASSP.1992.226513

Lumia, R., Shapiro, L. and Zuniga, O. (1983) A new connected components algorithm for virtual memory computers. Computer Vision, Graphics and Image Processing, 22 (2), 287–300. doi: 10.1016/0734-189X(83)90071-3

Lyon, R.F. and Hubel, P.M. (2002) Eyeing the camera: into the next century. Tenth Color Imaging Conference: Color Science and Engineering Systems, Technologies, Applications, Scottsdale, Arizona, USA (November 12–15, 2002), pp. 349– 355.

Ma, N., Bailey, D. and Johnston, C. (2008) Optimised single pass connected components analysis. International Conference on Field Programmable Technology, Taipei, Taiwan (8–10 December, 2008), pp. 185– 192. doi: 10.1109/FPT.2008.4762382

Mahalanobis, P.C. (1936) On the generalised distance in statistics. Proceedings of the National Institute of Sciences of India, 2 (1), 49–55.

Mandler, E. and Oberlander, M.F. (1990) One-pass encoding of connected components in multivalued images. 10th International Conference on Pattern Recognition, Atlantic City, New Jersey, USA, vol. 2 (16–21 June, 1990), pp. 64– 69. doi: 10.1109/ICPR.1990.119331

Manocha, D. (2005) General-purpose computations using graphics processors. Computer, 38 (8), 85–88. doi: 10.1109/MC.2005.261

Marr, D. and Hildreth, E. (1980) Theory of edge detection. Proceedings of the Royal Society of London, Series B, Biological Sciences, 207 (1167), 187–217. doi: 10.1098/rspb.1980.0020

Martin, G. and Smith, G. (2009) High-level synthesis: past, present, and future. IEEE Design & Test of Computers, 26 (4), 18–25. doi: 10.1109/MDT.2009.83

Martinez, J. and Altamirano, L. (2006) FPGA-based pipeline architecture to transform Cartesian images into foveal images by using a new foveation approach. IEEE International Conference on Reconfigurable Computing and FPGA's, San Luis Potosi, Mexico (20–22 September, 2006), pp. 227– 236. doi: 10.1109/RECONF.2006.307774

Martinez-Peiro, M., Boemo, E.I. and Wanhammar, L. (2002) Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 49 (3), 196–203. doi: 10.1109/TCSII.2002.1013866

Maruyama, T. (2004) Real-time computation of the generalized Hough transform, in 14th International Conference on Field Programmable Logic and Application, Antwerp, Belgium (29 August–1 September, 2004), Lecture Notes in Computer Science, vol. LNCS 3203, Springer, pp. 980–985. doi: 10.1007/b99787

Masrani, D.K. and MacLean, W.J. (2006) A real-time large disparity range stereo-system using FPGAs, in 7th Asian Conference on Computer Vision (ACCV 2006), Hyderabad, India (13–16 January, 2006), Lecture Notes in Computer Science, vol. LNCS 3852, Springer, pp. 42–51. doi: 10.1007/11612704_5

MathStar (2007) ArrixTM Family FPOATM Architecture Guide, vol. V1.02., MathStar Incorporated.

MathWorks (2010) Simulink HDL Coder 2 User's Guide. The MathWorks Inc.

Maurer, C.R., Qi, R. and Raghavan, V. (2003) A linear time algorithm for computing exact Euclidean distance transforms of binary images in arbitrary dimensions. IEEE Transactions on Pattern Analysis and Machine Intelligence, 25 (2), 265–270. doi: 10.1109/TPAMI.2003.1177156

Mayasandra, K., Salehi, S., Wang, W. and Ladak, H.M. (2005) A distributed arithmetic hardware architecture for real-time Hough-transform-based segmentation. Canadian Journal of Electrical and Computer Engineering, 30 (4), 201–205. doi: 10.1109/CJECE.2005.1541752

McCollum, A.J., Bowman, C.C., Daniels, P.A. and Batchelor, B.G. (1988) A histogram modification unit for real-time image enhancement. Computer Vision, Graphics and Image Processing, 42 (3), 387–398. doi: 10.1016/S0734-189X(88)80047-1

McDonnell, M.J. (1981) Box filtering techniques. Computer Graphics and Image Processing, 17 (1), 65–70. doi: 10.1016/S0146-664X(81)80009-3

McFarlane, M.D. (1972) Digital pictures fifty years ago. Proceedings of the IEEE, 60 (7), 768–770.

McIvor, A., Zang, Q. and Klette, R. (2001) The background subtraction problem for video surveillance systems, in International Workshop on Robot Vision (RobVis 2001), Auckland, New Zealand (16–18 February, 2001), Lecture Notes in Computer Science, vol. LNCS 1998, Springer, pp. 176–183. doi: 10.1007/3-540-44690-7_22

McLaughlin, J. (2000) The development of a Java image processing framework. Master of Technology Thesis, Institute of Information Sciences and Technology, Massey University: Palmerston North, New Zealand.

Mencer, O. (2006) ASC: a stream compiler for computing with FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25 (9), 1603–1617. doi: 10.1109/TCAD.2005.857377

Mencer, O. and Luk, W. (2004) Parameterized high throughput function evaluation for FPGAs. Journal of VLSI Signal Processing, 36 (1), 17–25. doi: 10.1023/B:VLSI.0000008067.31043.35

Mencer, O., Pearce, D.J., Howes, L.W. and Luk, W. (2003) Design space exploration with A Stream Compiler. 2003 IEEE International Conference on Field-Programmable Technology (FPT 2003), Tokyo, Japan (15–17 December, 2003), pp. 270– 277. doi: 10.1109/FPT.2003.1275757

Mentor (2010a) DK User Manual, Vol. Release v5.3_2., Mentor Graphics Corporation.

Mentor (2010b) Handel-C Language Reference Manual, Vol. Release v5.3_2., Mentor Graphics Corporation.

Mentor (2010c) PixelStreams User Manual, Vol. Release v5.3_2., Mentor Graphics Corporation.

Mercer, K., Bailey, D.G., Plaw, C., Ball, R. and Barraclough, H. (2002) Intelligent actuators for a high speed grading system. Ninth Electronics New Zealand Conference (ENZCon'02), Dunedin, New Zealand (14–15 November, 2002), pp. 61– 65.

Mesquita, D., Moraes, F., Palma, J., Möller, L. and Calazans, N. (2003) Remote and partial reconfiguration of FPGAs: tools and trends. International Parallel and Distributed Processing Symposium, Nice, France (22–26 April, 2003), p. 8. doi: 10.1109/IPDPS.2003.1213326

Micron (2007) Micron NAND flash controller via Xilinx Spartan-3 FPGA, Vol. TN-29-06 Revision B., Micron Technologies Inc.

Micron (2010) NAND Flash 101: an introduction to NAND flash and how to design it into your next product, Vol. TN-29-19 Revision B., Micron Technology, Inc.

Mignolet, J.Y., Nollet, V., Coene, P., Verkest, D., Vernalde, S. and Lauwereins, R. (2003) Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip. Design, Automation and Test in Europe (DATE'03), Munich, Germany (3–7 March, 2003), pp. 986– 991. doi: 10.1109/DATE.2003.10020

Millane, R.P., Alzaidi, S. and Hsiao, W.H. (2003) Scaling and power spectra of natural images. Image and Vision Computing New Zealand (IVCNZ'03), Palmerston North, New Zealand (26–28 November, 2003), pp. 148– 153.

Miller-Karlow, D.L. and Golin, E.J. (1992) vVHDL: a visual hardware description language. 1992 IEEE Workshop on Visual Languages, Seattle, Washington, USA (15–18 September, 1992), pp. 133– 139. doi: 10.1109/WVL.1992.275773

Mitra, S.K. (1998) Digital signal processing: a computer-based approach, McGraw-Hill, Singapore.

Miyamori, T. and Olukotun, U. (1998) A quantitative analysis of reconfigurable coprocessors for multimedia applications. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, USA (15–17 April, 1998), pp. 2– 11. doi: 10.1109/FPGA.1998.707876

Mohl, S. (2006) The Mitrion-C programming language, Vol. 1.3.0-001., Mitrionics.

Morris, J., Jawed, K., Gimel'farb, G. and Khan, T. (2009) Breaking the ‘ton’: achieving 1% depth accuracy from stereo in real time. 24th International Conference Image and Vision Computing New Zealand (IVCNZ '09), Wellington, New Zealand (23–25 November, 2009), pp. 142– 147. doi: 10.1109/IVCNZ.2009.5378423

Mosqueron, R., Dubois, J. and Paindavoine, M. (2007) High-speed smart camera with high resolution. EURASIP Journal on Embedded Systems, 2007, no. Article ID 24163. doi: 10.1155/2007/24163

Muller, J.M. (1985) Discrete basis and computation of elementary functions. IEEE Transactions on Computers, C-34 (9), 857–862. doi: 10.1109/TC.1985.1676643

Nagata, N. and Maruyama, T. (2004) Real-time detection of line segments using the line Hough transform. IEEE International Conference on Field-Programmable Technology, Brisbane, Australia (6–8 December, 2004), pp. 89– 96. doi: 10.1109/FPT.2004.1393255

Nagayama, S., Sasao, T. and Butler, J.T. (2008) Numerical function generators using bilinear interpolation. International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany (8–10 September, 2008), pp. 463– 466. doi: 10.1109/FPL.2008.4629984

Najjar, W.A., Böhm, W., Draper, B.A., Hammes, J., Rinker, R., Beveridge, J.R., Chawathe, M. and Ross, C. (2003) High-level language abstraction for reconfigurable computing. IEEE Computer, 36 (8), 63–69. doi: 10.1109/MC.2003.1220583

Nakagawa, Y. and Rosenfeld, A. (1978) A note on the use of local MIN and MAX operations in digital picture processing. IEEE Transactions on Systems, Man and Cybernetics, 8 (8), 632–635. doi: 10.1109/TSMC.1978.4310040

Narendra, P.M. (1981) A separable median filter for image noise smoothing. IEEE Transactions on Pattern Analysis and Machine Intelligence, 3 (1), 20–29. doi: 10.1109/TPAMI.1981.4767047

Nash, J.G. (2005) Systolic architecture for computing the discrete Fourier transform on FPGAs. 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), Napa, California, USA (18–20 April, 2005), pp. 305– 306. doi: 10.1109/FCCM.2005.60

Nassi, I. and Shneiderman, B. (1973) Flowchart techniques for structured programming. ACM SIGPLAN Notices, 8 (8), 12–26. doi: 10.1145/953349.953350

National Instruments (2005) Creating Custom Hardware with LabVIEW: NI LabVIEW FPGA Module, National Instruments.

Nayak, A., Haldar, M., Choudhary, A. and Banerjee, P. (2001) Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs. Design, Automation and Test in Europe, Munich, Germany (13–16 April, 2001), pp. 722– 728. doi: 10.1109/DATE.2001.915108

NEC (2009) Gate Arrays and Embedded Arrays, vol. A18258EJ7V0PF, NEC Electronics Corporation.

Ngan, P.M. (1992) The development of a visual language for image processing applications. PhD Thesis, Computer Science, Massey University: Palmerston North, New Zealand.

Ngo, H.T. and Asari, V.K. (2005) A pipelined architecture for real-time correction of barrel distortion in wide-angle camera images. IEEE Transactions on Circuits and Systems for Video Technology, 15 (3), 436–444. doi: 10.1109/TCSVT.2004.842609

Nicklin, S.P., Fisher, R.D. and Middleton, R.H. (2007) Rolling shutter image compensation, in RoboCup 2006: Robot Soccer World Cup X, Lecture Notes in Artificial Intelligence, vol. LNAI 4434, Springer, pp. 402–409. doi: 10.1007/978-3-540-74024-7_39

Nicol, C.J. (1995) A systolic approach for real time connected component labeling. Computer Vision and Image Understanding, 61 (1), 17–31. doi: 10.1006/cviu.1995.1002

Nielsen, A.M. and Muller, J.M. (1996) On-line algorithms for computing exponentials and logarithms, in Second International Euro-Par Conference, Lyon, France (26–29 August, 1996), Lecture Notes in Computer Science, vol. LNCS 1124, Springer, pp. 165–174. doi: 10.1007/BFb0024699

Nilsson, M., Dahl, M. and Claesson, I. (2005a) Gray-scale image enhancement using the SMQT. IEEE International Conference on Image Processing (ICIP '05), Genoa, Italy, vol. 1 (11–14 September, 2005), pp. 933– 936. doi: 10.1109/ICIP.2005.1529905

Nilsson, M., Dahl, M. and Claesson, I. (2005b) The successive mean quantization transform. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP '05), Philadelphia, Pennsylvania, USA, vol. 4 (18–23 March, 2005), pp. 429– 432. doi: 10.1109/ICASSP.2005.1416037

Nilsson, M., Sattar, F., Chng, H.K. and Claesson, I. (2005c) Automatic enhancement and subjective evaluation of dental X-ray images using the SMQT. 5th International Conference on Information, Communications and Signal Processing, Bangkok, Thailand (6–9 December, 2005), pp. 1448– 1451. doi: 10.1109/ICICS.2005.1689298

Noble, J.A. (1988) Finding corners. Image and Vision Computing, 6 (2), 121–128. doi: 10.1016/0262-8856(88)90007-8

Nodes, T.A. and Gallagher, N.C. (1982) Median filters: some modifications and their properties. IEEE Transactions on Acoustics, Speech and Signal Processing, 30 (5), 739–746. doi: 10.1109/TASSP.1982.1163951

Nuño-Maganda, M. and Arias-Estrada, M. (2005) Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling. International Conference on Reconfigurable Computing and FPGAs, Puebla City, Mexico (28–30 September, 2005), p. 8. doi: 10.1109/ReConFig.2005.34

NVIDIA (2006) Technical Brief – NVIDIA GeForce 8800 GPU Architecture Overview, NVIDIA Corporation.

NXP (2007) I2C-Bus Specification and User Manual, Vol. UM10204 Rev. 03., NXP Semiconductors.

Offen, R.J. (1985) VLSI Image Processing, Collins, London.

Oh, S. and Kim, G. (2008) An architecture for on-the-fly correction of radial distortion using FPGA, in Real-Time Image Processing 2008, San Jose, California, USA (28–29 January, 2008), vol. 6811, SPIE, pp. 68110X-1-9. doi: 10.1117/12.767125

Ong, S.W., Kerkiz, N., Srijanto, B., Langston, M.C.T., Newport, D. and Bouldin, D. (2001) Automatic mapping of multiple applications to multiple adaptive computing systems. 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '01), Rohnert Park, California, USA (30 April–2 May, 2001), pp. 10– 20. doi: 10.1109/FCCM.2001.15

Oraintara, S., Chen, Y.J. and Nguyen, T.Q. (2002) Integer fast Fourier transform. IEEE Transactions on Signal Processing, 50 (3), 607–618. doi: 10.1109/78.984749

Orwell, J., Remagnino, P. and Jones, G.A. (1999) Multi-camera colour tracking. Second IEEE Workshop on Visual Surveillance, Fort Collins, Colorado, USA (26 June, 1999), pp. 14– 21. doi: 10.1109/VS.1999.780264

Ostresh, L.M. (1978) On the convergence of a class of iterative methods for solving the Weber location problem. Operations Research, 26 (4), 597–609. doi: 10.1287/opre.26.4.597

Otsu, N. (1979) A threshold selection method from gray-level histograms. IEEE Transactions on Systems, Man and Cybernetics, 9 (1), 62–66. doi: 10.1109/TSMC.1979.4310076

Ovod, V.I., Baxter, C.R., Massie, M.A. and McCarley, P.L. (2005) Advanced image processing package for FPGA-based re-programmable miniature electronics, in Infrared Technology and Applications XXXI, Orlando, Florida, USA (28 March–1 April, 2005), vol. 5783, SPIE, pp. 304–315. doi: 10.1117/12.603019

Page, I. (1996) Closing the gap between hardware and software: hardware-software cosynthesis at Oxford. IEE Colloquium on Hardware-Software Cosynthesis for Reconfigurable Systems (Digest No: 1996/036), Bristol, UK (22 February, 1996), pp. 2/1–– 12 doi: 10.1049/ic:19960221

Page, I. and Luk, W. (1991) Compiling Occam into field-programmable gate arrays. Field Programmable Logic and Applications, Oxford, UK (4–6 September, 1991), pp. 271– 283.

Pajares, G. and de la Cruz, J.M. (2004) A wavelet-based image fusion tutorial. Pattern Recognition, 37 (9), 1855–1872. doi: 10.1016/j.patcog.2004.03.010

Parhami, B. (2000) Computer Arithmetic: Algorithms and Hardware Designs, Oxford University Press, New York.

Parhi, K.K. (1991) A systematic approach for design of digit-serial signal processing architectures. IEEE Transactions on Circuits and Systems, 38 (4), 358–375. doi: 10.1109/31.75394

Park, J.W. (1986) An efficient memory system for image processing. IEEE Transactions on Computers, 35 (7), 669–674. doi: 10.1109/TC.1986.1676813

Parulski, K.A. (1985) Color filters and processing alternatives for one-chip cameras. IEEE Transactions on Electron Devices, 32 (8), 1381–1389. doi: 10.1109/T-ED.1985.22133

Pavan, P., Bez, R., Olivo, P. and Zanoni, E. (1997) Flash memory cells-an overview. Proceedings of the IEEE, 85 (8), 1248–1271. doi: 10.1109/5.622505

Peleg, A., Wilkie, S. and Weiser, U. (1997) Intel MMX for multimedia PCs. Communications of the ACM, 40 (1), 24–38. doi: 10.1145/242857.242865

Pell, O. and Luk, W. (2005) Quartz: a framework for correct and efficient reconfigurable design. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2005), Puebla City, Mexico (28–30 September, 2005), p. 8. doi: 10.1109/RECONFIG.2005.32

Pellerin, D. and Thibault, S. (2005) Practical FPGA programming in C, Parson Education, Upper Saddle River, New Jersey, USA.

Pellerin, D., Edvenson, G., Shenoy, K. and Isaacs, D. (2005) Accelerating PowerPC software applications. Xcell Journal (55), 82–87.

Peterson, W.W. (1957) Addressing for random-access storage. IBM Journal of Research and Development, 1 (2), 130–146.

Pettersson, N. and Petersson, L. (2005) Online stereo calibration using FPGAs. IEEE Intelligent Vehicles Symposium, Las Vegas, Nevada, USA (6–8 June, 2005), pp. 55– 60. doi: 10.1109/IVS.2005.1505077

Piccardi, M. (2004) Background subtraction techniques: a review. IEEE International Conference on Systems, Man and Cybernetics, The Hague, The Netherlands, vol. 4 (10–13 October, 2004), pp. 3099– 3104. doi: 10.1109/ICSMC.2004.1400815

Pizer, S.M., Amburn, E.P., Austin, J.D., Cromartie, R., Geselowitz, A., Greer, T., Romeny, B.t.H., Zimmerman, J.B. and Zuiderveld, K. (1987) Adaptive histogram equalization and its variations. Computer Vision, Graphics, and Image Processing, 39 (3), 355–368. doi: 10.1016/S0734-189X(87)80186-X

Porikli, F. (2008) Reshuffling: a fast algorithm for filtering with arbitrary kernels, in Real-Time Image Processing 2008, San Jose, California, USA (28–29 January, 2008), vol. 6811, SPIE, pp. 68110M-1-10. doi: 10.1117/12.772114

Potkonjak, M., Srivastava, M.B. and Chandrakasan, A.P. (1996) Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15 (2), 151–165. doi: 10.1109/43.486662

Pratt, W.K. (1978) Digital Image Processing, John Wiley & Sons, Inc., New York.

Press, W.H., Flannery, B.P., Teukolsky, S.A. and Vetterling, W.T. (1993) Numerical Recipes in C: The Art Of Scientific Computing, Cambridge University Press.

Preston, K., Duff, M.J.B., Levialdi, S., Norgren, P.E. and Toriwaki, J. (1979) Basics of cellular logic with some applications in medical image processing. Proceedings of the IEEE, 67 (5), 826–856.

Prewitt, J.M.S. and Mendelsohn, M.L. (1966) The analysis of cell images. Annals of the New York Academy of Sciences, 128 (3), 1035–1053. doi: 10.1111/j.1749-6632.1965.tb11715.x

Proffitt, D. and Rosen, D. (1979) Metrication errors and coding efficiency of chain encoding schemes for the representation of lines and edges. Computer Graphics and Image Processing, 10 (4), 318–332. doi: 10.1016/S0146-664X(79)80041-6

Punchihewa, A., Bailey, D.G. and Hodgson, R.M. (2005) Colour reproduction performance of JPEG and JPEG2000 codecs. 8th International Symposium on DSP and Communication Systems, (DSPCS'2005) and 4th Workshop on the Internet, Telecommunications and Signal Processing, (WITSP'2005), Noosa Heads, Australia (19–21 December, 2005), pp. 312– 317.

QuickLogic (2007a) Eclipse II Family Data Sheet, Vol. Rev R., QuickLogic Corporation.

QuickLogic (2007b) Eclipse Family Data Sheet, Vol. Rev F., QuickLogic Corporation.

Rachakonda, R.V., Athanas, P.M. and Abbott, A.L. (1995) High-speed region detection and labeling using an FPGA-based custom computing platform, in Field Programmable Logic and Applications, Oxford, UK (29 August–1 September, 1995), Lecture Notes in Computer Science, vol. LNCS 975, Springer, pp. 86–93. doi: 10.1007/3-540-60294-1_101

Ragnemalm, I. (1993) The Euclidean distance transformation in arbitrary dimensions. Pattern Recognition Letters, 14 (11), 883–888. doi: 10.1016/0167-8655(93)90152-4

Rajagopalan, K. and Sutton, P. (2001) A flexible multiplication unit for an FPGA logic block. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australia, vol. 4 (6–9 May, 2001), pp. 546– 549. doi: 10.1109/ISCAS.2001.922295

Rambabu, C. and Chakrabarti, I. (2007) An efficient immersion-based watershed transform method and its prototype architecture. Journal of Systems Architecture, 53 (4), 210–226. doi: 10.1016/j.sysarc.2005.12.005

Rambabu, C., Chakrabarti, L. and Mahanta, A. (2002) An efficient architecture for an improved watershed algorithm and its FPGA implementation. IEEE International Conference on Field-Programmable Technology (FPT), Hong Kong (16–18 December, 2002), pp. 370– 373. doi: 10.1109/FPT.2002.1188713

Randen, T. and Husoy, J.H. (1999) Filtering for texture classification: a comparative study. IEEE Transactions on Pattern Analysis and Machine Intelligence, 21 (4), 291–310. doi: 10.1109/34.761261

Randhawa, S. and Li, J.S. (2005) CFA demosaicking with improved colour edge preservation. IEEE Region 10 Conference (IEEE Tencon'05), Melbourne, Australia (21–24 November, 2005). doi: 10.1109/TENCON.2005.301070

Ranganathan, N., Mehrotra, R. and Subramanian, S. (1995) A high speed systolic architecture for labeling connected components in an image. IEEE Transactions on Systems, Man and Cybernetics, 25 (3), 415–423. doi: 10.1109/21.364855

Ratha, N.K. and Jain, A.K. (1999) Computer vision algorithms on reconfigurable logic arrays. IEEE Transactions on Parallel and Distributed Systems, 10 (1), 29–43. doi: 10.1109/71.744833

Reddy, B.S. and Chatterji, B.N. (1996) An FFT-based technique for translation, rotation, and scale-invariant image registration. IEEE Transactions on Image Processing, 5 (8), 1266–1271. doi: 10.1109/83.506761

Reulke, R., Meysel, F. and Bauer, S. (2008) Situation analysis and atypical event detection with multiple cameras and multi-object tracking. Robot Vision, Auckland, New Zealand (18–20 February, 2008), Lecture Notes in Computer Science, vol. LNCS 4931, Springer, pp. 234–247. doi: 10.1007/978-3-540-78157-8_18

Reznik, Y.A., Hinds, A.T., Zhang, C., Yu, L. and Ni, Z. (2007) Efficient fixed-point approximations of the 8×8 inverse discrete cosine transform. Applications of Digital Image Processing XXX, San Diego, California, USA, vol. 6696, SPIE, p. 669617. doi: 10.1117/12.740228

Ridler, T.W. and Calvard, S. (1978) Picture thresholding using an iterative selection method. IEEE Transactions on Systems, Man and Cybernetics, 8 (8), 630–632. doi: 10.1109/TSMC.1978.4310039

Rissanen, J.J. (1976) Generalized Kraft inequality and arithmetic coding. IBM Journal of Research and Development, 20 (3), 198–203. doi: 10.1147/rd.203.0198

Roberts, D. (1996) Internet Protocols Handbook, Coriolis Group Books.

Robertson, J.E. (1958) A new class of digital division methods. IRE Transactions on Electronic Computers, EC-7 (3), 218–222. doi: 10.1109/TEC.1958.5222579

Rosenfeld, A. and de la Torre, P. (1983) Histogram concavity analysis as an aid in threshold selection. IEEE Transactions on Systems, Man and Cybernetics, 13 (3), 231–235.

Rosenfeld, A. and Pfaltz, J. (1966) Sequential operations in digital picture processing. Journal of the Association for Computing Machinery, 13 (4), 471–494. doi: 10.1145/321356.321357

Russ, J.C. (2002) The Image Processing Handbook, 4th edn, CRC Press, Boca Raton, Florida.

Rutenbar, R.A., Baron, M., Daniel, T., Jayaraman, R., Or-Bach, Z., Rose, J. and Sechen, C. (2001) (When) will FPGAs kill ASICs? 38th annual Design Automation Conference, Las Vegas, Nevada, USA (18–22 June, 2001), pp. 321– 322. doi: 10.1145/378239.378499

Saeed, A., Elbably, M., Abdelfadeel, G. and Eladawy, M.I. (2009) Efficient FPGA implementation of FFT/IFFT processor. International Journal of Circuits, Systems and Signal Processing, 3 (3), 103–110.

Sam, H. and Gupta, A. (1990) A generalized multibit recoding of two's complement binary numbers and its proof with application in multiplier implementations. IEEE Transactions on Computers, 39 (8), 1006–1015. doi: 10.1109/12.57039

Sanderson, C. (2004) Simplify FPGA application design with DIMEtalk. Xcell Journal, 51, 104–107.

Sansaloni, T., Perez-Pascual, A. and Valls, J. (2003) Area-efficient FPGA-based FFT processor. Electronics Letters, 39 (19), 1369–1370. doi: 10.1049/el:20030892

Sarwar, A. (1997) CMOS power consumption and Cpd calculation, Application Note: SCAA035B. Texas Instruments.

Sawchuk, A.A. (1977) Real-time correction of intensity nonlinearities in imaging systems. IEEE Transactions on Computers, 26 (1), 34–39. doi: 10.1109/TC.1977.5009271

Schaffer, G. (1984) Machine vision: a sense for computer integrated manufacturing. American Machinist, 128 (6), 101–129.

Schoonees, J.A. and Palmer, T. (2009) Camera shading calibration using a spatially modulated field. Image and Vision Computing New Zealand (IVCNZ 2009), Wellington, New Zealand (23–25 November, 2009), pp. 191– 196. doi: 10.1109/IVCNZ.2009.5378412

Schulte, M.J. and Stine, J.E. (1997) Symmetric bipartite tables for accurate function approximation. 13th IEEE Symposium on Computer Arithmetic, Asilomar, California, USA (6–9 July, 1997), pp. 175– 183. doi: 10.1109/ARITH.1997.614893

Schwarz, E.M. and Flynn, M.J. (1993) Hardware starting approximation for the square root operation. 11th Symposium on Computer Arithmetic, Windsor, Ontario, Canada (29 June–2 July, 1993), pp. 103– 111. doi: 10.1109/ARITH.1993.378103

Sedcole, P. (2006) Reconfigurable platform-based design in FPGAs for video image processing. PhD Thesis, Department of Electrical and Electronic Engineering, Imperial College, London, UK.

Sedcole, N.P., Cheung, P.Y.K., Constantinides, G.A. and Luk, W. (2003) A reconfigurable platform for real-time embedded video image processing. International Conference on Field Programmable Logic and Applications (FPL 2003), Lisbon, Portugal (1–3 September, 2003), Lecture Notes in Computer Science, vol. LNCS 2778, Springer, pp. 606–615. doi: 10.1007/b12007

Sedcole, P., Cheung, P.Y.K., Constantinides, G.A. and Luk, W. (2007) Run-time integration of reconfigurable video processing systems. IEEE Transactions on VLSI Systems, 15 (9), 1003–1016. doi: 10.1109/TVLSI.2007.902203

Sen, M., Corretjer, I., Haim, F., Saha, S., Schlessman, J., Lv, T., Bhattacharyya, S.S. and Wolf, W. (2007) Dataflow-based mapping of computer vision algorithms onto FPGAs. EURASIP Journal on Embedded Systems, 2007, no. Article ID 49236. doi: 10.1155/2007/49236

Sen Gupta, G., Win, T.A., Messom, C., Demidenko, S. and Mukhopadhyay, S. (2003) Defect analysis of grit-blasted or spray painted surface using vision sensing techniques. Image and Vision Computing New Zealand (IVCNZ'03), Palmerston North, New Zealand (26–28 November, 2003), pp. 18– 23.

Sen Gupta, G., Bailey, D. and Messom, C. (2004) A new colour-space for efficient and robust segmentation. Image and Vision Computing New Zealand (IVCNZ'04), Akaroa, New Zealand (21–23 November, 2004), pp. 315– 320.

Sen Gupta, G. and Bailey, D. (2008) Discrete YUV look-up tables for fast colour segmentation for robotic applications. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2008), Niagara Falls, Canada (4–7 May, 2008), pp. 963– 968. doi: 10.1109/CCECE.2008.4564679

Sendur, L. and Selesnick, I.W. (2002) Bivariate shrinkage functions for wavelet-based denoising exploiting interscale dependency. IEEE Transactions on Signal Processing, 50 (11), 2744–2756. doi: 10.1109/TSP.2002.804091

Sensor to Image (2009a) GigE Receiver Reference Design Description, vol. X-1.0.2, Sensor to Image GmbH.

Sensor to Image (2009b) GigE Vision Reference Design, vol. A-0.2.3, Sensor to Image GmbH.

Sensor to Image (2009c) GigE Vision Reference Design Description, vol. X-1.0.4, Sensor to Image GmbH.

Serra, J. (1986) Introduction to mathematical morphology. Computer Vision, Graphics and Image Processing, 35 (3), 283–305. doi: 10.1016/0734-189X(86)90002-2

Sezgin, M. and Sankur, B. (2004) Survey over image thresholding techniques and quantitative performance evaluation. Journal of Electronic Imaging, 13 (1), 146–165. doi: 10.1117/1.1631315

Shamos, M.I. (1978) Robust picture processing operators and their implementation as circuits. ARPA Image Understanding Workshop, Pittsburgh, Pennsylvania, USA (November, 1978), pp. 127– 129.

Shih, F.Y. and Wong, W.T. (1992) A new single-pass algorithm for extracting the mid-crack codes of multiple regions. Journal of Visual Communication and Image Representation, 3 (3), 217–224. doi: 10.1016/1047-3203(92)90018-O

Shilton, A. and Bailey, D. (2006) Drogue tracking by image processing for study of laboratory scale pond hydraulics. Journal of Flow Measurement and Instrumentation, 17 (1), 69–74. doi: 10.1016/j.flowmeasinst.2005.04.002

Sidahao, N., Constantinides, G.A. and Cheung, P.Y.K. (2003) Architectures for function evaluation on FPGAs. International Symposium on Circuits and Systems (ISCAS '03), Bangkok, Thailand, vol. 2 (25–28 May, 2003), pp. 804– 807. doi: 10.1109/ISCAS.2003.1206096

SiliconBlue (2009) iCE65 Ultra Low-Power mobileFPGA Family, vol. v2.0.1, SiliconBlue Technologies Corporation.

Simmler, H., Levinson, L. and Männer, R. (2000) Multitasking on FPGA coprocessors. 10th International Conference on Field Programmable Logic and Applications, Villach, Austria (27–30 August, 2000), Lecture Notes in Computer Science, vol. LNCS 1896, Springer, pp. 121–130. doi: 10.1007/3-540-44614-1_13

Simpson, P. (2010) FPGA Design: Best Practices for Team-Based Design, Springer. doi: 10.1007/978-1-4419-6339-0_1

Singh, S., Rose, J., Chow, P. and Lewis, D. (1992) The effect of logic block architecture on FPGA performance. IEEE Journal of Solid-State Circuits, 27 (3), 281–287. doi: 10.1109/4.121549

Skliarova, I. and Sklyarov, V. (2009) Recursion in reconfigurable computing: A survey of implementation approaches. International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic (31 August–2 September, 2009), pp. 224– 229. doi: 10.1109/FPL.2009.5272304

Sklyarov, V. (2002) Reconfigurable models of finite state machines and their implementation in FPGAs. Journal of Systems Architecture, 47 (14–15), 1043–1064. doi: 10.1016/S1383-7621(02)00067-X

Sklyarov, V. and Skliarova, I. (2008) Design and implementation of parallel hierarchical finite state machines. Second International Conference on Communications and Electronics (ICCE 2008), Hoi an, Vietnam (4–6 June, 2008), pp. 33– 38. doi: 10.1109/CCE.2008.4578929

So, H.K.H. (2007) BORPH: An operating system for FPGA-based reconfigurable computers. PhD Thesis, Electrical Engineering and Computer Sciences, University of California, Berkley.

Solomon, C. and Breckon, T. (2011) Fundamentals of Digital Image Processing: A practical approach with examples in Matlab. Wiley-Blackwell.

Specker, W.H. (1965) A class of algorithms for ln(x), exp(x), sin(x), cos(x), tan⁻¹(x) and cot⁻¹(x). IEEE Transactions on Electronic Computers, EC-14 (1), 85–86. doi: 10.1109/PGEC.1965.264066

Stauffer, C. and Grimson, W.E.L. (1999) Adaptive background mixture models for real-time tracking. IEEE Computer Society Conference on Computer Vision and Pattern Recognition, Fort Collins, Colorado, USA, vol. 2 (23–25 June, 1999), pp. 246– 252. doi: 10.1109/CVPR.1999.784637

Stefanov, T., Zissulescu, C., Turjan, A., Kienhuis, B. and Deprette, E. (2004) System design using Khan process networks: the Compaan/Laura approach. Design, Automation and Test in Europe Conference and Exhibition, Paris, France, vol. 1 (16–20 February, 2004), pp. 340– 345. doi: 10.1109/DATE.2004.1268870

Steiger, C., Walder, H. and Platzner, M. (2004) Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. IEEE Transactions on Computers, 53 (11), 1393–1407. doi: 10.1109/TC.2004.99

Stine, J.E. and Schulte, M.J. (1999) The symmetric table addition method for accurate function approximation. Journal of VLSI Signal Processing, 21 (2), 167–177. doi: 10.1023/A:1008004523235

Stokes, M., Anderson, M., Chandrasekar, S. and Motta, R. (1996) A standard default color space for the internet – sRGB. Available from http://www.w3.org/Graphics/Color/sRGB [cited 12 January, 2010].

Stone, H., Orchard, M. and Chang, E.C. (1999) Subpixel registration of images. Thirty-Third Asilomar Conference on Signals, Systems, and Computers, Monterey, California, USA, vol. 2 (24–27 October, 1999), pp. 1446– 1452. doi: 10.1109/ACSSC.1999.831945

Stone, H.S., Orchard, M.T., Chang, E.C. and Martucci, S.A. (2001) A fast direct Fourier-based algorithm for subpixel registration of images. IEEE Transactions on Geoscience and Remote Sensing, 39 (10), 2235–2243. doi: 10.1109/36.957286

Stowers, J., Hayes, M. and Bainbridge-Smith, A. (2010) Phase correlation using shear average for image registration. Image and Vision Computing New Zealand, Queenstown, New Zealand (8–9 November, 2010).

Strickland, R.N. and Hahn, H.I. (1997) Wavelet transform methods for object detection and recovery. IEEE Transactions on Image Processing, 6 (5), 724–735. doi: 10.1109/83.568929

Suciu, R.E. and Reeves, A.P. (1982) A comparison of differential and moment based edge detectors. IEEE Computer Society Conference on Pattern Recognition and Image Processing, Las Vegas, Nevada, USA (14–17 June, 1982), pp. 97– 102.

Sudha, N. and Mohan, A.R. (2008) Design of a hardware accelerator for path planning on the Euclidean distance transform. Journal of Systems Architecture, 54 (1–2), pp. 253–264. doi: 10.1016/j.sysarc.2007.06.003

Sukhsawas, S. and Benkrid, K. (2004) A high-level implementation of a high performance pipeline FFT on Virtex-E FPGAs. IEEE Computer society Annual Symposium on VLSI, Lafayette, Louisiana, USA (19–20 February, 2004), pp. 229– 232. doi: 10.1109/ISVLSI.2004.1339538

Sun, S.H. and Lee, S.J. (2003) A JPEG chip for image compression and decompression. The Journal of VLSI Signal Processing, 35 (1), 43–60. doi: 10.1023/A:1023383820503

Swain, M.J. and Ballard, D.H. (1991) Colour indexing. International Journal of Computer Vision, 7 (1), 11–32. doi: 10.1007/BF00130487

Swan, S. (2006) SystemC transaction level models and RTL verification. 43rd ACM/IEEE Design Automation Conference, San Francisco, California, USA (24–28 July, 2006), pp. 90– 92. doi: 10.1109/DAC.2006.229170

Swenson, R.L. and Dimond, K.R. (1999) A hardware FPGA implementation of a 2D median filter using a novel rank adjustment technique. Seventh International Conference on Image Processing And Its Applications, Manchester, UK, vol. Conf Publ 465 (13–15 July, 1999), pp. 103– 106. doi: 10.1049/cp:19990290

Tabula (2009) Abax™ Family Overview. Tabula Inc.

Tabula (2010a) Abax™ Product Family Overview. Tabula Inc.

Tabula (2010b) Tabula SpaceTime™ architecture White paper. Tabula Inc.

Tagzout, S., Achour, K. and Djekoune, O. (2001) Hough transform algorithm for FPGA implementation. Signal Processing, 81 (6), 1295–1301. doi: 10.1016/S0165-1684(00)00248-6

Tahir, M.A., Bouridane, A., Kurugollu, F. and Amira, A. (2003a) An FPGA based coprocessor for calculating grey level co-occurrence matrix. IEEE International Symposium on Micro-NanoMechatronics and Human Science, Cairo, Egypt, vol. 2 (27–30 December, 2003), pp. 868– 871. doi: 10.1109/MWSCAS.2003.1562424

Tahir, M.A., Roula, M.A., Bouridane, A., Kurugollu, F. and Amira, A. (2003b) An FPGA based co-processor for GLCM texture features measurement. 10th IEEE International Conference on Electronics, Circuits and Systems, Sharjah, United Arab Emirates, vol. 3 (14–17 December, 2003), pp. 1006– 1009. doi: 10.1109/ICECS.2003.1301679

Tang, K., Astola, J. and Neuvo, Y. (1994) Multichannel edge enhancement in color image processing. IEEE Transactions on Circuits and Systems for Video Technology, 4 (5), 468–479. doi: 10.1109/76.322994

Tatas, K., Soudris, D.J., Siomos, D., Dasygenis, M. and Thanailakis, A. (2002) A novel division algorithm for parallel and sequential processing. 9th International Conference on Electronics, Circuits and Systems, Dubrovnik, Croatia, vol. 2 (15–18 September, 2002), pp. 553– 556. doi: 10.1109/ICECS.2002.1046225

Taubman, D. (2000) High performance scalable image compression with EBCOT. IEEE Transactions on Image Processing, 9 (7), 1158–1170. doi: 10.1109/83.847830

Therrien, C.W., Quatieri, T.F. and Dudgeon, D.E. (1986) Statistical model-based algorithms for image analysis. Proceedings of the IEEE 74 (4), 532– 551.

Thevenaz, P., Ruttimann, U.E. and Unser, M. (1998) A pyramid approach to subpixel registration based on intensity. IEEE Transactions on Image Processing, 7 (1), 27–41. doi: 10.1109/83.650848

Thomas, D.B. and Luk, W. (2005) High quality uniform random number generation through LUT optimised linear recurrences. IEEE International Conference on Field-Programmable Technology, Singapore (11–14 December, 2005), pp. 61– 68. doi: 10.1109/FPT.2005.1568526

Thomas, D.B. and Luk, W. (2009) Using FPGA resources for direct generation of multivariate Gaussian random numbers. International Conference on Field Programmable Technology (FPT'09), Sydney, Australia (9–11 December, 2009), pp. 344– 347. doi: 10.1109/FPT.2009.5377680

Tian, Q. and Huhns, M.N. (1986) Algorithms for sub-pixel registration. Computer Vision, Graphics and Image Processing, 35 (2), 220–233. doi: 10.1016/0734-189X(86)90028-9

Timmermann, D., Hahn, H. and Hosticka, B.J. (1992) Low latency time CORDIC algorithms. IEEE Transactions on Computers, 41 (8), 1010–1015. doi: 10.1109/12.156543

Tocher, K.D. (1958) Techniques of multiplication and division for automatic binary divider. Quarterly Journal of Mechanics and Applied Mathematics, 11 (3), 364–384. doi: 10.1093/qjmam/11.3.364

Todman, T.J., Constantinides, G.A., Wilton, S.J.E., Mencer, O., Luk, W. and Cheung, P.Y.K. (2005) Reconfigurable computing: architectures and design methods. IEE Proceedings Computers and Digital Techniques, 152 (2), 193– 207. doi: 10.1049/ip-cdt:20045086

Toledo, F., Martinez, J.J., Garrigos, J., Ferrandez, J. and Rodellar, V. (2006) Skin color detection for real time mobile applications. International Conference on Field Programmable Logic and Applications (FPL'06), Madrid, Spain (28–30 August, 2006), pp. 721– 724. doi: 10.1109/FPL.2006.311299

Tombs, J., Aguirre Echanove, M.A., Munoz, F., Baena, V., Torralba, A., Fernandez-Leon, A. and Tortosa, F. (2004) The implementation of an FPGA hardware debugger system with minimal system overhead. 14th International Conference on Field Programmable Logic and Application, Antwerp, Belgium (29 August–1 September, 2004), Lecture Notes in Computer Science, vol. LNCS 3203, Springer, pp. 1062–1066. doi: 10.1007/b99787

Tomczak, T. (2006) Residue arithmetic in FPGA matrices. International Conference on Dependability of Computer Systems, Szklarska Poreba, Poland (25–27 May, 2006), pp. 297– 305. doi: 10.1109/DEPCOS-RELCOMEX.2006.43

Torres-Huitzil, C. and Arias-Estrada, M. (2004) Real-time image processing with a compact FPGA-based systolic architecture. Real-Time Imaging, 10 (3), 177–187. doi: 10.1016/j.rti.2004.06.001

Traver, V.J. and Pla, F. (2003) The log-polar image representation in pattern recognition tasks. First Iberian Conference on Pattern Recognition and Image Analysis, Mallorca, Spain (4–6 June, 2003), pp. 1032– 1040. doi: 10.1007/b12122

Trein, J., Schwarzbacher, A.T., Hoppe, B., Noffz, K.H. and Trenschel, T. (2007) Development of a FPGA based real-time blob analysis circuit. Irish Signals and Systems Conference, Derry, UK (13–14 September, 2007), pp. 121– 126.

Trein, J., Schwarzbacher, A.T. and Hoppe, B. (2008) FPGA implementation of a single pass real-time blob analysis using run length encoding. in MPC-Workshop, Ravensburg-Weingarten, Germany (1 February, 2008), pp. 71– 77.

Trieu, D.B.K. and Maruyama, T. (2006) Implementation of a parallel and pipelined watershed algorithm on FPGA. International Conference on Field Programmable Logic and Applications (FPL'06), Madrid, Spain (28–30 August, 2006), pp. 561– 566. doi: 10.1109/FPL.2006.311267

Trieu, D.B.K. and Maruyama, T. (2007) A pipeline implementation of a watershed algorithm on FPGA. International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam, The Netherlands (27–29 August, 2007), pp. 714– 717. doi: 10.1109/FPL.2007.4380752

Trieu, D.B.K. and Maruyama, T. (2008) An implementation of a watershed algorithm based on connected components on FPGA. International Conference on Field Programmable Technology, Taipei, Taiwan (7–10 December, 2008), pp. 253- 256. doi: 10.1109/FPT.2008.4762391

Trummer, R.K.L. (2005) A high-performance data-dependent hardware integer divider. Masters Thesis, University of Salzburg, Salzburg, Austria.

Trussell, H.J. (1979) Comments on “Picture thresholding using an iterative selection method”. IEEE Transactions on Systems, Man and Cybernetics, 9 (5), 311–1311 doi: 10.1109/TSMC.1979.4310204

Tsai, R.Y. (1987) A versatile camera calibration technique for high-accuracy 3D machine vision metrology using off-the-shelf TV cameras and lenses. IEEE Journal of Robotics and Automation, 3 (4), 323–344. doi: 10.1109/JRA.1987.1087109

Tsai, R.Y. and Huang, T.S. (1984) Multiframe image restoration and registration, Advances in Computer Vision and Image Processing, vol. 1, JAI Press, pp. 317–339.

Tsoi, K.H., Leung, K.H. and Leong, P.H.W. (2007) High performance physical random number generator. IET Computers and Digital Techniques, 1 (4), 349–352. doi: 10.1049/iet-cdt:20050173

Turk, M.A. and Pentland, A.P. (1991) Face recognition using eigenfaces. IEEE Conference on Computer Vision and Pattern Recognition (CVPR'91), Maui, Hawaii, USA (3–6 June, 1991), pp. 586– 591. doi: 10.1109/CVPR.1991.139758

Uber, G.T. (1986) Illumination methods for machine vision. Optics, Illumination, and Image Sensing for Machine Vision, Cambridge, Massachusetts, USA (30–31 October, 1986), vol. 728, SPIE, pp. 93–102.

Unger, S.H. (1958) A computer oriented toward spatial problems. Proceedings of the IRE, 46 (10), 1744–1750. doi: 10.1109/JRPROC.1958.286755

Unsal, O.S. and Koren, I. (2003) System-level power-aware design techniques in real-time systems. Proceedings of the IEEE, 91 (7), 1055–1069. doi: 10.1109/JPROC.2003.814617

Unser, M. (2000) Sampling - 50 years after Shannon. Proceedings of the IEEE, 88 (4), 569–587. doi: 10.1109/5.843002

Unser, M., Aldroubi, A. and Eden, M. (1991) Fast B-spline transforms for continuous image representation and interpolation. IEEE Transactions on Pattern Analysis and Machine Intelligence, 13 (3), 277–285. doi: 10.1109/34.75515

Uzun, I.S. and Bouridane, A.A.A. (2003) FPGA implementations of fast Fourier transforms for real-time signal and image processing. IEEE International Conference on Field-Programmable Technology (FPT), Tokyo, Japan (15–17 December, 2003), pp. 102– 109. doi: 10.1109/FPT.2003.1275737

Uzun, I.S., Amira, A. and Bouridane, A. (2005) FPGA implementations of fast Fourier transforms for real-time signal and image processing. IEE Proceedings – Vision, Image and Signal Processing, 152 (3), 283–296. doi: 10.1049/ip-vis:20041114

Vanmeerbeeck, G., Schaumont, P., Vernalde, S., Engels, M. and Bolsens, I. (2001) Hardware/software partitioning of embedded system in OCAPI-xl. International Conference on Hardware Software Codesign, Copenhagen, Denmark (25–27 April, 2001), pp. 30– 35. doi: 10.1145/371636.371665

Velten, J. and Kummert, A. (2002) FPGA-based implementation of variable sized structuring elements for 2D binary morphological operations. IEEE International Workshop on Electronic Design, Test, and Applications (DELTA), Christchurch, New Zealand (29–31 January, 2002), pp. 309– 312. doi: 10.1109/DELTA.2002.994636

VESA (2003) Coordinated Video Timings Standard, Version 1.1., Video Electronics Standards Association.

VESA (2007) VESA and Industry Standards and Guidelines for Computer Display Monitor Timing (DMT), Version 1.0, Revision 11, Video Electronics Standards Association.

Vezhnevets, V., Sazonov, V. and Andreeva, A. (2003) A survey on pixel-based skin color detection techniques. Graphicon-2003, Moscow, pp. 85– 92.

Villalba, J., Hidalgo, J.A., Zapata, E.L., Antelo, E. and Bruguera, J.D. (1995) CORDIC architectures with parallel compensation of the scale factor. International Conference on Application Specific Array Processors, Strasbourg, France (24–26 July, 1995), pp. 258– 269. doi: 10.1109/ASAP.1995.522930

Villasenor, J., Jones, C. and Schoner, B. (1995) Video communications using rapidly reconfigurable hardware. IEEE Transactions on Circuits and Systems for Video Technology, 5 (6), 565–567. doi: 10.1109/76.475899

Villasenor, J., Schoner, B., Chia, K.N., Zapata, C., Kim, H.J., Jones, C., Lansing, S. and Mangione-Smith, B. (1996) Configurable computing solutions for automatic target recognition. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, USA (17–19 April, 1996), pp. 70– 79. doi: 10.1109/FPGA.1996.564749

Vincent, L. (1991) Exact Euclidean distance function by chain propagations. IEEE Computer Society Conference on Computer Vision and Pattern Recognition, Maui, Hawaii, USA (3–6 June, 1991), pp. 520– 525. doi: 10.1109/CVPR.1991.139746

Vincent, L. and Soille, P. (1991) Watersheds in digital spaces: an efficient algorithm based on immersion simulations. IEEE Transactions on Pattern Analysis and Machine Intelligence, 13 (6), 583–598. doi: 10.1109/34.87344

Vinh, T.Q. and Kim, Y.C. (2010) Edge-preserving algorithm for block artifact reduction and its pipelined architecture. ETRI Journal, 32 (3), 380–389. doi: 10.4218/etrij.10.0109.0290

Viola, P. and Wells, W.M. (1997) Alignment by maximization of mutual information. International Journal of Computer Vision, 24 (2), 137–154. doi: 10.1023/A:1007958904918

Vogt, R.C. (1986) Formalised approaches to image algorithm development using mathematical morphology. Vision'86, Detroit, Michigan, USA, pp. 5/17– 5/37 (3–5 June, 1986).

Volder, J.E. (1959) The CORDIC trigonometric computing technique. IRE Transactions on Electronic Computers, EC-8 (3), 330–334. doi: 10.1109/TEC.1959.5222693

Vuillemin, J.E., Bertin, P., Roncin, D., Shand, M., Touati, H.H. and Boucard, P. (1996) Programmable active memories: reconfigurable systems come of age. IEEE Transactions on VLSI Systems, 4 (1), 56–69. doi: 10.1109/92.486081

Wallace, C.S. (1964) A suggestion for a fast multiplier. IEEE Transactions on Electronic Computers, 13 (1), 14–17. doi: 10.1109/PGEC.1964.263830

Wallace, G.K. (1992) The JPEG still picture compression standard. IEEE Transactions on Consumer Electronics, 38 (1), 17–34. doi: 10.1109/30.125072

Walther, J.S. (1971) A unified algorithm for elementary functions. in Spring Joint Computer Conference, Atlantic City, New Jersey, USA (18–20 May, 1971), pp. 379– 385.

Walther, J.S. (2000) The story of unified CORDIC. Journal of VLSI Signal Processing, 25 (2), 107–112. doi: 10.1023/A:1008162721424

Waltz, F.M. (1994a) Application of SKIPSM to binary template matching, in Machine Vision Applications, Architectures, and Systems Integration III, Boston, Massachusetts, USA (31 October–2 November, 1994), vol. 2347, SPIE, pp. 417–427. doi: 10.1117/12.188752

Waltz, F.M. (1994b) Application of SKIPSM to grey-level morphology, in Machine Vision Applications, Architectures, and Systems Integration III, Boston, Massachusetts, USA (31 October–2 November, 1994), vol. 2347, SPIE, pp. 428–435. doi: 10.1117/12.188754

Waltz, F.M. (1994c) Separated-kernel image processing using finite-state machines (SKIPSM), in Machine Vision Applications, Architectures, and Systems Integration III, Boston, Massachusetts, USA (31 October–2 November, 1994), vol. 2347, SPIE, pp. 386–395. doi: 10.1117/12.188749

Waltz, F.M. (1995) Application of SKIPSM to binary correlation, in Machine Vision Applications, Architectures, and Systems Integration IV, Philadelphia, USA (23–24 October, 1995), vol. 2597, SPIE, pp. 82–91. doi: 10.1117/12.223967

Waltz, F.M. and Garnaoui, H.H. (1994a) Application of SKIPSM to binary morphology, in Machine Vision Applications, Architectures, and Systems Integration III, Boston, Massachusetts, USA (31 October–2 November, 1994), vol. 2347, SPIE, pp. 396–407. doi: 10.1117/12.188750

Waltz, F.M. and Garnaoui, H.H. (1994b) Fast computation of the grassfire transform using SKIPSM, in Machine Vision Applications, Architectures and System Integration III, Boston, Massachusetts, USA (31 October–2 November, 1994), vol. 2347, SPIE, pp. 408–416. doi: 10.1117/12.188751

Waltz, F.M., Hack, R. and Batchelor, B.G. (1998) Fast efficient algorithms for 3x3 ranked filters using finite-state machines, in Machine Vision Systems for Inspection and Metrology VII, Boston, Massachusetts, USA (4–5 November, 1998), vol. 3521, SPIE, pp. 278–287. doi: 10.1117/12.326970

Wang, Y. (1998) New Chinese remainder theorems. Thirty-Second Asilomar Conference on Signals, Systems & Computers, Pacific Grove, California, USA, vol. 1 (1–4 November, 1998), pp. 165– 171. doi: 10.1109/ACSSC.1998.750847

Wang, S., Piuri, V. and Swartzlander, E.E. (1996) A unified view of CORDIC processor design. IEEE 39th Midwest Symposium on Circuits and Systems, Ames, Iowa, USA, vol. 2 (18–21 August, 1996), pp. 852– 855. doi: 10.1109/MWSCAS.1996.588050

Wang, Y., Song, X., Aboulhamid, M. and Shen, H. (2002) Adder based residue to binary number converters for (2ⁿ−1, 2ⁿ, 2ⁿ+1). IEEE Transactions on Signal Processing, 50 (7), 1772–1779. doi: 10.1109/TSP.2002.1011216

Wang, J., Hall-Holt, O., Konecny, P. and Kaufman, A.E. (2005) Per pixel camera calibration for 3D range scanning, in Videometrics VIII, San Jose, California, USA (18–20 January, 2005), vol. 5665, SPIE, pp. 342–352. doi: 10.1117/12.586209

Weems, C.C. (1991) Architectural requirements of image understanding with respect to parallel processing. Proceedings of the IEEE 79 (4), 537–547. doi: 10.1109/5.92046

Wei, Z., Lee, D.J., Nelson, B.E., Archibald, J.K. and Edwards, B.B. (2008) FPGA-based embedded motion estimation sensor. International Journal of Reconfigurable Computing, 2008, no. Article ID 636145. doi: 10.1155/2008/636145

Weinhardt, M. and Luk, W. (2001a) Memory access optimisation for reconfigurable systems. IEE Proceedings Computers and Digital Techniques, 148 (3), 105–112. doi: 10.1049/ip-cdt:20010514

Weinhardt, M. and Luk, W. (2001b) Pipeline vectorization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20 (2), 234–248. doi: 10.1109/43.908452

Welch, T.A. (1984) A technique for high-performance data compression. IEEE Computer, 17 (6), 8–19. doi: 10.1109/MC.1984.1659158

Wendt, P.D., Coyle, E.J. and Gallagher, N.C. (1986) Stack filters. IEEE Transactions on Acoustics, Speech and Signal Processing, 34 (4), 898–911. doi: 10.1109/TASSP.1986.1164871

Weszka, J.S., Nagel, R.N. and Rosenfeld, A. (1974) A threshold selection technique. IEEE Transactions on Computers, 23 (12), 1322–1326. doi: 10.1109/T-C.1974.223858

Wigley, G. and Kearney, D. (2001) The development of an operating system for reconfigurable computing. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01), Rohnert Park, California, USA (30 April–2 May, 2001), pp. 249– 250. doi: 10.1109/FCCM.2001.43

Wilen, A., Schade, J.P. and Thornburg, R. (2003) Introduction to PCI Express: A Hardware and Software Developer's Guide, Intel Press.

Will, P.M. and Pennington, K.S. (1972) Grid coding: a novel technique for image processing. Proceedings of the IEEE, 60 (6), 669–680. doi: 10.1109/PROC.1972.8726

Williams, L. (1983) Pyramidal parametrics. ACM SIGGRAPH Computer Graphics, 17 (3), 1–11. doi: 10.1145/964967.801126

Williams, J. (2009) Embedded Linux on Xilinx MicroBlaze. Xilinx University Program and PetaLogix Professor's Workshop Series. PetaLogix Qld Pty Ltd.

Williams, C.S. and Rasure, J.R. (1990) A visual language for image processing. IEEE Workshop on Visual Languages, Skokie, Illinois, USA (4–6 October, 1990), pp. 86– 91. doi: 10.1109/WVL.1990.128387

Willson, R.G. and Shafer, S.A. (1994) What is the center of the image? Journal of the Optical Society of America A, 11 (11), pp. 2946–2955. doi: 10.1364/JOSAA.11.002946

Wilson, G.R. (1997) Properties of contour codes. IEE Proceedings Vision, Image and Signal Processing, 144 (3), 145–149. doi: 10.1049/ip-vis:19971159

Wilson, H.R. and Giese, S.C. (1977) Threshold visibility of frequency gradient patterns. Vision Research, 17 (10), 1177–1190. doi: 10.1016/0042-6989(77)90152-3

Wilson, J.C. and Hodgson, R.M. (1992) Log-polar mapping applied to pattern representation and recognition, Computer Vision and Image Processing, Academic Press, pp. 245–277.

Wilson, R.P., French, R.S., Wilson, C.S., Amarasinghe, S.P., Anderson, J.M., Tjiang, S.W.K., Liao, S.W., Tseng, C.W., Hall, M.W., Lam, M.S. and Hennessy, J.L. (1994) SUIF: an infrastructure for research on parallelizing and optimizing compilers. ACM SIGPLAN Notices, 29 (12), 31–37. doi: 10.1145/193209.193217

Wirthlin, M.J., Hutchings, B.L. and Worth, C. (2001) Synthesizing RTL hardware from Java byte codes, in Field-Programmable Logic and Applications (FPL 2001), Belfast, UK (27–29 August, 2001), Lecture Notes in Computer Science, vol. LNCS 2147, Springer, pp. 123–132. doi: 10.1007/3-540-44687-7_13

Witten, I.H., Neal, R.M. and Cleary, J.G. (1987) Arithmetic coding for data compression. Communications of the ACM, 30 (6), 520–540. doi: 10.1145/214762.214771

Wolberg, G. (1990) Digital Image Warping, IEEE Computer Society Press, Los Alamitos, California.

Wolberg, G. and Boult, T.E. (1989) Separable image warping with spatial lookup tables. ACM SIGGRAPH Computer Graphics, 23 (3), 369–378. doi: 10.1145/74334.74371

Wolberg, G., Sueyllam, H.M., Ismail, M.A. and Ahmed, K.M. (2000) One-dimensional resampling with inverse and forward mapping functions. Journal of Graphics Tools, 5, 11–33.

Wong, S., Vassiliadis, S. and Cotofana, S. (2002) A sum of absolute differences implementation in FPGA hardware. 28th Euromicro Conference, Dortmund, Germany (4–6 September, 2002), pp. 183– 188. doi: 10.1109/EURMIC.2002.1046155

Woods, R., Trainor, D. and Heron, J.P. (1998) Applying an XC6200 to real-time image processing. IEEE Design & Test of Computers, 15 (1), 30–38. doi: 10.1109/54.655180

Wu, K., Otoo, E. and Shoshani, A. (2005) Optimizing connected component labelling algorithms, in Medical Imaging 2005: Image Processing, San Diego, California, USA (15–17 February, 2005), vol. 5747, SPIE, pp. 1965–1976. doi: 10.1117/12.596105

Xilinx (2001) VirtexTM 2.5V Field Programmable Gate Arrays, Vol. DS003 (v2.5), Xilinx Inc.

Xilinx (2007a) Virtex-II Platform FPGAs: Complete Data Sheet, Vol. DS031 (v3.5), Xilinx Inc.

Xilinx (2007b) Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet, Vol. DS083 (v4.7), Xilinx Inc.

Xilinx (2008a) Spartan-3 FPGA Family Data Sheet, Vol. DS099 (v2.4), Xilinx Inc.

Xilinx (2008b) Spartan-II FPGA Family Data Sheet, Vol. DS001 (v2.8), Xilinx Inc.

Xilinx (2008c) Virtex-4 FPGA User Guide, Vol. UG070 (v2.6), Xilinx Inc.

Xilinx (2008d) Virtex-5 FPGA User Guide, Vol. UG190 (v4.4), Xilinx Inc.

Xilinx (2008e) Spartan-3A DSP FPGA Family Data Sheet, Vol. DS610 (v2.1), Xilinx Inc.

Xilinx (2008f) ChipScope Pro 10.1 Software and Cores User Guide, Vol. UG029, Xilinx Inc.

Xilinx (2009a) Spartan-6 Family Overview, Vol. DS160 (V1.0), Xilinx Inc.

Xilinx (2009b) Spartan-3AN FPGA In-System Flash User Guide, Vol. UG333 (v2.1), Xilinx Inc.

Xilinx (2009c) AccelDSP Synthesis Tool User Guide, Vol. UG634 (v11.4), Xilinx Inc.

Xilinx (2010a) 7 Series Overview, Vol. DS150 (V1.0), Xilinx Inc.

Xilinx (2010b) Spartan-6 FPGA CLB User Guide, Vol. UG384 (v1.1), Xilinx Inc.

Xilinx (2010c) Spartan-6 FPGA Memory Controller, vol. UG388 (v2. 1), Xilinx Inc.

Xilinx (2010d) Virtex-6 Family Overview, Vol. DS150 (V2.2), Xilinx Inc.

Yamada, A., Nishida, K., Sakurai, R., Kay, A., Nomura, T. and Kambe, T. (1999) Hardware synthesis with the Bach system. 1999 IEEE International Symposium on Circuits and Systems (ISCAS '99), Orlando, Florida, USA, vol. 6 (30 May–2 June, 1999), pp. 366– 369. doi: 10.1109/ISCAS.1999.780171

Yao, L., Feng, H., Zhu, Y., Jiang, Z., Zhao, D., and Feng, W. (2009) An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher. International Conference on Field-Programmable Technology (FPT 2009), Sydney, Australia (9–11 December, 2009), pp. 30– 37. doi: 10.1109/FPT.2009.5377651

Yu, N., Kim, K. and Salcic, Z. (2004) A new motion estimation algorithm for mobile real-time video and its FPGA implementation. IEEE Region 10 Conference (TENCON), Chiang Mai, Thailand, vol. 1 (21–24 November, 2004), pp. 383– 386. doi: 10.1109/TENCON.2004.1414437

Yuen, H.K., Princen, J., Illingworth, J. and Kittler, J. (1990) Comparative study of Hough transform methods for circle finding. Image and Vision Computing, 8 (1), 71–77. doi: 10.1016/0262-8856(90)90059-E

Zahn, C.T. and Roskies, R.Z. (1972) Fourier descriptors for plane closed curves. IEEE Transactions on Computers, 21 (3), 269–281. doi: 10.1109/TC.1972.5008949

Zhang, D. and Lu, G. (2002) A comparative study of Fourier descriptors for shape representation and retrieval. 5th Asian Conference on Computer Vision, Melbourne, Australia (23–25 January, 2002), pp. 646– 651.

Zingaretti, P., Gasparroni, M. and Vecci, L. (1998) Fast chain coding of region boundaries. IEEE Transactions on Pattern Analysis and Machine Intelligence, 20 (4), 407–415. doi: 10.1109/34.677272

Zitova, B. and Flusser, J. (2003) Image registration methods: a survey. Image and Vision Computing, 21 (11), 977–1000. doi: 10.1145/146370.146374

Ziv, J. and Lempel, A. (1977) A universal algorithm for sequential data compression. IEEE Transactions on Information Theory, 23 (3), 337–343. doi: 10.1109/TIT.1977.1055714

Zoss, R., Habegger, A., Bandi, V., Goette, J. and Jacomet, M. (2011) Comparing signal processing hardware-synthesis methods based on the Matlab tool-chain, in 6th International Symposium on Electronic Design, Test and Applications, Queenstown, New Zealand, pp 281–286 (17–19 January, 2011). doi: 10.1109/DELTA.2011.58