6.1 Digital and Analog

In mixed-signal chips, analog and digital functions are isolated into functional blocks to reduce noise coupling between the digital circuitry and analog functions. The switching noise of the digital circuitry must be isolated to avoid analog functional failures. Figure 6.1 shows an example of a semiconductor chip with separated digital and analog domains. Semiconductor chip architectures today provide the following solutions: (i) separate digital and analog circuit domains, (ii) separate digital and analog V_DD power rails, (iii) separate digital V_SS (DV_SS) and analog V_SS (AV_SS) power rails, (iv) an ESD power clamp for each independent domain, and (v) a bidirectional symmetric diode string between DV_SS and AV_SS.

In the ESD design synthesis process, there is a flow of steps and procedures to construct a semiconductor chip. The following design synthesis procedure is an example of an ESD design flow needed for semiconductor chip implementations:

• I/O, domains, and core floor plan: Define floor plan of regions of cores, domains, and peripheral I/O circuitry.
• I/O floor plan: Define area and placement for I/O circuitry.
• ESD signal pin floor plan: Define ESD area and placement.
• ESD power clamp network floor plan: Define ESD power clamp area and placement for a given domain.
• ESD domain-to-domain network floor plan: Define ESD networks between the different chip domain area and placement for a given domain.
• ESD signal pin network definition: Define ESD network for the I/O circuitry.
• ESD power clamp network definition: Define ESD power clamp network within a power domain.
• Power bus definition and placement: Define placement, bus width, and resistance requirements for the power bus.
• Ground bus definition and placement: Define placement, bus width, and resistance requirements for the ground bus.
• I/O to ESD guard rings: Define guard rings between I/O and ESD networks.
• I/O internal guard rings: Define guard rings within the I/O circuitry.
• I/O external guard rings: Define guard rings between I/O circuitry and adjacent external circuitry.

In this chapter, the focus will be on digital-to-analog interdomain issues.

6.2 Interdomain Signal Line ESD Failures

In foundry and ASIC environments, chips are segregated into “cores” or subfunctions. Where “cores” are established, the chip is naturally segregated into separate functions, and functional blocks are assembled. In ASIC applications, “voltage islands” are also formed between chip sectors for power management. In this case, many chip sectors’ power is shut down, while a given signal path remains “active.” In these applications, the power rails are isolated into separate domains, but signal lines pass from one chip subfunction to another; the electrical connectivity between these domains exist only through the common signal paths (and the substrate wafer).

6.2.1 Digital-to-Analog Signal Line Failures

A common interdomain signal line ESD failure mechanism is signal lines between separated subfunctions [1–36]. Figure 6.2 shows the case of two functional blocks, with an inverter where one is the transmitter and the other is a receiver. The ESD networks are shown in the diagram as well. E. Worley noted that during CDM stress, the receiving inverter network can experience an electrical stress on the MOSFET gate dielectric input [14]. This is due to the resistance of the V_SS ground rails, the ESD diode turn-on, and the resistances. Worley noted that the transmitter n-channel MOSFET can transfer current from the charged chip substrate to the transmitter output signal. In that case, current will flow through the signal line between the transmitter and the receiver leading to MOSFET gate dielectric failure in the MOSFET receiver gate.

A common interdomain signal line ESD failure mechanism is signal lines between digital and analog subfunctions [1–14, 34–36]. Digital-to-analog interfaces occur in digital-to-analog converters (DAC) and analog-to-digital converters (ADC). Figure 6.3 shows the case of two functional blocks, with an inverter where one is the transmitter and the other is a receiver. The ESD networks are shown in the diagram as well. As in Figure 6.2, the receiving inverter network can experience an electrical stress on the MOSFET gate dielectric input. Current will flow through the signal line between the transmitter and the receiver leading to MOSFET gate dielectric failure in the MOSFET receiver gate.

In this concept, proposed solutions to address these failure mechanisms, the following solutions were recommended:

• Resistor elements between V_DD power rails (e.g., V_DD to V_DD) as well as V_SS power rails (e.g., V_SS to V_SS)
• Back-to-back diodes between V_DD power rails (e.g., V_DD to V_DD) as well as V_SS power rails (e.g., V_SS to V_SS)
• Adding CDM ESD circuits between the transmitter and receiver networks providing an “internal” ESD network
• Adding an additional “third-party” functional block to transmit signals between a first and second functional block
• Using additional intervening blocks within the signal path

6.3 Digital-to-Analog Core Spatial Isolation

Figure 6.4 shows the floor plan of a mixed-signal semiconductor chip [34–36]. The digital and the analog cores are spatially separated. This minimizes digital noise from impacting analog circuitry.

6.4 Digital-to-Analog Core Ground Coupling

Figure 6.5 illustrates a circuit schematic of an ESD network between the digital and the analog grounds (e.g., DV_SS to AV_SS) in a mixed-signal semiconductor chip.

6.4.1 Digital-to-Analog Core Resistive Ground Coupling

Figure 6.6 shows an example of an analog-to-digital domain with resistor elements between the power supplies. Resistive coupling allows for the control of the resistance between the two chip subfunctions through design.

6.4.2 Digital-to-Analog Core Diode Ground Coupling

Analog-to-digital subfunctions place antiparallel diode strings between the ground power rails for ESD protection [34–36]. For ESD protection, it is common to place antiparallel diode strings between the electrical grounds to establish ESD current paths between the V_SS power rails (e.g., AV_SS and DV_SS). Figure 6.7 highlights an architecture where the V_SS-to-V_SS ESD power rail is an antiparallel diode string. In the placement of the antiparallel diode strings, the bus resistance of the V_SS and the V_DD can play a role in the voltage stress across the signal lines. In the case of signal lines between functional blocks, a voltage differential can be established between the output of a first logic block and the input of the second logic block.

6.5 Domain-to-Domain Signal Line ESD Networks

Figure 6.8 shows an example of an interdomain ESD network. For CDM solutions, the second-stage network consists of a resistor and dual-diode element [14]. Other CDM networks can consist of a resistor and MOSFET element.

6.6 Domain-to-Domain Third-Party Coupling Networks

Voltage drops along cross-domain signal lines can be achieved by introduction of additional circuitry along the signal path. A “third-party” functional block to transmit the signals between the transmitter and the receiver can be introduced [14]. This third-party block contains two inverters in series, supportive ESD elements, and its own independent power rails (Figure 6.9).

6.7 Domain-to-Domain Cross-Domain ESD Power Clamp

A means to avoid current flow from the digital power rail (DV_DD) and the analog ground rail (AV_SS) can be achieved by introduction of a “cross-domain” ESD network [34–36]. Figure 6.10 illustrates a circuit schematic highlighting the cross-domain ESD network. The cross-domain ESD network can be the following:

• Silicon-controlled rectifier (SCR)
• GGNMOS
• Series diodes
• RC-triggered MOSFET power clamp

6.8 Digital-to-Analog Domain Moat

In mixed-signal applications, noise isolation and substrate injection are critical for analog circuitry. Noise isolation can be improved by placement of a “moat” that isolated the digital and analog core regions (Figure 6.11) [34–36]. With the placement of a “moat,” the resistance between the two regions can be increased to provide improved noise isolation. Additionally, the minority carrier transport between the digital and analog domains can be decreased.

6.9 Digital-to-Analog Domain Moat with Through-Silicon Via

In system-on-chip (SOC), 2.5-D, and 3-D applications, through-silicon via (TSV) structures are integrated into the technology. TSV structures are integrated into memory, microprocessors, and other mixed-signal applications. Noise isolation can be improved by placement of the TSV structures within the moat that isolated the digital and analog core regions (Figure 6.12). With the placement of an array of TSV structures or “bar” TSV structures (e.g., high aspect ratio length and width), the resistance between the two regions can be increased to provide improved noise isolation [37–45]. Additionally, the minority carrier transport between the digital and analog domains can be decreased.

6.10 Domain-to-Domain ESD Design Rule Check and Verification Methods

ESD checking and verification are used to address finding the cross-domain signal lines to avoid ESD failure [15–33]. These ESD design checking used various methods that address circuit topology connectivity and resistance along the signal lines that cross the digital-to-analog domain. This will be discussed in Chapter 12.

6.11 Closing Comments and Summary

This chapter addressed integration of digital and analog domains where they are required to be decoupled due to noise. Electrical isolation of the two domains leads to ESD failures between the grounds, as well as along signal lines that cross these separated domains. ESD solutions between the ground connections include coupling using resistors and diode elements, as well as third-party functional blocks. ESD solutions along the signal lines include the ground connections as well as the ESD networks on the signal lines that cross the digital-to-analog domain.

Chapter 7 addresses analog and ESD signal pin cosynthesis that introduces usage of interdigitated layout and common centroid concepts to provide ideal matching, low capacitance, and small area in differential signal pins. Using interdigitated designs, the parasitic elements are utilized for signal pin-to-signal pin ESD protection.

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