10.1 Latchup in Analog Applications

CMOS latchup is a concern in advanced semiconductor CMOS, BiCMOS, and bipolar–CMOS–LDMOS (BCD) technologies within a given circuit, between adjacent circuits, and between domains [1–59]. Due to technology scaling, the physical distances between p-channel MOSFETs and n-channel MOSFETs continue to be reduced in the periphery and core of circuits. With density scaling, the number of I/O circuits increases according to Rent’s rule. As a result, the aspect ratio of peripheral I/O circuitry continues to move toward “long/narrow I/O standard cells” with decreased spacing between adjacent I/O standard cells. Hence, the interaction between adjacent I/O (e.g., I/O to I/O) will continue to be a design issue associated with CMOS latchup. In addition, with mixed signal (MS) and system on chip (SOC), the placement of circuits of different domains can also lead to CMOS latchup concerns.

Figure 10.1 shows possible latchup issues in a semiconductor chip. The focus in this chapter will be on the issue of I/O-to-I/O latchup [6, 7], guard rings [8–18], through-silicon via (TSV) [32–39], deep trench [40–46], and active guard rings [47–59]. Test structures that address I/O-to-I/O interactions will be discussed. Electrical measurements of parasitic bipolar current gain and analysis will be shown.

10.2 I/O-to-I/O Latchup

I/O-to-I/O latchup can occur with the formation of a lateral parasitic pnpn network between two adjacent I/O cells [6]. With two adjacent I/O standard cells, latchup can occur in multiple interactions due to the two PFETs and two NFETs. The adjacent standard cells can be the following:

• Digital-to-analog I/O
• Analog I/O to analog I/O
• High-voltage I/O to analog I/O
• Analog I/O to ESD
• Analog I/O to ESD power clamp
• Analog I/O to grounded n-well plate
• Analog I/O to decoupling capacitor

I/O-to-I/O latchup can occur between two n-well regions of adjacent analog standard cell and an adjacent structure. To quantify I/O-to-I/O latchup concerns, a structure can be formed to address all interactions. Two four-stripe structures can be formed in a test structure as shown in Figure 10.2.

10.3 I/O-to-I/O Latchup: N-Well to N-Well

I/O-to-I/O latchup can occur between two n-well regions of adjacent analog standard cells. A lateral pnpn can be formed between the first I/O network PFET, its own n-well, the p-substrate, and an adjacent n-well (Figure 10.3) [6].

The critical parameter of interest is the spacing between the two adjacent cells forming a lateral npn between the first and second n-well regions. As the technologies are scaled, the bond pad will be scaled, decreasing the space between the two adjacent n-well regions. As the spacing decreases, the npn bipolar current gain will increase with the n-well-to-n-well space. Note that this interaction is symmetrical and bidirectional (e.g., there are two pnpn parasitic elements formed). Tables 10.1 and 10.2 show the lateral bipolar npn gain as a function of n-well-to-n-well spacing at 25 and 125°C, respectively (Figures 10.4 and 10.5).

10.4 I/O-to-I/O Latchup: N-Well to NFET

A lateral pnpn can be also formed between the first I/O network PFET, its own n-well, the p-substrate, and the adjacent n-channel MOSFET device of the second I/O cell (Figure 10.6) [6]. In this case, the NFET pull-down source serves as the emitter of the pnpn network. Test structures varied all the design variables to evaluate the npn bipolar current gain between the n-well of the first standard cell and the adjacent “NFET” structure.

Table 10.3 contains experimental results of NW to n+ where the well-to-well spacing was varied from 15 to 5 µm (Figures 10.7 and 10.8). Table 10.3 is data for a p+/n+ spacing of 2.4 µm.

An interesting experimental results showed that as the NFET (I/O = 2) became closer to the n-well (I/O = 2), the bipolar current gain between the n-well (I/O = 1) and NFET (I/O = 2) decreased!.

Table 10.4 shows the bipolar gain of NW(1) –to – n+ (2), as the p+/n+ spacing is reduced in the design. The lateral bipolar current gain decreases from 0.5 to 0.4 (at 25°C); note that it decreased instead of increasing. This is counterintuitive. The reason for the reduction is the NW(2) starts to collect the carrier from NW(I/O = 1) to n + (I/O = 2), serving as a “pseudo guard ring” for this interaction [6].

10.5 I/O-to-I/O Latchup: NFET to NFET

A third interaction of interest is the lateral npn bipolar transistor formed between the two adjacent NFET devices [6]. In this case, only a lateral npn is formed (Figure 10.9). Table 10.5 shows the experimental results as a function of the n-well-to-n-well spacing (leading to a smaller base width between the two NFETs).

10.6 I/O-to-I/O Latchup: N-Well Guard Ring between Adjacent Cells

In some foundries, an n-well guard ring is placed between the two adjacent cells. With the placement of the n-well guard ring, carriers will be collected by the adjacent n-well guard ring instead of the adjacent I/O cell’s n-well or NFET region [6]. Figure 10.10 shows the standard cell with an n-well guard ring diffusion, and Table 10.6 shows the experimental results. In this implementation, the issue is the npn bipolar current gain between the PFET tub and the n-well guard ring, as well as the n-well guard ring series resistance.

10.7 Latchup of Analog I/O to Adjacent Structures

Many CMOS latchup problems today occur due to the placement of circuits adjacent to each other without verification of the interaction. This will become more important in analog design as technology spacings are reduced in CMOS, BiCMOS, BCD, and high-voltage and ultrahigh-voltage technologies.

10.7.3 Latchup and Decoupling Capacitors

In analog design, the density of the I/O is not as limited due to the reduced pin count for analog applications [6, 7]. One of the critical problems is that digital standard cells are used for analog applications, where it is anticipated that the periphery is 100% I/O cells. Figure 10.11 shows an example where the decoupling capacitors were placed between the standard cell I/O circuitries. The decoupling capacitor contains a grounded n-well bottom plate to form the capacitor structure. With the grounded n-well plate adjacent to an I/O PFET, a lateral pnpn is formed between the PFET, the n-well associated with the PFET, the substrate, and the decoupling capacitor.

10.8 Analog I/O to Core

CMOS latchup occurs in analog and MS application between the I/O circuitry and the cores [3]. Guard rings can be placed to separate the analog I/O from digital cores and the digital I/O from the analog cores. Figure 10.12 shows test structures to evaluate external latchup between I/O and core circuitries. The placement of I/O PFET and I/O NFET “injectors” from core circuitry is a design issue. In addition, guard rings can be placed between the I/O and the core networks to collect minority injection carriers. These guard rings can also help reduce the noise interaction between the I/O and analog cores.

10.9 Core-to-Core Analog–Digital Floor Planning

In a semiconductor chip, the analog and digital core floor planning is key to prevent the digital noise from impacting analog circuitry. Spatial separation of the circuits and signal lines is critical as well as isolation using moats and guard rings.

10.9.1 Analog–Digital Moats and Guard Rings

Within a MS chip, analog and digital domains are physically separated to avoid digital noise and injection from affecting analog circuitry. Figure 10.13 is an example of MS floor plan. The digital and analog domains are separated by establishing a “moat.” The physical spacing between the digital and analog domains can be moat widths on the order of 10–50 µm.

10.10 High-Voltage Guard Rings

Within an LDMOS technology, there are a significant number of design layers which allow for utilization for guard rings and noise isolation [28–31]. Figure 10.14 shows an example of guard rings that contain deep implant layers to provide an improved collection of minority carriers in the substrate. With the deep implants, the guard ring efficiency is improved. With improved guard ring efficiency, noise and latchup can be reduced in CMOS analog circuitry.

Figure 10.15 contains a semiconductor chip floor plan which contains high-voltage, digital, and analog domains. The high-voltage domain is spatially separated from the analog circuitry by the digital domain, as well as two moats.

10.11 Through-Silicon Via (TSV)

TSV structures have been introduced in advanced technologies for multichip integration. TSV structures have been integrated into silicon chips and silicon interposers. In MS chips, where digital and analog functions are on the same semiconductor chip, TSV can be used between the two domains to provide noise isolation and minimize minority carrier injection [32–39]. Figure 10.16 shows an example of a TSV guard ring structure. Figure 10.17 shows a cross section of the wafer highlighting the TSV depth extends from the top to the bottom of the wafer. TSV structures can be placed in the moat area between the digital and analog domains, allowing collection of the minority carriers and eliminating external latchup.

10.12 Trench Guard Rings

Deep trench structures can be utilized to improve the latchup robustness and noise reduction in CMOS, BiCMOS, and LDMOS technologies [40–46]. Deep trench structures are used for high-performance bipolar transistors. Deep trench structures reduce collector to substrate capacitance in bipolar transistors; these can be utilized for noise reduction and latchup. Deep trench structures can be used for guard rings (Figures 10.18 and 10.19). Deep trench structures can be on the order of 5–10 µm deep from the silicon surface. Deep trench structures prevent lateral minority carrier transport.

10.13 Active Guard Rings

Today, SOC solutions have been used for solving the MS requirements. SOC applications have a wide range of power supply conditions, number of independent power domains, and circuit performance objectives. Different power domains are established between digital and analog circuits on an integrated chip. The integration of different circuits and system functions into a common chip has also resulted in solutions for ensuring that noise from one portion or circuit of the chip does not affect a different circuit within the chip.

With the chip integration issues, the need for better guard rings and alternative guard ring solutions has had increased interest [47–59]. Since 2000, there has been an increased focus on guard ring solutions that achieve the following objectives:

• Solutions that achieve noise isolation, latchup robustness, and ESD results
• Solutions which do not inject current back into the power grid

With the growth of interaction between digital and analog domains, new guard ring concepts have increased in importance. In addition, with the growth of smart power technology, solutions are needed for avoidance of interaction of the high-voltage CMOS (HVCMOS) chip sectors and the low-voltage sectors of a CMOS chip.

Different “active” guard ring circuit concepts have been introduced for latchup improvement. In “active” guard rings, the objective is to not only collect minority carriers but to actively compensate the effect. The latchup circuit design discipline includes the following concepts:

• Electrically collecting minority carriers at a metallurgical junction and whose junction is electrically connected to the chip substrate to alter the substrate potential
• Electrically collecting minority carriers at a metallurgical junction and whose junction is electrically connected to the chip substrate, to alter the substrate potential, with the objective of reduced forward bias of the injection structure
• Electrically collecting minority carriers at a metallurgical junction and whose junction is electrically connected to the chip substrate, to alter the substrate potential, with the objective of introduction of a lateral electrical field assist to reduce the lateral bipolar current gain
• Electrically sensing the substrate potential drop and inverting the polarity of the potential drop using inverting amplifier networks

Figure 10.20 is an example of an active guard ring. Typically, in a passive guard ring concept, a p+ substrate contact is electrically connected to a V_SS power rail, and an n-well ring is electrically connected to a V_DD power rail. But in an active guard ring, an n-well region is not electrically connected to a power rail. In an active guard ring, the n-well structure collects the minority carrier electrons in its metallurgical junction formed with the p-substrate region. The n-well ring is electrically connected to a “soft grounded” p+ substrate contact. When the minority carrier electrons traverse the metallurgical junction, it reduces the electrical potential of the n-well region (e.g., denoted in the figure as ΔV). By electrically connecting the n-well to the p+ substrate contact, the electrical potential of the substrate is also lowered by the same potential magnitude. In this case, the electrical potential of the region is lowered. The lowering of the substrate potential can be utilized as two means. First, given the p+ diffusion is near a forward-bias structure (e.g., an injecting structure), the reduction of the potential can lower the forward-bias state, turning off the injection process. Second, given another p+ substrate contact, a lateral electric field can be established which inhibits the flow of minority carriers. Given a parasitic npn bipolar transistor is formed between the injection source and a collecting victim circuit, if the lateral electrical field opposes the current transport, the lateral npn bipolar current gain is reduced.

Figure 10.21 demonstrates the “electric field assist” wherein in this case, the electric field reduces the lateral bipolar current gain. In this methodology, the placement of the p+ region can be on the injection side or collection side of the n-well region. By adding an additional p++ substrate diffusion inside of the n-well ring/p+ substrate contact, a well defined electric field is established. A p+ region is flanking both sides of the n-well ring, with an outer p+ substrate contact electrically connected to the n-well ring.

Figure 10.22 introduces a secondary p+ passive guard ring. Various implementations of guard rings are utilized where a plurality of p+ substrate contacts and n-wells are integrated, mixing both the active and passive concepts, where some of the wells are “floating” and some electrically connected to the power supplies. In these implementations, a plurality of trench structures can also be added to reduce the lateral bipolar current gain. In all cases, as the number of additional guard rings is increased, as well as the effective base width, the bipolar current gain decreases.

10.14 Closing Comments and Summary

In this chapter, latchup in analog design was discussed. This chapter addressed solutions to avoid digital noise from impacting analog circuitry. Solutions such as spatial placement of digital and analog cores in a mixed-signal chip as well as guard rings between the domains are discussed. Moats, guard rings, and TSV advantages and disadvantages are discussed as possible solutions to minimize both noise and latchup are highlighted. Special features, such as grounded wells, and decoupling capacitor issues and how they can lead to latchup in analog applications are also reviewed. In conclusion, I/O-to-I/O interactions as a function of standard cell-to-standard cell spacings were discussed. As technology spacings are reduced, cell-to-cell latchup will increase in importance in analog design.

In Chapter 11, ESD and EOS libraries and documents for an analog or MS technology are discussed. The discussion includes a plethora of items, from analog libraries, ESD library elements, Cadence-based parameterized cells, and Cadence-based hierarchical ESD designs to ESD cookbooks.

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