Index

  • ADCs see analog-to-digital converter (ADCs)
  • analog circuits
    • Analog-digital converter (ADC)
    • bandgap reference
    • bandgap regulators
    • boost DC/DC converters
    • buck/boost converters
    • buck converters
    • comparators
    • current mirrors
    • DC converters
    • differential operational amplifiers
    • low dropout (LDO)
    • operational amplifiers
    • phase lock loops (PLL)
    • receivers
    • regulators
    • switches
    • system clocks
  • analog design
    • active guard rings
    • analog–digital (pre)
    • analog domain
    • guard rings
    • mixed signal
  • analog–digital mixed signal design synthesis
    • analog-to-digital guard rings
    • breaker cells
    • digital to analog design ESD solutions
    • digital to analog signal lines
    • floorplanning
    • guard rings
    • power domains
    • power grid
  • analog ESD power clamps
    • bipolar ESD power clamps
    • CMOS ESD power clamps
    • high voltage power clamps
    • low voltage power clamps
  • analog layout
    • array
    • capacitors
    • common centroid design
    • differential circuitry
    • diodes
    • resistors
    • thermal lines
  • analog layout design matching
    • capacitor matching rules
    • common centroid design
    • resistor matching rules
    • thermal lines
  • analog-to-digital converter (ADCs)
  • application specific integrated circuits (ASICs)
    • ESD design
  • Assemblies
  • auditing
    • assembly
    • audit cycle
    • documentation
    • ESD control program
    • manufacturing
  • avalanche
    • avalanche breakdown
    • avalanche multiplication
  • bandgap references
  • bandgap regulators
  • bipolar transistors
    • parasitic bipolar transistors
  • bond pad
    • ESD adjacent to bond pad
    • ESD under bond pad
    • octagonal bond pad
    • rectangular bond pad
  • boost converter
  • boost DC/DC converters
  • buck–boost converters
  • buck converters
  • bus
    • across ESD bus resistance
    • clamp-to-clamp resistance
    • ESD dummy bus
    • ground bus
    • power bus
  • cable discharge event (CDE)
  • cassette model
  • CDM see charged device model (CDM)
  • charged board model (CBM)
  • charged cable model
  • charged device model (CDM)
    • standard
    • test
    • un-socket charged device model
  • checklists
    • audits
    • ESD protection design
    • manufacturing audit
    • semiconductor chip architecture
    • semiconductor chip design
    • semiconductor chip design rule checking (DRC)
  • comparators
  • converters
    • AC/DC
    • boost
    • buck
    • buck–boost
    • Cuk DC/DC
    • DC/AC
  • current mirror
    • Widlar
  • DAC see digital to analog converter (DAC)
  • deep trench
    • bipolar transistors
    • ESD structures
    • floating polysilicon-filled trench
    • guard ring structures
    • latchup
    • polysilicon filled deep trench structures
  • degradation
    • alternating current (AC)
    • direct current (DC)
  • design synthesis
    • ESD power clamp
    • ESD signal pin
    • ground bus
    • ground power rail
    • power rail
  • dielectrics
    • inter-level dielectric (ILD)
    • metal–insulator–metal
    • vertical natural plate (VNP) capacitor
    • vertical parallel plate (VPP)
  • differential operational amplifiers
  • differential pair circuits
    • differential pair ESD networks
    • differential pair failure mechanisms
  • digital to analog converter (DAC)
  • diodes
    • high current conduction
    • self-heating
    • series resistance
  • direct current (DC) converters
    • AC/DC converters
  • dynamic read-access memory (DRAM)
  • electrical overstress (EOS)
    • electrical over-current
    • electrical over-voltage
    • failure mechanisms
    • high voltage electronics
    • latchup
    • power electronics
    • protection
      • diodes
      • fuses
      • MOSFETs
      • off-chip design
      • on-board design
      • on-chip design
      • resistors
      • silicon controlled rectifiers (SCR)
      • transient voltage suppression (TVS)
    • time constant
  • electrical over-voltage (EOV)
  • electromagnetic compatibility (EMC)
    • components
    • susceptibility
    • systems
  • electromagnetic interference (EMI)
    • equipment
    • noise
    • shielding
  • electrostatic discharge (ESD) circuits
    • common centroid ESD
    • cross-domain ESD power clamps
    • cross-domain internal signal path ESD networks
    • differential pair ESD
    • DVDD-to-AVDD ESD
    • DVDD-to-AVSS ESD
    • DVSS-to-AVSS ESD
    • ESD power clamps
    • ESD signal pin
    • internal ESD networks
    • signal path cross-domain ESD
  • electrostatic discharge (ESD) design
    • floorplanning
    • placement
    • power clamps
    • rail-to-rail designs
    • signal pin designs
  • electrostatic discharge (ESD) power clamps
    • breakdown voltage triggered
    • CMOS
    • RC-triggered power clamp
    • Zener-diode breakdown voltage triggered
  • electrostatic discharge program manager
    • checklists
    • controls
    • handling
    • manufacturing
    • packaging
    • semiconductor chip design
  • EMC see electromagnetic compatibility (EMC)
  • EMI see electromagnetic interference (EMI)
  • EOS see electrical overstress (EOS)
  • error amplifier
  • Brokaw
  • failure
    • charged board event (CBE)
    • charged board model (CBM)
    • charged device model (CDM)
    • conductor
    • device
    • dielectric
    • human body model (HBM)
    • human metal model (HMM)
    • IEC 61000-4-2
    • machine model (MM)
    • system
  • failure criteria
    • analog circuit
    • digital circuit
    • noise figure (NF)
    • radio frequency circuits
    • test equipment
  • feedback
    • avalanche multiplication
    • regenerative feedback
  • floorplanning
    • application specific integrated circuits (ASICs)
    • charged device model ESD networks
    • DRAM
    • ESD power clamps
    • ESD signal pins
    • microprocessors
  • guard rings
    • ESD
    • ESD-to-I/O
    • I/O-to-core
    • I/O to I/O
    • latchup
  • human body model (HBM)
    • alternative test methods
    • characterization method
    • ESD protection circuit solutions
    • failure criteria
    • failure mechanisms
    • pin-to-pin test
    • pin-to-power supply test
    • pulse waveform
    • test
    • waveform
  • human metal model (HMM)
    • air discharge method
    • characterization method
    • commercial test systems
    • direct contact method
    • equipment requirements
    • ESD gun
    • failure mechanisms
    • IEC current waveform
    • pin combinations
    • powered board
    • pulse source
    • pulse waveform
    • standard practice (SP)
    • standard test method (STM)
    • test levels
  • inductors
    • analog metal (AM) inductors
    • ESD inductors
    • low resistance
    • quality factor
    • under-pass connections
  • instability
    • electrical instability
    • electro-thermal instability
    • spatial instability and current constriction
  • interconnect resistor
    • aluminum interconnect resistor
    • cladding resistor
    • copper interconnect resistor
    • tungsten M0 wiring resistor
  • International Electro-technical Commission (IEC)
    • IEC 61000-4-2
    • IEC 61000-4-5
    • standards
    • technical reports
    • technical specifications
  • I/O
    • peripheral I/O
  • isolation structures
    • deep trench isolation
    • dual depth shallow trench isolation
    • LOCOS
    • shallow trench isolation
  • Johnson limit
    • breakdown-frequency relationship
    • power relationship
    • voltage relationship
  • key parameters
    • capacitors
    • diode
    • ESD power clamp networks
    • ESD signal pad networks
    • MOSFET
    • power bus
    • resistors
    • vias
    • wiring
  • latchup
    • deep trench
    • shallow trench isolation
    • trench isolation
  • latchup testing
    • characterization method
    • commercial test equipment
    • equipment requirements
    • failure criteria
    • standard
  • LDO regulator see low dropout (LDO) regulator
  • leakage mechanisms
  • linearity
  • LOCOS isolation
    • n+/substrate diodes
    • n-well-to-n-well lateral bipolar
    • n-well-to-substrate diodes
    • p+/n-well diode
    • thick oxide MOSFET
  • low dropout (LDO) regulator
  • machine model (MM)
    • failure criteria
    • HBM correlation
    • pin-to-pin test
    • powered human body model
    • power supply pin testing method
    • separation of power supply domains
    • Standard Test Method (STM)
    • waveform
  • matching
    • common centroid design
    • differential pair
    • etch variation mismatch
    • photolithographic mismatch
    • resistor
    • systematic variation
    • transistor
  • metal–insulator–metal (MIM) capacitor
  • microprocessors
    • phase lock loops
    • system clocks
  • MIM capacitor see metal–insulator–metal (MIM) capacitor
  • mismatch
    • etch variation
    • mechanical stress
    • photo-lithography
  • MM see machine model (MM)
  • models
    • cable discharge event (CDE)
    • charged device model
    • human body model (HBM)
    • human metal model (HMM)
    • latchup
    • machine model (MM)
    • transient latchup
    • very-fast transmission line pulse (VF-TLP) model
  • MOSFET
    • avalanche breakdown
    • characterization
    • current constriction model
    • dielectric breakdown
    • high current device physics
    • parasitic bipolar equation
    • series cascode
    • snapback
  • n+ diffusion resistor characterization
  • noise
    • latchup and noise
  • n-well resistor characterization
    • contact layout
    • diffused well
  • off-chip driver circuits
    • RF CMOS off-chip driver
  • operational amplifiers
    • phase lock loops (PLL)
  • quality factor (Q), inductors
  • receiver networks
    • bipolar receivers
    • CMOS receivers
    • differential receiver
    • feedback networks
    • Schmitt trigger networks
    • single-ended cascode receivers
    • single-ended receivers
  • regulators
    • boost
    • buck
    • buck–boost
    • Cuk
  • resistance
    • across ESD bus resistance
    • bond pad to ESD signal pin
    • ESD power clamp network
    • ESD power rail to ESD power clamp resistance
    • ESD signal pin network
  • resistors
    • analog resistor design
    • ballast resistors
    • common centroid design
  • retrograde wells
    • n-well
    • sheet resistance
  • safe operation area (SOA)
    • electrical safe operation area (E-SOA)
    • thermal safe operation area (T-SOA)
    • transient safe operation area
  • salicide
    • cobalt salicide
    • latchup stability criteria
    • titanium salicide
  • scaling
  • second breakdown
  • sensitivity parameters
  • shallow trench isolation ESD devices
  • silicide block mask, MOSFETs
  • silicides
  • silicon controlled rectifiers
    • holding current relationship
    • regenerative feedback analysis
  • snapback
    • bipolar
    • MOSFET
  • SOA see safe operation area (SOA)
  • SRAM see static read-access memory (SRAM)
  • stability
    • electrical stability
    • electro-thermal stability
  • standards
    • ESD Association transient latchup upset (TLU) standard
    • JEDEC latchup standard
  • static read-access memory (SRAM)
    • design
  • symmetry
    • common centroid design
    • ESD design symmetry
    • layout symmetry
  • system clocks
  • system level model
    • cable discharge event
    • ESD gun
    • human metal model
    • IEC 61000-4-2
    • IEC 61000-4-5
  • test
    • external latchup characterization
    • internal latchup characterization
    • techniques
      • chip level
      • system level
  • TLP testing see transmission line pulse testing
  • transient latchup
  • transient latchup upset (TLU)
  • transient voltage suppression (TVS) devices
    • electronic polymers
    • surge protection
  • transmission line pulse (TLP) testing
    • current vs. voltage (I–V) plot
  • triple well
  • TVS devices see transient voltage suppression (TVS) devices
  • very fast transmission line pulse (VF-TLP) model
    • characterization method
    • commercial test equipment
    • current vs. voltage (I–V) characteristic
    • failure criteria
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