This book Electrostatic Discharge (ESD): Analog Circuits and Design was initiated based on the need to produce a text that addresses the fundamentals of electrostatic discharge (ESD) requirements for analog and power electronic devices, components and systems. As the manufacturing world evolves, semiconductor devices are scaling and systems are changing. As a result, the needs and requirements of reliability and ESD robust products are increasing. A text is required that connects and synthesizes the fundamentals of analog design discipline and the ESD discipline. Whereas significant texts are available today to teach experts on ESD on-chip design for digital design discipline and radio frequency (RF) design discipline, there is no single textbook devoted to ESD on-chip design dedicated to analog design.

With the growth of mixed signal applications that integrate both the digital and analog circuitries on a common semiconductor chip, there is a growing interest in the concerns associated with ESD design and protection within a digital–analog application. New issues arise by the integration of two separate cores within a chip, where the digital and the analog domains are separated spatially and electrically. As a result, new problems arise with the design synthesis and architecture of an analog–digital mixed signal semiconductor chip.

With the growth of power management and power devices, there is an additional challenge in providing ESD protection within a power application. In power technology, the number of allowed power conditions has grown significantly, leading to a significant difficulty to provide ESD protection.

In addition, there is a growing interest in electrical overstress (EOS). Today, there is a need for understanding the fundamentals of EOS. Necessarily experts, non-experts, non-technical staff and layman should understand the problems that the world faces today. Today, real-world EOS issues surround us; this occurs in manufacturing environments, power sources, machinery, actuators, solenoids, soldering irons, cables, and lightning. When there is switching, poor grounding, ground loops, noise and transient phenomena, there is a potential for EOS of devices, components, and printed circuit boards. Hence, there is a need for experts and non-experts to understand the issues that revolve around us and the steps to be taken to avoid them. At present, this book is the only textbook on the issues of EOS. In this book, EOS issues for analog and power applications are emphasized.

Hence, there is an opportunity to intermix the analog design discipline and the ESD design discipline to produce a synthesized “ESD analog design discipline” that utilizes analog design techniques and ESD protection techniques.

This book has multiple goals and are as follows.

The first goal is to teach the basic and fundamental concepts of the analog design discipline.

The second goal is to review the analog circuit building blocks used in analog design, such as current mirrors, error amplifiers, feedback loops, and comparators, and to discuss the bandgap reference circuits and low dropout regulators.

The third goal is to discuss EOS and ESD, that is to explain the practices, devices, and novel concepts to address both ESD and EOS on-chip and off-chip.

The fourth goal is to discuss the needs for analog circuits and design associated with CMOS latchup. This involves understanding of latchup in a mixed signal digital–analog environment.

The fifth goal is to explain the semiconductor chip floorplanning to address ESD, EOS and latchup in an analog–digital mixed signal environment. Latchup issues, placement, and guard ring requirements will be highlighted.

The sixth goal is to describe the novel concepts that provide both analog and ESD advantages.

And, the last goal is to highlight the electrical design automation (EDA) methods for analog, analog–digital mixed signal, and power electronics to provide ESD and EOS robust products.

This book is organized as to allow the reader to learn the fundamentals of ESD analog design.

In Chapter 1, analog design principles associated with matching and design symmetry are discussed, and EOS and its relationship with other phenomena, such as ESD, electromagnetic interference, electromagnetic compatibility, and latchup are explained. EOS is defined as well in terms of electrical over-current, electrical over-power, and other concepts. ESD and EOS events on analog applications are also emphasized. As a result, we will draw distinctions through the text on difference of failure analysis, time constants, and other means of identification and classification. A plan to define safe operating area and its role in EOS is also emphasized.

In Chapter 2, the analog design layout practices of interdigitated design layout and common centroid concepts in one- and two dimensions are discussed. These concepts are implemented into ESD networks and the cosynthesis of analog circuits and ESD networks.

In Chapter 3, examples of analog building blocks and circuits that exist in analog designs are provided for readers unfamiliar with analog circuit networks. The analog circuit examples include single-ended receivers, differential receivers, comparators, current mirrors, bandgap regulators, and voltage converters. Voltage regulators of interest include buck, boost, buck–boost, and other circuit topologies.

In Chapter 4, the analog ESD design discipline is introduced, applying both the ESD requirements and the layout concepts of analog circuitry. This includes the digital ESD design discipline, in contrast to the analog ESD design discipline.

In Chapter 5, the analog design synthesis on a high level, by addressing the floorplanning of a mixed signal chip application is discussed. This includes the digital and analog power domain floorplanning, digital and analog power grid, digital to analog breaker cells, and ESD concerns in digital–analog mixed signal chips. Additionally, the guard ring and moats within the chip architecture are discussed, and active and passive guard ring concepts are shown.

In Chapter 6, the signal line ESD failures in digital and analog domains where they are required to be decoupled due to noise are addressed. ESD solutions between the ground connections include coupling using resistors, diode elements, as well as third-party functional blocks. ESD solutions along the signal lines include the ground connections as well as the ESD networks on the signal lines that cross the digital to analog domain.

In Chapter 7, the analog and ESD signal pin cosynthesis that introduces the usage of inter-digitated layout and common centroid concepts to provide ideal matching, low capacitance, and small area in differential signal pins is addressed. Using interdigitated designs, the parasitic elements are utilized for signal pin-to-signal pin ESD protection. In conclusion, the issue of common centroid design of ESD protection networks which integrates signal pin-to-signal pin ESD protection with the inter-digitation pattern for ESD pin-to-rail protection network for differential pair circuitry is discussed for the first time. With integration of the ESD pin-to-rail solution and the ESD signal pin solution, a significant reduction in the area and loading effect for CMOS differential circuits is established. This novel concept will provide significant advantage for present and future high-performance analog and RF design for matching, area reduction, and performance advantages.

In Chapter 8, analog and ESD integration is focused. Topics such as analog signal pin input circuitry and ESD power clamps are discussed, and ESD power clamp issues and solutions are explained in more details. Significant discussion is provided due to the importance of ESD power clamps in analog and digital ESD design.

In Chapter 9, the system-level issues associated with EOS in chips, printed circuit boards, and systems are discussed. EOS protection device classifications, symbols, and types for both over-voltage or over-current conditions are highlighted. System-level and system-like testing methods, such as IEC 61000-4-2, IEC 61000-4-5, and human metal model waveforms and methods, are reviewed. Examples for printed circuit board design for digital–analog systems are also provided. The EDA techniques and methods for ESD in analog design are also discussed. Methods such as design rule checking (DRC), layout versus schematic (LVS), and electrical rule checking (ERC) are used for both ESD and EOS checking and verification.

In Chapter 10, latchup in analog design is discussed and solutions to avoid digital noise from impacting analog circuitry are addressed. The spatial placement of digital and analog cores in a mixed signal chip as well as the guard rings between these domains are also explained. Moats, guard rings, and through-silicon via advantages and disadvantages as possible solutions to minimize both noise and latchup are highlighted. Special features, such as grounded wells, and decoupling capacitor issues and how they can lead to latchup in analog applications are also reviewed. In conclusion, I/O to I/O interactions as a function of standard cell-to-standard cell spacings are discussed. As technology spacings are reduced, cell-to-cell latchup will increase in importance in analog design.

In Chapter 11, ESD and EOS libraries and documents for an analog or mixed signal technology are discussed. The discussion includes a plethora of items, from analog libraries, ESD library elements, Cadence^TM-based parameterized cells, Cadence-based hierarchical ESD designs, to ESD cookbooks. ESD and EOS documents for technology design manual, cookbooks, checklists, and design release processes are discussed. Control programs and documents for analog ESD design are highlighted. This includes ESD analog design “cookbooks” to assist design teams to determine the correct elements to use for a given circuit.

In Chapter 12, EDA techniques and methods for ESD, EOS, and latchup are discussed. Methods such as DRC, LVS and ERC are used for ESD, latchup, and EOS checking and verification. As time progresses, ESD CAD methods are being propagated to EOS CAD methods, to address ESD and EOS in the same design tool. The example of Calibre PERC^TM shows how the methods of ESD are being extended to the EOS issue. A key issue is the checking and verification of analog-to-digital cross domain sign lines. This trend will continue in the future.

This introductory text will hopefully open your interest in the field of ESD in analog design. To establish a stronger knowledge of ESD protection, it is advisable to read other texts such as ESD Basics: From Semiconductor Manufacturing to Product Use, ESD: Physics and Devices, ESD: Circuits and Technology, ESD: RF Circuits and Technology, ESD: Failure Mechanisms and Models, ESD: Design and Synthesis, EOS: Devices, Circuits and Systems, and Latchup.

Enjoy the text, and enjoy the subject of ESD design in analog devices, circuitry, and systems.