Figures
1-3 Example System
1-4 Packet Format When the Source and Destination Ports Are In the Same Subnet
1-5 Packet Format When the Source and Destination Ports Are In Different Subnets
1-6 Sample System Block Diagram
2-1 Each MA Accesses Its Manager's Attributes
3-1 QP Context
3-2 Example Path Maximum Transfer Unit Size
3-3 Packet Injection Delay Example
3-4 Example Scenario (left half of illustration)
3-5 Example Scenario (right half of illustration)
4-1 QP Basics
4-3 Encapsulated EtherType Packet Format
5-5 The Atomic Fetch and Add Operation
5-6 The Atomic Compare and Swap If Equal Operation
5-7 RQ's Handling of an Inbound Send Operation
6-2 CA Layers Handling Outbound Request
6-3 Layers
6-6 CA Receives Request Packet and Issues Response Packet
6-7 Differential Electrical Link
6-8 Fiber Link
6-9 Link/Physical Layer Interface
6-11 Virtual Lanes
7-1 Intra-Subnet Packet Format
7-2 LID's Purpose: Packet Routing Within Subnet
8-1 Inter-Subnet Packet Format
8-2 Inter-Subnet Packet Example
8-3 Basic GID Format
8-4 Unicast GID Address Format
8-5 Link-Local Unicast GID Format
8-6 Site-Local Unicast GID Format
8-7 Multicast Global GID Format
8-8 EUI-64 Format
10-1 RC/UC Connection Establishment
10-2 Connection Establishment Message Exchange
10-3 QP Basics
11-2 Requester QP's SQ Logic PSN Usage
11-3 Responder QP's RQ Logic Request PSN Verification
12-1 The QP State Machine
13-1 RD RDCs
13-2 Relaxed RDMA Read Ordering Example
15-1 Pages Assigned by OS Are Not Necessarily Contiguous
15-3 Window Concept
16-1 P_Key Format
16-2 M_Key Compare
16-3 M_KeyLeasePeriod, M_KeyViolations and M_KeyViolations Trap
16-4 BM/BMA/MME/CME Relationships
16-5 B_Key Compare
16-6 B_KeyLeasePeriod, B_KeyViolations and B_KeyViolations Trap
17-1 Relationship of SQ Start PSN and RQ ePSN at Startup
17-2 SQ Logic's View of PSN in Ack Packets
17-3 RQ Logic's View of PSN in Request Packets
17-4 Base Transport Header Fields
17-5 Send Request Packet Format
17-6 Ack Packet Format
17-7 RDMA Write Request Packet Format
17-8 RDMA Read Request Packet Format
17-9 RDMA Read Response Packet Format
17-10 Atomic Compare and Swap If Equal Request Packet Format
17-11 Atomic Acknowledge Packet Format
17-12 Message Transfer Overview
17-13 Requester QP's SQ Logic Ack/Response Processing
17-14 Ack Coalescing and an RDMA Read or Atomic Response Lost in Fabric
17-15 Transport Timer
17-16 Responder QP RQ Logic's View of Request Packet PSN
17-17 Requester QP SQ Logic's View of Response Packet PSN
17-18 MSN + Credit Count = LSN
17-19 Requester QP's SQ Logic Credit Recovery and Credit Check
17-20 Responder QP's RQ Logic Credit Calculation
17-21 MSN Usage on First Message Transmit
17-22 MSN Used To Retire Multiple SQ WQEs
17-23 MSN and RDMA Read and Atomic Operations
17-24 SQ Logic's Validation of a Response
17-25 Packet Header Validation
18-1 UC and UD Packet Header Validation Process
19-1 QP Type Overview
19-2 RD Scenario
19-3 Example RD Scheduler
19-4 Scenario One
19-6 Scenario Two
19-7 Requester Issuance of Resync and Handling Resync Ack
20-1 UD QPs
21-1 LRH:LNH Defines Packet Type
21-3 Raw Ethernet Packet Format
22-1 Switch Performing a Multicast
22-2 Multicast UD Packet Arrives at a CA Port
23-1 QP or EEC APM State Machine
24-1 Paths with Non-Uniform Transfer Speeds
25-1 The Link Layer in a CAs, Switches, and Routers
25-3 Local Route Header
25-4 CA Port's Transmitter and Receiver Are Shared Resources
25-5 Multiple Transmit/Receive Buffer Pairs
25-6 Example Packet Transit from Source to Destination
25-7 Common Format of High- and Low-Priority VL Arbitration Tables
25-9 High-Priority Limit
25-10 Example Data VL Arbitration Scenario
25-11 Example Flow Control Scenario
25-12 Example Flow Control Scenario (continued)
25-13 Example Flow Control Receive Buffer Full Scenario
25-14 Example Flow Control FCCL Rollover Scenario
25-15 Fields Excluded from ICRC in Local Packet's ICRC Calculation
25-16 Fields Excluded from ICRC Calculation in Global Packet's ICRC Calculation
25-17 All Fields Are Included in VCRC Calculation
25-18 Physical Layer/Link Layer Interface
25-19 Packet Receive State Machine
25-20 Link Layer's Data Packet Check
25-21 Link Layer's Link Packet Check
25-22 Switch Port Zero Is Its Management Port
25-23 Packet Switching
25-24 Receiving Port's Actions
25-25 Exit Port's Actions
25-26 Link Layer to Link Layer Transfer
25-27 Switch SLtoVLMappingTable Operation
25-28 Linear Forwarding Table Structure
25-29 Switch RFT Has One Entry per Port (port connected to fabric has no entry)
25-30 Switch MFT Structure
25-31 Switch Performing a Multicast
25-32 Router Layers
26-2 Cable Port Signals
26-4 Differential Transmitter/Receiver
26-5 LVDS (Low-Voltage Differential Signal) Eye Diagram
26-6 Eye Diagram Jitter Indication
26-7 Eye Diagram Noise/Attenuation Indication
26-8 Interface Between Link and Physical Layers
26-9 XmitControl and XmitStream
26-10 RcvControl and RcvStream
26-11 Physical Layer Transmit and Receive Logic
26-12 1X Byte-Striping
26-13 4X Byte-Striping
26-14 12X Byte-Striping
26-15 Preparing 8-bit Character for Encode
26-16 8-bit/10-bit Encoding
26-17 Example 8-bit/10-bit Encodings
26-18 Example 8-bit/10-bit Transmission
26-19 Control Characters
26-20 1x Packet Format
26-21 4x Packet Format
26-22 12x Packet Format
26-23 Skip Ordered Set
26-24 Receiver Logic's Front End
26-25 10-bit/8-bit Decoder per Lane
26-26 Example of Delayed Disparity Error Detection
26-27 Example of 12x Byte Un-Striping
26-28 Link Training State Machine
26-29 Polling Substates
26-30 TS1 Ordered Set (aka the beacon sequence)
26-31 Configuration State
26-32 TS2 Ordered Set
26-33 Recovery Substates
26-34 Sleeping substates
26-35 Receiver's Link De-Skew Logic
26-36 Repeater Block Diagram
27-1 Relationship of the SM, SMIs, and SMAs
28-1 A MAD Is Exactly 256 Bytes in Length
29-1 P_KeyTable Attribute Programming
29-2 PortInfo.DiagCode Attribute
29-3 VendorDiag Attribute
30-1 SM State Diagram
30-2 Discovering State
30-3 Master State Diagram (part 1)
30-4 Master State Diagram (part 2)
30-5 Standby State Diagram (part 1)
30-6 Standby State Diagram (part 2)
31-1 At Startup, No LIDs Assigned and Forwarding Tables Not Programmed
31-2 SMI Processing Directed-Route SMP Request Packet When HopPointer = HopCount
31-3 SMI Processing Directed-Route SMP Request Packet When Hop Count ≠ 0 and HopCount > HopPointer
31-4 SMI Processing Directed-Route SMP Request Packet When HopPointer > HopCount
31-5 SMI Processing Directed-Route SMP Response Packet When HopCount ≠ 0 and HopPointer > 1
31-6 SMI Processing Directed-Route SMP Response Packet When HopPointer = 1
31-8 Latter Half of Path Unaddressable
31-9 Initial Half of Path Unaddressable
31-10 Middle Portion of Path Unaddressable
32-1 Relationship of GSMs, GSAs, and GSIs
32-2 GSI Distributes Incoming GMPs to Destination GSA
33-1 RA Formats
33-2 Multi-Packet SA Response Example
33-3 Example Multi-Packet SA Request
34-1 IBA Module/Chassis Interconnect
34-3 Major Baseboard Management Elements (Actively Managed Chassis)
34-4 Passively Managed Chassis
34-5 Module Baseboard Management Elements
36-1 Communications Establishment Message Exchange
36-2 Communications Management Overview
36-3 Peer-to-Peer With Same ServiceID
36-4 Active Client to Passive Server with Third-Party Redirector
37-1 IOU, IOCs, and TCA