8.1 Introduction

The advent of 5G communications and the convergence with the Internet of Things (IoT) require next‐generation energy‐efficient devices which can integrate into our daily life. From autonomous cars to drones, entertainment, defense technologies, health services and low‐power pervasive radio frequency (RF) communication, technology enablers incorporating large‐scale‐integration chips with extremely low power consumption are in huge need [1]. At the transistor level, one of the main requirements is to achieve very steep devices operating at supply voltages (V_dd) less than 0.5 V. Therefore, tunneling field effect transistors (TFETs) are being explored as the most promising devices which can answer this demand and help in reducing power consumption and boosting performance [2,3].

In this chapter, we try to show the importance of molecular beam epitaxy (MBE) as an ideal technique for making next‐generation low‐power tunneling devices. We start with a brief introduction of the TFET working principle and its main advantage over the traditional metal–oxide–semiconductor field effect transistor (MOSFET). Then, we show how III–V properties and their capability to offer different band alignments make them promising alternatives to Si in TFETs. After showing an example of an ideal MBE production cluster for complementary metal–oxide–semiconductor (CMOS) technology, we discuss the main challenges encountered during the epitaxial growth of III–V tunneling devices and how MBE is helping in solving them.

8.2 TFET Working Principle

The basic working principle of a TFET, especially its switching mechanism, is compared with that of a traditional MOSFET in Figure 8.1. Unlike MOSFETs, where the source and drain have the same doping polarity (i.e. n+/i/n+ for n‐MOS or p+/i/p+ for p‐MOS), TFETs operate like a reversed p–i–n diode which is gate controlled (p+/i/n+ for n‐TFET and n+/i/p+ for p‐TFET). Here, we take the example of an n‐(MOS)TFET configuration with a gate stack over the intrinsic region.

For MOSFETs, the high gate voltage in the on‐state regime reduces the band energies of the channel region. This allows the flow of electrons from the conduction band (CB) of the n+ source region to the CB of the n+ drain region through the channel CB. In the off‐state regime, the potential barrier imposed by the channel prevents the flow of the majority of the CB source electrons. However, the very high‐energy electrons still succeed in being injected into the channel because of thermionic emission. This phenomenon is the core reason for the MOSFET sub‐threshold swing theoretical limit SS = ln(10)k_BT/q = 60 mV dec⁻¹ at room temperature, where T is the temperature, k_B is the Boltzmann constant, and q is the electron charge.

For TFETs, the behavior is different. In the on‐state regime, the high gate voltage suppresses the energy bands of the channel. But this time, the electrons reach the CB of the channel from the electron valence band (VB) of the p+ source region through an energy filtering mechanism by band‐to‐band tunneling (BTBT). In the off‐state, the tunneling path of these electrons becomes much longer (Figure 8.1). Compared to a MOSFET, the high‐energy carriers from the Fermi–Dirac tail are now eliminated by the bandgap in the p‐type source and thermionic emission is therefore absent. It is this steep change from short to long tunnel paths which allows TFETs to operate with SS < 60 mv dec⁻¹ at a potentially smaller V_dd and thus lower power than MOSFETs (see graph in Figure 8.1).

8.3 III–V Heterostructure for TFETs

The graph in Figure 8.1 clearly highlights the benefit of TFETs over MOSFETs for low‐power applications. However, it points out that in order for TFET to compete with MOSFET, I_on should be in the range of 300 µA µm⁻¹ for V_dd at 0.4 V, combined with a low SS over several decades of current while maintaining a low I_off of ∼50 pA µm⁻¹. With the target to find ideal materials to boost I_on in TFETs, Smets and Renard [4] compared the BTBT generation rate (G) as a function of the electric field (E) for different active‐layer materials of Esaki tunneling diodes [Figure 8.2(a)].

They demonstrated how III–V single‐material generation rates exceed the group IV ones for lower electric fields, basically due to the lower electron mass of the III–V compound and the switch from an indirect to a direct bandgap. Nevertheless, the use of a small bandgap combined with a low effective mass also facilitates both ambipolar and direct source–drain tunneling, which can induce high I_off. This can be solved by the use of III–V heterostructure configurations, where different materials are used in one system. This actually allows us to have a large bandgap at the channel–drain junction, for example, and solve the problem of any I_off degradation. Verreck and Webster [5] showed how the use of heterostructure TFET would help in solving this problem by comparing simulated I–V characteristics of InGaAs homostructure and heterostructure staggered gap (SG) InGaAs/GaAsSb TFETs [Figure 8.2(b)]. It is clear how the heterostructure TFET exhibits better SS than the homostructure one. Furthermore, the difference in the band alignment of the SG allows a decrease in the effective bandgap, which means a smaller electron tunneling length and thus a higher I_on in TFETs. This has also been expected for the broken gap (BG) configurations, which would further decrease the tunneling length and improve drive currents [5].

A summary of the reported TFETs with different configurations is compared with the state‐of‐the‐art MOSFET (modified from ref. [6]). Here we would like to mention that even if other promising TFETs are made using other techniques {e.g. exfoliation of 2D dichalcogenide materials [7] or carbon nanotubes (CNTs) [8]}, we only focus in our study on III–V TFEETs which are directly epitaxially grown on commercial substrates (see Figure 8.3).

We first notice that TFETs with a III–V heterostructure system lead to much better characteristics than a single‐material TFET, where a trade‐off between I_on and I_off is observed (i.e. either a high I_on with a high I_off or a decent I_off but a low I_on). However, it is clear that none of these devices meet the target input characteristics defined in Figure 8.1, due to many traditional device fabrication problems (channel growth, gate stack, contacts, etc.) [ 3, 4]. In the following section, we focus on the interface defects [like trap‐assisted tunneling (TAT) and Shockley–Read–Hall (SRH)] which are found at the tunnel junction of a TFET and play a unique role in device performance.

8.4 MBE for Beyond CMOS Technologies

In order to make III–V TFETs operate with the desired characteristics, the different material components constituting these devices – as well as the interfaces between them – should be at their best. One would need to carefully choose the exact growth machines for the different deposition steps. An example of a suitable machine to grow TFETs is the RIBER 200‐mm MBE production cluster installed at IMEC (Belgium) and depicted in detail in Figure 8.4. This cluster is used to study different kinds of FET devices and consists of one III–V MBE machine, one passivation chamber, and one oxide deposition machine. One of the main advantages of this cluster is the connection of the three machines under ultra‐high vacuum (UHV), which protects for instance the III–V channel surface from being oxidized before the gate stack deposition. This has been shown to be a critical step for lowering defects at the channel/gate interface (D_it, interface traps, etc.) [25].

Many studies in the literature on passivation and gate stack deposition on group IV and III–V surfaces (like GaAs, GaSb, InGaAs, etc.) using MBE technique can be found [26–28], and all these studies are of crucial importance for FET fabrication. Since our chapter highlights the MBE advantage for tunnel devices, we keep our discussion to III–V epitaxial growth of the tunneling active area, which is the main difference between TFET and other FET devices.

8.5 Doping

As mentioned, TAT, interface defects, phonon‐assisted tunneling, and band tails have all been shown to contribute to TFET performance [5]. Since doping, which is a point defect, can be the main source in all this, but also affects the system band configuration [29], studies on III–V doping and its effects on structural and tunneling properties are mandatory. As an example, we present in Figure 8.5 the effects of Si (Be) doping on the InGaAs (GaAsSb) layer grown on (001) InP in our III–V MBE tool [30]. It can be seen from the microscope images that the Si doping at high concentrations (>2e¹⁹ cm⁻³) leads to the deterioration of the InGaAs crystalline quality. Also, doping polarity deviation is observed at high concentrations due to the amphoteric nature of Si in InGaAs [31]. For the Be case, no clear surface degradation is observed at high doping concentrations. However, a p‐type doping saturation starts to be observed when the hole concentration reaches the range of 1e¹⁹ cm⁻² (nearly 820 °C for cell temperature).

Since our idea is to understand the growth influence on BTBT and separate it from other challenges (like gate stack or contacting), we have already proposed an easy BTBT measurement method using highly doped Esaki tunneling diodes to have accurate TFET predictions [32]. Using the above results, Esaki tunneling diodes are grown by the EPIPHY group (IEMN‐Lille) [30] with maximum Si n‐type doping of 1e¹⁹ cm⁻³ for InGaAs to avoid any III–V material degradation and carbon (C) instead of Be for p+ doping due to its low diffusivity and ability to achieve very high p‐type doping in III–V materials [33].

The SIMS dopant profiles of the different Esaki diode heterostructures fabricated using either Be or C‐doped GaAs_0.5Sb_0.5 are shown in Figure 8.6, along with the corresponding I–V characteristics. Si, Be, and C (even at high concentrations, ED3) exhibit slopes less than 10 nm dec⁻¹, which is considered a rough guide line to allow TFET operation with SS ≪ 60 mV dec⁻¹ [34]. This highlights the MBE advantage as a suitable doping control technique, which allows high doping concentrations with steep gradients. One can also see a similar J–V behavior by using either Be or C as p+ dopant in GaAsSb (ED1 and ED2). The peak current in ED3 shows a higher current value with a slight shift of the supply voltage. This is due to the higher doping concentration, which increases the band overlaps and reduces the tunneling length. This will also result in a decrease of the peak‐to‐valley ratio (PVCR) values with the doping concentration (ED1 = 13; ED2 = 13; ED3 = 5). The lower PVCR is caused by band tails due to random dopant fluctuations or extra defect states. Alternatively, it may also be due to a higher hole quasi‐Fermi level degeneracy. Ongoing simulation and experimental works, for example on quantifying TATs [35] and understanding Urbach tails [36] at different doping levels, aim to reveal the role of doping on BTBT behavior and thus provide deeper learning on experimental TFETs.

8.6 Tunneling Interface Engineering

Other sources of interface defects at the tunneling region are interface roughness and stoichiometry engineering during epitaxial growth of this interface. Studies have already reported the importance of growing by MBE sharp and defect‐free heterointerfaces for many electronic or photonic devices [37–40]. For TFETs, Zhu et al. [41] compared III–V TFET grown by MBE with different tunneling interface stoichiometry, as shown in Figure 8.7(a). They demonstrated that an InAs‐like interface is essential at the In_0.7Ga_0.3As/GaAs_0.35Sb_0.65 source channel tunneling region. This confines strain between the layers, inducing sharp interfaces with much better TFET characteristics compared to when a GaAs‐like interface is used. At a later stage, they proved that a defective interface would change the bandgap configuration of the system from a staggered bandgap to a broken bandgap [43].

Alternatively, Rajamohanan et al. [42] fabricated broken‐gap p‐type InAs/GaSb TFETs [Figure 8.7(b)]. From the I_DS–V_GS characteristics of the device, they noticed high I_off of 1 µA µm⁻¹ at 300 K, which reduces substantially at 150 K and I_on/I_off improves to 10⁴. They related the I_off degradation to the GaAsSb amorphous layer at the tunneling InAs/GaSb region and concluded that optimized MBE growth conditions will help in reducing tunneling defects, which would translate into better TFET performance.

In our group we have investigated tunneling interface engineering for both the staggered‐gap n+ (50 nm)/p+ (600 nm) In_0.53Ga_0.47As/GaAs_0.49Sb_0.51 [30] and broken‐gap InAs/GaSb systems [44] [Figures 8.8(a–c) and (d–e), respectively]. For the SG system, we have first studied the right growth conditions to grow GaAsSb and InGaAs separately at the same growth temperature [45]. Proper monitoring of the MBE shutter sequence was then used to grow InGaAs/GaAsSb Esaki diodes [30] with different interface stoichiometry [see e.g. the GaAs‐like interface in Figure 8.8(a)]. High‐angle annular dark field (HAADF)‐HR‐STEM was used to carefully probe the interface stoichiometry of samples with different interface engineering, as shown in the example of Figure 8.8(b). The diodes fabricated with different interface stoichiometry in the SG showed similar J–V behavior [Figure 8.8(c)]. We believe that since GaAsSb and InGaAs are nearly perfectly matched and grown pseudomorphically on InP, whatever the interface stoichiometry is, the interface can be kept strained and thus no relaxation or dislocations are introduced. However, this behavior was different for the BG system, where InAs and GaSb have a small 0.6% mismatch: as can be see from the I–V characteristics in Figure 8.8(e), a higher valley current is observed for the GaAs‐like interface with nearly no negative differential resistance (NDR). On the other hand, a clear NDR is observed for the InSb‐like case with a peak current reaching 8 µA µm⁻¹. The difference in the device behavior is linked to material degradation for the GaAs‐like interface case [see Figure 8.8(d)], which is related to strain relaxation by 60° misfit dislocations (MDs) at the InAs/GaSb tunneling interface [44].

8.7 MBE for III–V TFET Integration

Until now, we have discussed the problems which can be encountered during growth of the III–V active area without handling the challenges coming from the substrates. To reach industry, TFETs would need to be integrated on commercial substrates (like Si or GaAs), which usually have a large lattice mismatch with the device active area. Furthermore, nanowire (NW)‐based devices are believed to be the ideal architecture for TFET characteristics [46]. Hence, two main routes are being investigated in order to achieve III–V NW TFETs on commercial substrates. Here, we will focus on how MBE is helping in both approaches.

1. The first route is a ‘top‐down’ approach, depicted in the left part of Figure 8.9. It consists of growing the III–V heterostructures on commercial blanket substrates, followed by careful III–V NW etching to reach very narrow NW diameters (sub‐10 nm) [52]. The different studies on the MBE growth of tunneling diodes and TFETs on blanket substrates which are relevant for this route are also presented in Figure 8.9. The main epitaxial challenge is to decrease the defect density in the active area caused by the mismatch with the substrate. For instance, S. Datta's group from Pennsylvania State University [Figure 8.9(a)] used MBE to mitigate the detrimental defects by bending the vertically propagating defects coming from 60° MDs using compositionally graded layers [ 41, 43]. Thomas et al. [51] used buffer layers to grow InGaAs tunneling diodes on Si and reported nearly similar electrical results when compared to the lattice‐matched InP growth, highlighting the high III–V on Si crystal quality [Figure 8.9(b)]. In the same context, Liu et al. [47] and Bhatnagar et al. [50] both grew BG InAsGaSb Esaki diodes on GaAs [Figure 8.9(c)] and Si substrates [Figure 8.9(d)], respectively. By using 90° interfacial MDs at the III‐Sb buffer layer/substrate [the interface misfit (IMF) technique], the mismatch is revealed instantly at the first monolayer of growth. Both groups report severe device degradation when mismatched substrates are used, due to the high threading dislocation (TD) density. Since the IMF method already showed very low TD densities (<5×10⁵ cm⁻²) with MBE [53] due to the convenient energy formation of 90° MDs, especially when Sb‐rich substrate surfaces are used [54], this technique can offer an important promise for tunneling device integration on (001) Si substrates.
2. The second route is a ‘bottom‐up’ approach presented on the right‐side line of Figure 8.9. Here the idea is to grow ordered III–V NW directly on commercial substrates. With this technique, pattern substrates are used to predefine the location of the NW growth and thus selective area epitaxy (SAE) is required. Usually with MBE, catalyst‐assisted growth (Ga [55], Au [56], etc.) is used to induce selective III–V NW growth on (111) Si substrates. Even if NW tunneling devices were fabricated by transferring NWs grown by catalyst‐assisted MBE [57], this method is too complex and difficult to be implemented, mainly due to contamination problems of the catalyst. Recently, the MBE team of the Technical University of Munich (TUM) successfully demonstrated catalyst‐free SAE growth of In_xGa_1−xAs NW by MBE [Figure 8.9(e–g)] on pattern SiO₂/Si templates by carefully tuning the growth conditions and forbidding any deposition on the surface mask [48]. Using C‐AFM, they confirmed interband tunneling of MBE‐grown In(Ga)As NW diodes directly integrated on p‐Si substrate [Figure 8.9(h)] [49]. Another interesting approach for SAE growth of III–V TFET in pattern (001) substrates is the use of atomic hydrogen flux during the epitaxy to influence group III desorption [58] and assure the absence of growth on the surface mask [59].

With this technique, an InAs/Al_0.5Ga_0.5Sb vertical TFET on (001) GaAs was fabricated [60] with a large I_on of 433 µA µm⁻¹ at V_DS = V_GS = 0.5 V and SS of 71 mV dec⁻¹ at 77 K. Later, the same group reported the first dislocation‐free GaSb growth on large lattice‐mismatched GaAs [Figure 8.9(i, j)] [61], which interestingly opens the path for III–V NW TFET integration into (001) commercial substrates.

8.8 Conclusions and Perspectives

In summary, this chapter presents an overview of the main works done with MBE for the new era of TFET devices. After introducing the basic working principle of TFETs and highlighting their advantage on MOSFETs, we have shown how these new devices are still lacking behind their expected performance. By giving an example of an ideal MBE cluster to investigate different TFET material problems, we have focused our discussion on the epitaxial growth of the tunneling active area, which is the unique property of TFETs. First, we demonstrated that a unique understanding of the doping effect on both the structural and electrical results is of high importance to understand TFET performance. Then, we showed how careful MBE growth is helping to get defect‐free and high‐quality tunneling interface layers. Finally, we proved that MBE is being used in both ‘top‐down’ and ‘bottom‐up’ approaches to fabricate tunnel devices where the main challenges and solutions are addressed for the different techniques.

It is clear from this overview that many challenges need to be overcome in order to integrate III–V TFETs on large‐area commercial substrates. However, we highlight in this work the main challenges that need to be addressed and how one can work to solve them using the MBE technique. Finally, even though we have tackled in our work the importance of III–V TFETs, we believe that MBE will further offer new insights and solutions for the next generation of 2D materials, pushing by this the CMOS technology roadmap through MX₂ TFET devices onto Si substrates.

Acknowledgments

The author would like to thank all the IMEC TFET team members, especially Devin Verreck, Quentin Smets, and C. Merckling, for fruitful discussions and support of this overview.

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