Chapter 15, “SPU Assembly Language,” presented SPU assembly coding in depth, but there wasn’t enough room to add details related to the timing and pipeline usage of the individual instructions. In this case, pipeline usage refers to whether the instruction is processed by the even pipeline (0) or the odd pipeline (1). This is important to know; the SPU can issue two instructions in the same cycle if they are processed by different pipelines.
This appendix lists the SPU’s instructions in alphabetic order. Each entry shows the number of clock cycles required by the instruction (latency), which pipeline it uses (0 or 1), and a description of the instruction’s purpose.
Table D.1. SPU Load/Store Instructions
Opcode | Latency | Pipeline | Purpose |
---|---|---|---|
| 2 | 0 | Add words in |
| 4 | 0 | Subtract bytes in |
| 2 | 0 | Add words in |
| 2 | 0 | Add halfwords in |
| 2 | 0 | Add halfwords in |
| 2 | 0 | Add words in |
| 2 | 0 | AND the values of |
| 2 | 0 | AND the bytes of |
| 2 | 0 | AND the values of |
| 2 | 0 | AND the halfwords of |
| 2 | 0 | AND the words of |
| 4 | 0 | Average of bytes in |
| 2 | 0 | Generate borrow from |
| 2 | 0 | Generate borrow from |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to ra if |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to sum of |
| 4 | 1 | Branch to the |
| 4 | 1 | Branch to |
| 4 | 1 | Branch to sum of |
| 4 | 1 | Branch to sum of |
| 4 | 1 | Branch to sum of |
| 4 | 1 | Branch to sum of |
| 4 | 1 | Branch to sum of |
| 4 | 1 | Create mask for byte insertion |
| 4 | 1 | Create mask for byte insertion |
| 4 | 1 | Create mask for doubleword insertion |
| 4 | 1 | Create mask for doubleword insertion |
| 2 | 0 | Compare equality of words in |
| 2 | 0 | Compare equality of bytes in |
| 2 | 0 | Compare equality of bytes in |
| 2 | 0 | Compare equality of halfwords in |
| 2 | 0 | Compare equality of halfwords in |
| 2 | 0 | Compare equality of words in |
| 7 | 0 | Convert float in |
| 7 | 0 | Convert float in |
| 2 | 0 | Generate carry vector from |
| 2 | 0 | Return if words in |
| 2 | 0 | Return if bytes in |
| 2 | 0 | Return if bytes in |
| 2 | 0 | Return if halfwords in |
| 2 | 0 | Return if halfwords in |
| 2 | 0 | Return if words in |
| 2 | 0 | Generate carry vector from |
| 4 | 1 | Create mask for halfword insertion |
| 4 | 1 | Create mask for halfword insertion |
| 2 | 0 | Return if words in |
| 2 | 0 | Return if bytes in |
| 2 | 0 | Return if bytes in |
| 2 | 0 | Return if halfwords in |
| 2 | 0 | Return if halfwords in |
| 2 | 0 | Return if words in |
| 2 | 0 | Count 0s preceding the first 1 in |
| 4 | 0 | Count number of 1s in each byte of |
| 7 | 0 | Convert signed integer in |
| 7 | 0 | Convert unsigned integer in |
| 4 | 1 | Create mask for word insertion |
| 4 | 1 | Create mask for word insertion |
| 13 | 0 | Add double-precision values in |
| 13 | 0 | Multiply double-precision values in |
| 13 | 0 | Multiply double-precision values in |
| 13 | 0 | Multiply double-precision values in |
| 13 | 0 | Multiply double-precision values in |
| 13 | 0 | Multiply double-precision values in |
| 13 | 0 | Subtract double-precision value in |
| 4 | 1 | Ensures LS data is current before external accessing |
| 2 | 0 | Return 1 if |
| 6 | 0 | Add single-precision values in |
| 2 | 0 | Compare floating-point equality of |
| 2 | 0 | Return if floating-point |
| 2 | 0 | Compare floating-point equality of |
| 2 | 0 | Return if floating-point magnitude of |
| 13 | 0 | Convert |
| 7 | 0 | Floating-point interpolate between |
| 6 | 0 | Multiply floating-point values in |
| 6 | 0 | Multiply floating-point values in |
| 6 | 0 | Multiply floating-point values in |
| 6 | 0 | Multiply floating-point values in |
| 13 | 0 | Round |
| 4 | 1 | Floating-point reciprocal estimate |
| 4 | 1 | Floating-point reciprocal absolute square-root estimate |
| 6 | 0 | Subtract floating-point values in |
| 13 | 0 | Move floating point status and control register to |
| 7 | 0 | Move |
| 4 | 1 | Form select mask for words |
| 4 | 1 | Form select mask for bytes |
| 4 | 1 | Form select mask for bytes with |
| 4 | 1 | Form select mask for halfwords |
| 4 | 1 | Concatenate LSBs of each word in |
| 4 | 1 | Concatenate LSBs of each byte in |
| 4 | 1 | Concatenate LSBs of each halfword in |
| 15 | 1 | Hint that the branch at |
| 15 | 1 | Hint that the branch at |
| 15 | 1 | Hint for upcoming branch, prefetch |
| 15 | 1 | Hint that the branch at PC + |
| 2 | 0 | Halt if |
| 2 | 0 | Halt if |
| 2 | 0 | Halt if |
| 2 | 0 | Halt if |
| 2 | 0 | Halt if |
| 2 | 0 | Halt if |
| 2 | 0 | Load each word in |
| 2 | 0 | Load |
| 2 | 0 | Load each halfword in |
| 2 | 0 | Load the high halfword of each word in |
| 2 | 0 | OR the low halfword of each word in |
| 4 | 1 | Interrupt return |
| 4 | 1 | Interrupt return, disable |
| 4 | 1 | Interrupt return, enable |
| 0 | 1 | No operation (pipeline 1) |
| 6 | 1 | Load quadword from |
| 6 | 1 | Load quadword from |
| 6 | 1 | Load quadword from |
| 6 | 1 | Load quadword from |
| 6 | 1 | Move special-purpose register |
| 7 | 0 | Multiply low halfwords in |
| 7 | 0 | Multiply signed words in |
| 7 | 0 | Multiply high halfwords of |
| 7 | 0 | Multiply high halfwords of |
| 7 | 0 | Multiply high halfwords of |
| 7 | 0 | Multiply unsigned high halfwords of |
| 7 | 0 | Multiply unsigned high halfwords of |
| 7 | 0 | Multiply low halfwords in |
| 7 | 0 | Multiply low halfwords in |
| 7 | 0 | Multiply unsigned low halfwords in |
| 7 | 0 | Multiply unsigned low halfwords in |
| 6 | 1 | Move |
| 2 | 0 | NAND the values of |
| 0 | 0 | No operation (pipeline 0) |
| 2 | 0 | NOR the values of |
| 2 | 0 | OR the values of |
| 2 | 0 | OR the bytes of |
| 2 | 0 | OR the values of |
| 2 | 0 | OR the halfwords of |
| 2 | 0 | OR the words of |
| 4 | 1 | OR the words of |
| 6 | 1 | Read capacity of channel |
| 6 | 1 | Read data from channel |
| 4 | 0 | Rotate bits in words of |
| 4 | 0 | Rotate bits in halfwords of |
| 4 | 0 | Rotate bits in halfwords of |
| 4 | 0 | Rotate bits in halfwords of |
| 4 | 0 | Rotate bits in halfwords of |
| 4 | 0 | Rotate bits in words of |
| 4 | 0 | Shift bits in words of |
| 4 | 0 | Shift bits in words of ra right according to |
| 4 | 0 | Shift bits in halfwords of |
| 4 | 0 | Shift bits in halfwords of |
| 4 | 0 | Shift bits in words of |
| 4 | 0 | Shift bits in words of |
| 4 | 1 | Rotate entire |
| 4 | 1 | Rotate entire |
| 4 | 1 | Rotate entire |
| 4 | 1 | Rotate entire |
| 4 | 1 | Rotate entire |
| 4 | 1 | Shift entire |
| 4 | 1 | Shift entire |
| 4 | 1 | Shift entire |
| 4 | 1 | Shift entire |
| 4 | 1 | Shift entire |
| 2 | 0 | Select bits from |
| 2 | 0 | Subtract words in |
| 2 | 0 | Subtract halfwords in |
| 2 | 0 | Subtract halfwords in |
| 2 | 0 | Subtract words in |
| 2 | 0 | Subtract words in |
| 4 | 0 | Shift bits in words of |
| 4 | 0 | Shift bits in halfwords of |
| 4 | 0 | Shift bits in halfwords of |
| 4 | 0 | Shift bits in words of |
| 4 | 1 | Shift entire |
| 4 | 1 | Shift entire |
| 4 | 1 | Shift entire |
| 4 | 1 | Shift entire |
| 4 | 1 | Shift entire |
| 4 | 1 | Form |
| 4 | 1 | Halt the SPU and send stop signal to PPU |
| 4 | 1 | Halt the SPU and send signal (can be used as breakpoint) |
| 6 | 1 | Store quadword from register |
| 6 | 1 | Store quadword from register |
| 6 | 1 | Store quadword from register |
| 6 | 1 | Store quadword from register |
| 4 | 0 | Add bytes in |
| 4 | 1 | Force SPU to complete all store operations before continuing |
| 4 | 1 | Force SPU to complete store and channel operations |
| 6 | 1 | Write data from |
| 2 | 0 | XOR the values of |
| 2 | 0 | XOR the bytes of |
| 2 | 0 | XOR the halfwords of |
| 2 | 0 | XOR the words of |
| 2 | 0 | Sign extend bytes in |
| 2 | 0 | Sign extend halfwords in |
| 2 | 0 | Sign extend words in |
[1] The double-precision math instructions ( |
3.139.90.172