Appendix B
Exception Type Quick Reference
B.1. Exception Types
The exception types and corresponding control registers are listed in Table B.1:
Table B.1
Exception types and associated enable control registers
| Exception type | Name | Priority (word address) | Enable |
| 1 | Reset | −3 | Always |
| 2 | NMI | −2 | Always |
| 3 | HardFault | −1 | Always |
| 11 | SVCall | Programmable (0xE000ED1C, byte 3) | Always |
| 14 | PendSV | Programmable (0xE000ED20, byte 2) | Always |
| 15 | SYSTICK | Programmable (0xE000ED20, byte 3) | SYSTICK Control and Status Register (SysTick->CTRL) |
| 16 | Interrupt #0 | Programmable (0xE000E400, byte 0) | NVIC SETENA0 (0xE000E100, bit 0) |
| 17 | Interrupt #1 | Programmable (0xE000E400, byte 1) | NVIC SETENA0 (0xE000E100, bit 1) |
| 18 | Interrupt #2 | Programmable (0xE000E400, byte 2) | NVIC SETENA0 (0xE000E100, bit 2) |
| 19 | Interrupt #3 | Programmable (0xE000E400, byte 3) | NVIC SETENA0 (0xE000E100, bit 3) |
| 20 | Interrupt #4 | Programmable (0xE000E404, byte 0) | NVIC SETENA0 (0xE000E100, bit 4) |
| 21 | Interrupt #5 | Programmable (0xE000E404, byte 1) | NVIC SETENA0 (0xE000E100, bit 5) |
| 22–31 | Interrupt #6–#31 | Programmable (0xE000E404–0xE000E41C) | NVIC SETENA0 (0xE000E100, bit 6–bit 31) |
B.2. Stack Frame Layout (Stack Contents After Exception Stacking)
Table B.2 describes the layout of a stack frame in the stack memory after an exception stacking sequence is carried out. This information is useful for extracting stacked data within the exception handler.
Depending on the Stack Pointer (SP) value before the exception has taken place, the previous SP can be either the new SP value plus 32 or the new SP value plus 36: If the previous SP was aligned to a double-word aligned address boundary, then the previous SP is new SP + 32. Otherwise, a padding word would be allocated before stacking and therefore the previous SP is new SP + 36.
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